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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (C) 2016 Broadcom Corporation
0003  *
0004  * This file contains the Northstar2 IOMUX driver that supports group
0005  * based PINMUX configuration. The PWM is functional only when the
0006  * corresponding mfio pin group is selected as gpio.
0007  */
0008 
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/pinctrl/pinconf.h>
0013 #include <linux/pinctrl/pinconf-generic.h>
0014 #include <linux/pinctrl/pinctrl.h>
0015 #include <linux/pinctrl/pinmux.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/slab.h>
0018 
0019 #include "../core.h"
0020 #include "../pinctrl-utils.h"
0021 
0022 #define NS2_NUM_IOMUX           19
0023 #define NS2_NUM_PWM_MUX         4
0024 
0025 #define NS2_PIN_MUX_BASE0       0x00
0026 #define NS2_PIN_MUX_BASE1       0x01
0027 #define NS2_PIN_CONF_BASE       0x02
0028 #define NS2_MUX_PAD_FUNC1_OFFSET    0x04
0029 
0030 #define NS2_PIN_SRC_MASK        0x01
0031 #define NS2_PIN_PULL_MASK       0x03
0032 #define NS2_PIN_DRIVE_STRENGTH_MASK 0x07
0033 
0034 #define NS2_PIN_PULL_UP         0x01
0035 #define NS2_PIN_PULL_DOWN       0x02
0036 
0037 #define NS2_PIN_INPUT_EN_MASK       0x01
0038 
0039 /*
0040  * Northstar2 IOMUX register description
0041  *
0042  * @base: base address number
0043  * @offset: register offset for mux configuration of a group
0044  * @shift: bit shift for mux configuration of a group
0045  * @mask: mask bits
0046  * @alt: alternate function to set to
0047  */
0048 struct ns2_mux {
0049     unsigned int base;
0050     unsigned int offset;
0051     unsigned int shift;
0052     unsigned int mask;
0053     unsigned int alt;
0054 };
0055 
0056 /*
0057  * Keep track of Northstar2 IOMUX configuration and prevent double
0058  * configuration
0059  *
0060  * @ns2_mux: Northstar2 IOMUX register description
0061  * @is_configured: flag to indicate whether a mux setting has already
0062  * been configured
0063  */
0064 struct ns2_mux_log {
0065     struct ns2_mux mux;
0066     bool is_configured;
0067 };
0068 
0069 /*
0070  * Group based IOMUX configuration
0071  *
0072  * @name: name of the group
0073  * @pins: array of pins used by this group
0074  * @num_pins: total number of pins used by this group
0075  * @mux: Northstar2 group based IOMUX configuration
0076  */
0077 struct ns2_pin_group {
0078     const char *name;
0079     const unsigned int *pins;
0080     const unsigned int num_pins;
0081     const struct ns2_mux mux;
0082 };
0083 
0084 /*
0085  * Northstar2 mux function and supported pin groups
0086  *
0087  * @name: name of the function
0088  * @groups: array of groups that can be supported by this function
0089  * @num_groups: total number of groups that can be supported by function
0090  */
0091 struct ns2_pin_function {
0092     const char *name;
0093     const char * const *groups;
0094     const unsigned int num_groups;
0095 };
0096 
0097 /*
0098  * Northstar2 IOMUX pinctrl core
0099  *
0100  * @pctl: pointer to pinctrl_dev
0101  * @dev: pointer to device
0102  * @base0: first IOMUX register base
0103  * @base1: second IOMUX register base
0104  * @pinconf_base: configuration register base
0105  * @groups: pointer to array of groups
0106  * @num_groups: total number of groups
0107  * @functions: pointer to array of functions
0108  * @num_functions: total number of functions
0109  * @mux_log: pointer to the array of mux logs
0110  * @lock: lock to protect register access
0111  */
0112 struct ns2_pinctrl {
0113     struct pinctrl_dev *pctl;
0114     struct device *dev;
0115     void __iomem *base0;
0116     void __iomem *base1;
0117     void __iomem *pinconf_base;
0118 
0119     const struct ns2_pin_group *groups;
0120     unsigned int num_groups;
0121 
0122     const struct ns2_pin_function *functions;
0123     unsigned int num_functions;
0124 
0125     struct ns2_mux_log *mux_log;
0126 
0127     spinlock_t lock;
0128 };
0129 
0130 /*
0131  * Pin configuration info
0132  *
0133  * @base: base address number
0134  * @offset: register offset from base
0135  * @src_shift: slew rate control bit shift in the register
0136  * @input_en: input enable control bit shift
0137  * @pull_shift: pull-up/pull-down control bit shift in the register
0138  * @drive_shift: drive strength control bit shift in the register
0139  */
0140 struct ns2_pinconf {
0141     unsigned int base;
0142     unsigned int offset;
0143     unsigned int src_shift;
0144     unsigned int input_en;
0145     unsigned int pull_shift;
0146     unsigned int drive_shift;
0147 };
0148 
0149 /*
0150  * Description of a pin in Northstar2
0151  *
0152  * @pin: pin number
0153  * @name: pin name
0154  * @pin_conf: pin configuration structure
0155  */
0156 struct ns2_pin {
0157     unsigned int pin;
0158     char *name;
0159     struct ns2_pinconf pin_conf;
0160 };
0161 
0162 #define NS2_PIN_DESC(p, n, b, o, s, i, pu, d)   \
0163 {                       \
0164     .pin = p,               \
0165     .name = n,              \
0166     .pin_conf = {               \
0167         .base = b,          \
0168         .offset = o,            \
0169         .src_shift = s,         \
0170         .input_en = i,          \
0171         .pull_shift = pu,       \
0172         .drive_shift = d,       \
0173     }                   \
0174 }
0175 
0176 /*
0177  * List of pins in Northstar2
0178  */
0179 static struct ns2_pin ns2_pins[] = {
0180     NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
0181     NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
0182     NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
0183     NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
0184     NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
0185     NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
0186     NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
0187     NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
0188     NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
0189     NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
0190     NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
0191     NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
0192     NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
0193     NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
0194     NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
0195     NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
0196     NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
0197     NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
0198     NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
0199     NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
0200     NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
0201     NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
0202     NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
0203     NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
0204     NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
0205     NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
0206     NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
0207     NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
0208     NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
0209     NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
0210     NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
0211     NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
0212     NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
0213     NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
0214     NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
0215     NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
0216     NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
0217     NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
0218     NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
0219     NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
0220     NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
0221     NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
0222     NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
0223     NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
0224     NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
0225     NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
0226     NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
0227     NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
0228     NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
0229     NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
0230     NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
0231     NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
0232     NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
0233     NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
0234     NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
0235     NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
0236     NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
0237     NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
0238     NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
0239     NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
0240     NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
0241     NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
0242     NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
0243     NS2_PIN_DESC(63, "qspi_wp", 2, 0x0, 31, 30, 27, 24),
0244     NS2_PIN_DESC(64, "qspi_hold", 2, 0x0, 23, 22, 19, 16),
0245     NS2_PIN_DESC(65, "qspi_cs", 2, 0x0, 15, 14, 11, 8),
0246     NS2_PIN_DESC(66, "qspi_sck", 2, 0x0, 7, 6, 3, 0),
0247     NS2_PIN_DESC(67, "uart3_sin", 2, 0x04, 31, 30, 27, 24),
0248     NS2_PIN_DESC(68, "uart3_sout", 2, 0x04, 23, 22, 19, 16),
0249     NS2_PIN_DESC(69, "qspi_mosi", 2, 0x04, 15, 14, 11, 8),
0250     NS2_PIN_DESC(70, "qspi_miso", 2, 0x04, 7, 6, 3, 0),
0251     NS2_PIN_DESC(71, "spi0_fss", 2, 0x08, 31, 30, 27, 24),
0252     NS2_PIN_DESC(72, "spi0_rxd", 2, 0x08, 23, 22, 19, 16),
0253     NS2_PIN_DESC(73, "spi0_txd", 2, 0x08, 15, 14, 11, 8),
0254     NS2_PIN_DESC(74, "spi0_sck", 2, 0x08, 7, 6, 3, 0),
0255     NS2_PIN_DESC(75, "spi1_fss", 2, 0x0c, 31, 30, 27, 24),
0256     NS2_PIN_DESC(76, "spi1_rxd", 2, 0x0c, 23, 22, 19, 16),
0257     NS2_PIN_DESC(77, "spi1_txd", 2, 0x0c, 15, 14, 11, 8),
0258     NS2_PIN_DESC(78, "spi1_sck", 2, 0x0c, 7, 6, 3, 0),
0259     NS2_PIN_DESC(79, "sdio0_data7", 2, 0x10, 31, 30, 27, 24),
0260     NS2_PIN_DESC(80, "sdio0_emmc_rst", 2, 0x10, 23, 22, 19, 16),
0261     NS2_PIN_DESC(81, "sdio0_led_on", 2, 0x10, 15, 14, 11, 8),
0262     NS2_PIN_DESC(82, "sdio0_wp", 2, 0x10, 7, 6, 3, 0),
0263     NS2_PIN_DESC(83, "sdio0_data3", 2, 0x14, 31, 30, 27, 24),
0264     NS2_PIN_DESC(84, "sdio0_data4", 2, 0x14, 23, 22, 19, 16),
0265     NS2_PIN_DESC(85, "sdio0_data5", 2, 0x14, 15, 14, 11, 8),
0266     NS2_PIN_DESC(86, "sdio0_data6", 2, 0x14, 7, 6, 3, 0),
0267     NS2_PIN_DESC(87, "sdio0_cmd", 2, 0x18, 31, 30, 27, 24),
0268     NS2_PIN_DESC(88, "sdio0_data0", 2, 0x18, 23, 22, 19, 16),
0269     NS2_PIN_DESC(89, "sdio0_data1", 2, 0x18, 15, 14, 11, 8),
0270     NS2_PIN_DESC(90, "sdio0_data2", 2, 0x18, 7, 6, 3, 0),
0271     NS2_PIN_DESC(91, "sdio1_led_on", 2, 0x1c, 31, 30, 27, 24),
0272     NS2_PIN_DESC(92, "sdio1_wp", 2, 0x1c, 23, 22, 19, 16),
0273     NS2_PIN_DESC(93, "sdio0_cd_l", 2, 0x1c, 15, 14, 11, 8),
0274     NS2_PIN_DESC(94, "sdio0_clk", 2, 0x1c, 7, 6, 3, 0),
0275     NS2_PIN_DESC(95, "sdio1_data5", 2, 0x20, 31, 30, 27, 24),
0276     NS2_PIN_DESC(96, "sdio1_data6", 2, 0x20, 23, 22, 19, 16),
0277     NS2_PIN_DESC(97, "sdio1_data7", 2, 0x20, 15, 14, 11, 8),
0278     NS2_PIN_DESC(98, "sdio1_emmc_rst", 2, 0x20, 7, 6, 3, 0),
0279     NS2_PIN_DESC(99, "sdio1_data1", 2, 0x24, 31, 30, 27, 24),
0280     NS2_PIN_DESC(100, "sdio1_data2", 2, 0x24, 23, 22, 19, 16),
0281     NS2_PIN_DESC(101, "sdio1_data3", 2, 0x24, 15, 14, 11, 8),
0282     NS2_PIN_DESC(102, "sdio1_data4", 2, 0x24, 7, 6, 3, 0),
0283     NS2_PIN_DESC(103, "sdio1_cd_l", 2, 0x28, 31, 30, 27, 24),
0284     NS2_PIN_DESC(104, "sdio1_clk", 2, 0x28, 23, 22, 19, 16),
0285     NS2_PIN_DESC(105, "sdio1_cmd", 2, 0x28, 15, 14, 11, 8),
0286     NS2_PIN_DESC(106, "sdio1_data0", 2, 0x28, 7, 6, 3, 0),
0287     NS2_PIN_DESC(107, "ext_mdio_0", 2, 0x2c, 15, 14, 11, 8),
0288     NS2_PIN_DESC(108, "ext_mdc_0", 2, 0x2c, 7, 6, 3, 0),
0289     NS2_PIN_DESC(109, "usb3_p1_vbus_ppc", 2, 0x34, 31, 30, 27, 24),
0290     NS2_PIN_DESC(110, "usb3_p1_overcurrent", 2, 0x34, 23, 22, 19, 16),
0291     NS2_PIN_DESC(111, "usb3_p0_vbus_ppc", 2, 0x34, 15, 14, 11, 8),
0292     NS2_PIN_DESC(112, "usb3_p0_overcurrent", 2, 0x34, 7, 6, 3, 0),
0293     NS2_PIN_DESC(113, "usb2_presence_indication", 2, 0x38, 31, 30, 27, 24),
0294     NS2_PIN_DESC(114, "usb2_vbus_present", 2, 0x38, 23, 22, 19, 16),
0295     NS2_PIN_DESC(115, "usb2_vbus_ppc", 2, 0x38, 15, 14, 11, 8),
0296     NS2_PIN_DESC(116, "usb2_overcurrent", 2, 0x38, 7, 6, 3, 0),
0297     NS2_PIN_DESC(117, "sata_led1", 2, 0x3c, 15, 14, 11, 8),
0298     NS2_PIN_DESC(118, "sata_led0", 2, 0x3c, 7, 6, 3, 0),
0299 };
0300 
0301 /*
0302  * List of groups of pins
0303  */
0304 
0305 static const unsigned int nand_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
0306     11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23};
0307 static const unsigned int nor_data_pins[] =  {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
0308     10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25};
0309 
0310 static const unsigned int gpio_0_1_pins[] = {24, 25};
0311 static const unsigned int pwm_0_pins[] = {24};
0312 static const unsigned int pwm_1_pins[] = {25};
0313 
0314 static const unsigned int uart1_ext_clk_pins[] = {26};
0315 static const unsigned int nor_adv_pins[] = {26};
0316 
0317 static const unsigned int gpio_2_5_pins[] = {27, 28, 29, 30};
0318 static const unsigned int pcie_ab1_clk_wak_pins[] = {27, 28, 29, 30};
0319 static const unsigned int nor_addr_0_3_pins[] = {27, 28, 29, 30};
0320 static const unsigned int pwm_2_pins[] = {27};
0321 static const unsigned int pwm_3_pins[] = {28};
0322 
0323 static const unsigned int gpio_6_7_pins[] = {31, 32};
0324 static const unsigned int pcie_a3_clk_wak_pins[] = {31, 32};
0325 static const unsigned int nor_addr_4_5_pins[] = {31, 32};
0326 
0327 static const unsigned int gpio_8_9_pins[] = {33, 34};
0328 static const unsigned int pcie_b3_clk_wak_pins[] = {33, 34};
0329 static const unsigned int nor_addr_6_7_pins[] = {33, 34};
0330 
0331 static const unsigned int gpio_10_11_pins[] = {35, 36};
0332 static const unsigned int pcie_b2_clk_wak_pins[] = {35, 36};
0333 static const unsigned int nor_addr_8_9_pins[] = {35, 36};
0334 
0335 static const unsigned int gpio_12_13_pins[] = {37, 38};
0336 static const unsigned int pcie_a2_clk_wak_pins[] = {37, 38};
0337 static const unsigned int nor_addr_10_11_pins[] = {37, 38};
0338 
0339 static const unsigned int gpio_14_17_pins[] = {39, 40, 41, 42};
0340 static const unsigned int uart0_modem_pins[] = {39, 40, 41, 42};
0341 static const unsigned int nor_addr_12_15_pins[] = {39, 40, 41, 42};
0342 
0343 static const unsigned int gpio_18_19_pins[] = {43, 44};
0344 static const unsigned int uart0_rts_cts_pins[] = {43, 44};
0345 
0346 static const unsigned int gpio_20_21_pins[] = {45, 46};
0347 static const unsigned int uart0_in_out_pins[] = {45, 46};
0348 
0349 static const unsigned int gpio_22_23_pins[] = {47, 48};
0350 static const unsigned int uart1_dcd_dsr_pins[] = {47, 48};
0351 
0352 static const unsigned int gpio_24_25_pins[] = {49, 50};
0353 static const unsigned int uart1_ri_dtr_pins[] = {49, 50};
0354 
0355 static const unsigned int gpio_26_27_pins[] = {51, 52};
0356 static const unsigned int uart1_rts_cts_pins[] = {51, 52};
0357 
0358 static const unsigned int gpio_28_29_pins[] = {53, 54};
0359 static const unsigned int uart1_in_out_pins[] = {53, 54};
0360 
0361 static const unsigned int gpio_30_31_pins[] = {55, 56};
0362 static const unsigned int uart2_rts_cts_pins[] = {55, 56};
0363 
0364 #define NS2_PIN_GROUP(group_name, ba, off, sh, ma, al)  \
0365 {                           \
0366     .name = __stringify(group_name) "_grp",     \
0367     .pins = group_name ## _pins,            \
0368     .num_pins = ARRAY_SIZE(group_name ## _pins),    \
0369     .mux = {                    \
0370         .base = ba,             \
0371         .offset = off,              \
0372         .shift = sh,                \
0373         .mask = ma,             \
0374         .alt = al,              \
0375     }                       \
0376 }
0377 
0378 /*
0379  * List of Northstar2 pin groups
0380  */
0381 static const struct ns2_pin_group ns2_pin_groups[] = {
0382     NS2_PIN_GROUP(nand, 0, 0, 31, 1, 0),
0383     NS2_PIN_GROUP(nor_data, 0, 0, 31, 1, 1),
0384     NS2_PIN_GROUP(gpio_0_1, 0, 0, 31, 1, 0),
0385 
0386     NS2_PIN_GROUP(uart1_ext_clk, 0, 4, 30, 3, 1),
0387     NS2_PIN_GROUP(nor_adv, 0, 4, 30, 3, 2),
0388 
0389     NS2_PIN_GROUP(gpio_2_5, 0, 4, 28, 3, 0),
0390     NS2_PIN_GROUP(pcie_ab1_clk_wak, 0, 4, 28, 3, 1),
0391     NS2_PIN_GROUP(nor_addr_0_3, 0, 4, 28, 3, 2),
0392 
0393     NS2_PIN_GROUP(gpio_6_7, 0, 4, 26, 3, 0),
0394     NS2_PIN_GROUP(pcie_a3_clk_wak, 0, 4, 26, 3, 1),
0395     NS2_PIN_GROUP(nor_addr_4_5, 0, 4, 26, 3, 2),
0396 
0397     NS2_PIN_GROUP(gpio_8_9, 0, 4, 24, 3, 0),
0398     NS2_PIN_GROUP(pcie_b3_clk_wak, 0, 4, 24, 3, 1),
0399     NS2_PIN_GROUP(nor_addr_6_7, 0, 4, 24, 3, 2),
0400 
0401     NS2_PIN_GROUP(gpio_10_11, 0, 4, 22, 3, 0),
0402     NS2_PIN_GROUP(pcie_b2_clk_wak, 0, 4, 22, 3, 1),
0403     NS2_PIN_GROUP(nor_addr_8_9, 0, 4, 22, 3, 2),
0404 
0405     NS2_PIN_GROUP(gpio_12_13, 0, 4, 20, 3, 0),
0406     NS2_PIN_GROUP(pcie_a2_clk_wak, 0, 4, 20, 3, 1),
0407     NS2_PIN_GROUP(nor_addr_10_11, 0, 4, 20, 3, 2),
0408 
0409     NS2_PIN_GROUP(gpio_14_17, 0, 4, 18, 3, 0),
0410     NS2_PIN_GROUP(uart0_modem, 0, 4, 18, 3, 1),
0411     NS2_PIN_GROUP(nor_addr_12_15, 0, 4, 18, 3, 2),
0412 
0413     NS2_PIN_GROUP(gpio_18_19, 0, 4, 16, 3, 0),
0414     NS2_PIN_GROUP(uart0_rts_cts, 0, 4, 16, 3, 1),
0415 
0416     NS2_PIN_GROUP(gpio_20_21, 0, 4, 14, 3, 0),
0417     NS2_PIN_GROUP(uart0_in_out, 0, 4, 14, 3, 1),
0418 
0419     NS2_PIN_GROUP(gpio_22_23, 0, 4, 12, 3, 0),
0420     NS2_PIN_GROUP(uart1_dcd_dsr, 0, 4, 12, 3, 1),
0421 
0422     NS2_PIN_GROUP(gpio_24_25, 0, 4, 10, 3, 0),
0423     NS2_PIN_GROUP(uart1_ri_dtr, 0, 4, 10, 3, 1),
0424 
0425     NS2_PIN_GROUP(gpio_26_27, 0, 4, 8, 3, 0),
0426     NS2_PIN_GROUP(uart1_rts_cts, 0, 4, 8, 3, 1),
0427 
0428     NS2_PIN_GROUP(gpio_28_29, 0, 4, 6, 3, 0),
0429     NS2_PIN_GROUP(uart1_in_out, 0, 4, 6, 3, 1),
0430 
0431     NS2_PIN_GROUP(gpio_30_31, 0, 4, 4, 3, 0),
0432     NS2_PIN_GROUP(uart2_rts_cts, 0, 4, 4, 3, 1),
0433 
0434     NS2_PIN_GROUP(pwm_0, 1, 0, 0, 1, 1),
0435     NS2_PIN_GROUP(pwm_1, 1, 0, 1, 1, 1),
0436     NS2_PIN_GROUP(pwm_2, 1, 0, 2, 1, 1),
0437     NS2_PIN_GROUP(pwm_3, 1, 0, 3, 1, 1),
0438 };
0439 
0440 /*
0441  * List of groups supported by functions
0442  */
0443 
0444 static const char * const nand_grps[] = {"nand_grp"};
0445 
0446 static const char * const nor_grps[] = {"nor_data_grp", "nor_adv_grp",
0447     "nor_addr_0_3_grp", "nor_addr_4_5_grp", "nor_addr_6_7_grp",
0448     "nor_addr_8_9_grp", "nor_addr_10_11_grp", "nor_addr_12_15_grp"};
0449 
0450 static const char * const gpio_grps[] = {"gpio_0_1_grp", "gpio_2_5_grp",
0451     "gpio_6_7_grp", "gpio_8_9_grp", "gpio_10_11_grp", "gpio_12_13_grp",
0452     "gpio_14_17_grp", "gpio_18_19_grp", "gpio_20_21_grp", "gpio_22_23_grp",
0453     "gpio_24_25_grp", "gpio_26_27_grp", "gpio_28_29_grp",
0454     "gpio_30_31_grp"};
0455 
0456 static const char * const pcie_grps[] = {"pcie_ab1_clk_wak_grp",
0457     "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", "pcie_b2_clk_wak_grp",
0458     "pcie_a2_clk_wak_grp"};
0459 
0460 static const char * const uart0_grps[] = {"uart0_modem_grp",
0461     "uart0_rts_cts_grp", "uart0_in_out_grp"};
0462 
0463 static const char * const uart1_grps[] = {"uart1_ext_clk_grp",
0464     "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", "uart1_rts_cts_grp",
0465     "uart1_in_out_grp"};
0466 
0467 static const char * const uart2_grps[] = {"uart2_rts_cts_grp"};
0468 
0469 static const char * const pwm_grps[] = {"pwm_0_grp", "pwm_1_grp",
0470     "pwm_2_grp", "pwm_3_grp"};
0471 
0472 #define NS2_PIN_FUNCTION(func)              \
0473 {                           \
0474     .name = #func,                  \
0475     .groups = func ## _grps,            \
0476     .num_groups = ARRAY_SIZE(func ## _grps),    \
0477 }
0478 
0479 /*
0480  * List of supported functions
0481  */
0482 static const struct ns2_pin_function ns2_pin_functions[] = {
0483     NS2_PIN_FUNCTION(nand),
0484     NS2_PIN_FUNCTION(nor),
0485     NS2_PIN_FUNCTION(gpio),
0486     NS2_PIN_FUNCTION(pcie),
0487     NS2_PIN_FUNCTION(uart0),
0488     NS2_PIN_FUNCTION(uart1),
0489     NS2_PIN_FUNCTION(uart2),
0490     NS2_PIN_FUNCTION(pwm),
0491 };
0492 
0493 static int ns2_get_groups_count(struct pinctrl_dev *pctrl_dev)
0494 {
0495     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0496 
0497     return pinctrl->num_groups;
0498 }
0499 
0500 static const char *ns2_get_group_name(struct pinctrl_dev *pctrl_dev,
0501                       unsigned int selector)
0502 {
0503     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0504 
0505     return pinctrl->groups[selector].name;
0506 }
0507 
0508 static int ns2_get_group_pins(struct pinctrl_dev *pctrl_dev,
0509                   unsigned int selector, const unsigned int **pins,
0510                   unsigned int *num_pins)
0511 {
0512     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0513 
0514     *pins = pinctrl->groups[selector].pins;
0515     *num_pins = pinctrl->groups[selector].num_pins;
0516 
0517     return 0;
0518 }
0519 
0520 static void ns2_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
0521                  struct seq_file *s, unsigned int offset)
0522 {
0523     seq_printf(s, " %s", dev_name(pctrl_dev->dev));
0524 }
0525 
0526 static const struct pinctrl_ops ns2_pinctrl_ops = {
0527     .get_groups_count = ns2_get_groups_count,
0528     .get_group_name = ns2_get_group_name,
0529     .get_group_pins = ns2_get_group_pins,
0530     .pin_dbg_show = ns2_pin_dbg_show,
0531     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0532     .dt_free_map = pinctrl_utils_free_map,
0533 };
0534 
0535 static int ns2_get_functions_count(struct pinctrl_dev *pctrl_dev)
0536 {
0537     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0538 
0539     return pinctrl->num_functions;
0540 }
0541 
0542 static const char *ns2_get_function_name(struct pinctrl_dev *pctrl_dev,
0543                      unsigned int selector)
0544 {
0545     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0546 
0547     return pinctrl->functions[selector].name;
0548 }
0549 
0550 static int ns2_get_function_groups(struct pinctrl_dev *pctrl_dev,
0551                    unsigned int selector,
0552                    const char * const **groups,
0553                    unsigned int * const num_groups)
0554 {
0555     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0556 
0557     *groups = pinctrl->functions[selector].groups;
0558     *num_groups = pinctrl->functions[selector].num_groups;
0559 
0560     return 0;
0561 }
0562 
0563 static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl,
0564               const struct ns2_pin_function *func,
0565               const struct ns2_pin_group *grp,
0566               struct ns2_mux_log *mux_log)
0567 {
0568     const struct ns2_mux *mux = &grp->mux;
0569     int i;
0570     u32 val, mask;
0571     unsigned long flags;
0572     void __iomem *base_address;
0573 
0574     for (i = 0; i < NS2_NUM_IOMUX; i++) {
0575         if ((mux->shift != mux_log[i].mux.shift) ||
0576             (mux->base != mux_log[i].mux.base) ||
0577             (mux->offset != mux_log[i].mux.offset))
0578             continue;
0579 
0580         /* if this is a new configuration, just do it! */
0581         if (!mux_log[i].is_configured)
0582             break;
0583 
0584         /*
0585          * IOMUX has been configured previously and one is trying to
0586          * configure it to a different function
0587          */
0588         if (mux_log[i].mux.alt != mux->alt) {
0589             dev_err(pinctrl->dev,
0590                 "double configuration error detected!\n");
0591             dev_err(pinctrl->dev, "func:%s grp:%s\n",
0592                 func->name, grp->name);
0593             return -EINVAL;
0594         }
0595 
0596         return 0;
0597     }
0598     if (i == NS2_NUM_IOMUX)
0599         return -EINVAL;
0600 
0601     mask = mux->mask;
0602     mux_log[i].mux.alt = mux->alt;
0603     mux_log[i].is_configured = true;
0604 
0605     switch (mux->base) {
0606     case NS2_PIN_MUX_BASE0:
0607         base_address = pinctrl->base0;
0608         break;
0609 
0610     case NS2_PIN_MUX_BASE1:
0611         base_address = pinctrl->base1;
0612         break;
0613 
0614     default:
0615         return -EINVAL;
0616     }
0617 
0618     spin_lock_irqsave(&pinctrl->lock, flags);
0619     val = readl(base_address + grp->mux.offset);
0620     val &= ~(mask << grp->mux.shift);
0621     val |= grp->mux.alt << grp->mux.shift;
0622     writel(val, (base_address + grp->mux.offset));
0623     spin_unlock_irqrestore(&pinctrl->lock, flags);
0624 
0625     return 0;
0626 }
0627 
0628 static int ns2_pinmux_enable(struct pinctrl_dev *pctrl_dev,
0629                  unsigned int func_select, unsigned int grp_select)
0630 {
0631     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0632     const struct ns2_pin_function *func;
0633     const struct ns2_pin_group *grp;
0634 
0635     if (grp_select >= pinctrl->num_groups ||
0636         func_select >= pinctrl->num_functions)
0637         return -EINVAL;
0638 
0639     func = &pinctrl->functions[func_select];
0640     grp = &pinctrl->groups[grp_select];
0641 
0642     dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
0643         func_select, func->name, grp_select, grp->name);
0644 
0645     dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
0646         grp->mux.offset, grp->mux.shift, grp->mux.alt);
0647 
0648     return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
0649 }
0650 
0651 static int ns2_pin_set_enable(struct pinctrl_dev *pctrldev, unsigned int pin,
0652                 u16 enable)
0653 {
0654     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
0655     struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
0656     unsigned long flags;
0657     u32 val;
0658     void __iomem *base_address;
0659 
0660     base_address = pinctrl->pinconf_base;
0661     spin_lock_irqsave(&pinctrl->lock, flags);
0662     val = readl(base_address + pin_data->pin_conf.offset);
0663     val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en);
0664 
0665     if (!enable)
0666         val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en;
0667 
0668     writel(val, (base_address + pin_data->pin_conf.offset));
0669     spin_unlock_irqrestore(&pinctrl->lock, flags);
0670 
0671     dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable);
0672     return 0;
0673 }
0674 
0675 static int ns2_pin_get_enable(struct pinctrl_dev *pctrldev, unsigned int pin)
0676 {
0677     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
0678     struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
0679     unsigned long flags;
0680     int enable;
0681 
0682     spin_lock_irqsave(&pinctrl->lock, flags);
0683     enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
0684     enable = (enable >> pin_data->pin_conf.input_en) &
0685             NS2_PIN_INPUT_EN_MASK;
0686     spin_unlock_irqrestore(&pinctrl->lock, flags);
0687 
0688     if (!enable)
0689         enable = NS2_PIN_INPUT_EN_MASK;
0690     else
0691         enable = 0;
0692 
0693     dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable);
0694     return enable;
0695 }
0696 
0697 static int ns2_pin_set_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
0698                 u32 slew)
0699 {
0700     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
0701     struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
0702     unsigned long flags;
0703     u32 val;
0704     void __iomem *base_address;
0705 
0706     base_address = pinctrl->pinconf_base;
0707     spin_lock_irqsave(&pinctrl->lock, flags);
0708     val = readl(base_address + pin_data->pin_conf.offset);
0709     val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift);
0710 
0711     if (slew)
0712         val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift;
0713 
0714     writel(val, (base_address + pin_data->pin_conf.offset));
0715     spin_unlock_irqrestore(&pinctrl->lock, flags);
0716 
0717     dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew);
0718     return 0;
0719 }
0720 
0721 static int ns2_pin_get_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
0722                 u16 *slew)
0723 {
0724     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
0725     struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
0726     unsigned long flags;
0727     u32 val;
0728 
0729     spin_lock_irqsave(&pinctrl->lock, flags);
0730     val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
0731     *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK;
0732     spin_unlock_irqrestore(&pinctrl->lock, flags);
0733 
0734     dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew);
0735     return 0;
0736 }
0737 
0738 static int ns2_pin_set_pull(struct pinctrl_dev *pctrldev, unsigned int pin,
0739                 bool pull_up, bool pull_down)
0740 {
0741     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
0742     struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
0743     unsigned long flags;
0744     u32 val;
0745     void __iomem *base_address;
0746 
0747     base_address = pinctrl->pinconf_base;
0748     spin_lock_irqsave(&pinctrl->lock, flags);
0749     val = readl(base_address + pin_data->pin_conf.offset);
0750     val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift);
0751 
0752     if (pull_up == true)
0753         val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift;
0754     if (pull_down == true)
0755         val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift;
0756     writel(val, (base_address + pin_data->pin_conf.offset));
0757     spin_unlock_irqrestore(&pinctrl->lock, flags);
0758 
0759     dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n",
0760         pin, pull_up, pull_down);
0761     return 0;
0762 }
0763 
0764 static void ns2_pin_get_pull(struct pinctrl_dev *pctrldev,
0765                  unsigned int pin, bool *pull_up,
0766                  bool *pull_down)
0767 {
0768     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
0769     struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
0770     unsigned long flags;
0771     u32 val;
0772 
0773     spin_lock_irqsave(&pinctrl->lock, flags);
0774     val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
0775     val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK;
0776     *pull_up = false;
0777     *pull_down = false;
0778 
0779     if (val == NS2_PIN_PULL_UP)
0780         *pull_up = true;
0781 
0782     if (val == NS2_PIN_PULL_DOWN)
0783         *pull_down = true;
0784     spin_unlock_irqrestore(&pinctrl->lock, flags);
0785 }
0786 
0787 static int ns2_pin_set_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
0788                 u32 strength)
0789 {
0790     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
0791     struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
0792     u32 val;
0793     unsigned long flags;
0794     void __iomem *base_address;
0795 
0796     /* make sure drive strength is supported */
0797     if (strength < 2 || strength > 16 || (strength % 2))
0798         return -ENOTSUPP;
0799 
0800     base_address = pinctrl->pinconf_base;
0801     spin_lock_irqsave(&pinctrl->lock, flags);
0802     val = readl(base_address + pin_data->pin_conf.offset);
0803     val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift);
0804     val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift;
0805     writel(val, (base_address + pin_data->pin_conf.offset));
0806     spin_unlock_irqrestore(&pinctrl->lock, flags);
0807 
0808     dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n",
0809         pin, strength);
0810     return 0;
0811 }
0812 
0813 static int ns2_pin_get_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
0814                  u16 *strength)
0815 {
0816     struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
0817     struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
0818     u32 val;
0819     unsigned long flags;
0820 
0821     spin_lock_irqsave(&pinctrl->lock, flags);
0822     val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
0823     *strength = (val >> pin_data->pin_conf.drive_shift) &
0824                     NS2_PIN_DRIVE_STRENGTH_MASK;
0825     *strength = (*strength + 1) * 2;
0826     spin_unlock_irqrestore(&pinctrl->lock, flags);
0827 
0828     dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n",
0829         pin, *strength);
0830     return 0;
0831 }
0832 
0833 static int ns2_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
0834                   unsigned long *config)
0835 {
0836     struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data;
0837     enum pin_config_param param = pinconf_to_config_param(*config);
0838     bool pull_up, pull_down;
0839     u16 arg = 0;
0840     int ret;
0841 
0842     if (pin_data->pin_conf.base == -1)
0843         return -ENOTSUPP;
0844 
0845     switch (param) {
0846     case PIN_CONFIG_BIAS_DISABLE:
0847         ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
0848         if (!pull_up && !pull_down)
0849             return 0;
0850         else
0851             return -EINVAL;
0852 
0853     case PIN_CONFIG_BIAS_PULL_UP:
0854         ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
0855         if (pull_up)
0856             return 0;
0857         else
0858             return -EINVAL;
0859 
0860     case PIN_CONFIG_BIAS_PULL_DOWN:
0861         ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
0862         if (pull_down)
0863             return 0;
0864         else
0865             return -EINVAL;
0866 
0867     case PIN_CONFIG_DRIVE_STRENGTH:
0868         ret = ns2_pin_get_strength(pctldev, pin, &arg);
0869         if (ret)
0870             return ret;
0871         *config = pinconf_to_config_packed(param, arg);
0872         return 0;
0873 
0874     case PIN_CONFIG_SLEW_RATE:
0875         ret = ns2_pin_get_slew(pctldev, pin, &arg);
0876         if (ret)
0877             return ret;
0878         *config = pinconf_to_config_packed(param, arg);
0879         return 0;
0880 
0881     case PIN_CONFIG_INPUT_ENABLE:
0882         ret = ns2_pin_get_enable(pctldev, pin);
0883         if (ret)
0884             return 0;
0885         else
0886             return -EINVAL;
0887 
0888     default:
0889         return -ENOTSUPP;
0890     }
0891 }
0892 
0893 static int ns2_pin_config_set(struct pinctrl_dev *pctrldev, unsigned int pin,
0894                   unsigned long *configs, unsigned int num_configs)
0895 {
0896     struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
0897     enum pin_config_param param;
0898     unsigned int i;
0899     u32 arg;
0900     int ret = -ENOTSUPP;
0901 
0902     if (pin_data->pin_conf.base == -1)
0903         return -ENOTSUPP;
0904 
0905     for (i = 0; i < num_configs; i++) {
0906         param = pinconf_to_config_param(configs[i]);
0907         arg = pinconf_to_config_argument(configs[i]);
0908 
0909         switch (param) {
0910         case PIN_CONFIG_BIAS_DISABLE:
0911             ret = ns2_pin_set_pull(pctrldev, pin, false, false);
0912             if (ret < 0)
0913                 goto out;
0914             break;
0915 
0916         case PIN_CONFIG_BIAS_PULL_UP:
0917             ret = ns2_pin_set_pull(pctrldev, pin, true, false);
0918             if (ret < 0)
0919                 goto out;
0920             break;
0921 
0922         case PIN_CONFIG_BIAS_PULL_DOWN:
0923             ret = ns2_pin_set_pull(pctrldev, pin, false, true);
0924             if (ret < 0)
0925                 goto out;
0926             break;
0927 
0928         case PIN_CONFIG_DRIVE_STRENGTH:
0929             ret = ns2_pin_set_strength(pctrldev, pin, arg);
0930             if (ret < 0)
0931                 goto out;
0932             break;
0933 
0934         case PIN_CONFIG_SLEW_RATE:
0935             ret = ns2_pin_set_slew(pctrldev, pin, arg);
0936             if (ret < 0)
0937                 goto out;
0938             break;
0939 
0940         case PIN_CONFIG_INPUT_ENABLE:
0941             ret = ns2_pin_set_enable(pctrldev, pin, arg);
0942             if (ret < 0)
0943                 goto out;
0944             break;
0945 
0946         default:
0947             dev_err(pctrldev->dev, "invalid configuration\n");
0948             return -ENOTSUPP;
0949         }
0950     }
0951 out:
0952     return ret;
0953 }
0954 static const struct pinmux_ops ns2_pinmux_ops = {
0955     .get_functions_count = ns2_get_functions_count,
0956     .get_function_name = ns2_get_function_name,
0957     .get_function_groups = ns2_get_function_groups,
0958     .set_mux = ns2_pinmux_enable,
0959 };
0960 
0961 static const struct pinconf_ops ns2_pinconf_ops = {
0962     .is_generic = true,
0963     .pin_config_get = ns2_pin_config_get,
0964     .pin_config_set = ns2_pin_config_set,
0965 };
0966 
0967 static struct pinctrl_desc ns2_pinctrl_desc = {
0968     .name = "ns2-pinmux",
0969     .pctlops = &ns2_pinctrl_ops,
0970     .pmxops = &ns2_pinmux_ops,
0971     .confops = &ns2_pinconf_ops,
0972 };
0973 
0974 static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
0975 {
0976     struct ns2_mux_log *log;
0977     unsigned int i;
0978 
0979     pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,
0980                     sizeof(struct ns2_mux_log),
0981                     GFP_KERNEL);
0982     if (!pinctrl->mux_log)
0983         return -ENOMEM;
0984 
0985     for (i = 0; i < NS2_NUM_IOMUX; i++)
0986         pinctrl->mux_log[i].is_configured = false;
0987     /* Group 0 uses bit 31 in the IOMUX_PAD_FUNCTION_0 register */
0988     log = &pinctrl->mux_log[0];
0989     log->mux.base = NS2_PIN_MUX_BASE0;
0990     log->mux.offset = 0;
0991     log->mux.shift = 31;
0992     log->mux.alt = 0;
0993 
0994     /*
0995      * Groups 1 through 14 use two bits each in the
0996      * IOMUX_PAD_FUNCTION_1 register starting with
0997      * bit position 30.
0998      */
0999     for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) {
1000         log = &pinctrl->mux_log[i];
1001         log->mux.base = NS2_PIN_MUX_BASE0;
1002         log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET;
1003         log->mux.shift = 32 - (i * 2);
1004         log->mux.alt = 0;
1005     }
1006 
1007     /*
1008      * Groups 15 through 18 use one bit each in the
1009      * AUX_SEL register.
1010      */
1011     for (i = 0; i < NS2_NUM_PWM_MUX; i++) {
1012         log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];
1013         log->mux.base = NS2_PIN_MUX_BASE1;
1014         log->mux.offset = 0;
1015         log->mux.shift = i;
1016         log->mux.alt =  0;
1017     }
1018     return 0;
1019 }
1020 
1021 static int ns2_pinmux_probe(struct platform_device *pdev)
1022 {
1023     struct ns2_pinctrl *pinctrl;
1024     struct resource *res;
1025     int i, ret;
1026     struct pinctrl_pin_desc *pins;
1027     unsigned int num_pins = ARRAY_SIZE(ns2_pins);
1028 
1029     pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1030     if (!pinctrl)
1031         return -ENOMEM;
1032 
1033     pinctrl->dev = &pdev->dev;
1034     platform_set_drvdata(pdev, pinctrl);
1035     spin_lock_init(&pinctrl->lock);
1036 
1037     pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
1038     if (IS_ERR(pinctrl->base0))
1039         return PTR_ERR(pinctrl->base0);
1040 
1041     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1042     if (!res)
1043         return -EINVAL;
1044     pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
1045                     resource_size(res));
1046     if (!pinctrl->base1) {
1047         dev_err(&pdev->dev, "unable to map I/O space\n");
1048         return -ENOMEM;
1049     }
1050 
1051     pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);
1052     if (IS_ERR(pinctrl->pinconf_base))
1053         return PTR_ERR(pinctrl->pinconf_base);
1054 
1055     ret = ns2_mux_log_init(pinctrl);
1056     if (ret) {
1057         dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
1058         return ret;
1059     }
1060 
1061     pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
1062     if (!pins)
1063         return -ENOMEM;
1064 
1065     for (i = 0; i < num_pins; i++) {
1066         pins[i].number = ns2_pins[i].pin;
1067         pins[i].name = ns2_pins[i].name;
1068         pins[i].drv_data = &ns2_pins[i];
1069     }
1070 
1071     pinctrl->groups = ns2_pin_groups;
1072     pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);
1073     pinctrl->functions = ns2_pin_functions;
1074     pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
1075     ns2_pinctrl_desc.pins = pins;
1076     ns2_pinctrl_desc.npins = num_pins;
1077 
1078     pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
1079             pinctrl);
1080     if (IS_ERR(pinctrl->pctl)) {
1081         dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");
1082         return PTR_ERR(pinctrl->pctl);
1083     }
1084 
1085     return 0;
1086 }
1087 
1088 static const struct of_device_id ns2_pinmux_of_match[] = {
1089     {.compatible = "brcm,ns2-pinmux"},
1090     { }
1091 };
1092 
1093 static struct platform_driver ns2_pinmux_driver = {
1094     .driver = {
1095         .name = "ns2-pinmux",
1096         .of_match_table = ns2_pinmux_of_match,
1097     },
1098     .probe = ns2_pinmux_probe,
1099 };
1100 
1101 static int __init ns2_pinmux_init(void)
1102 {
1103     return platform_driver_register(&ns2_pinmux_driver);
1104 }
1105 arch_initcall(ns2_pinmux_init);
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