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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014-2017 Broadcom
0004  */
0005 
0006 /*
0007  * This file contains the Broadcom Iproc GPIO driver that supports 3
0008  * GPIO controllers on Iproc including the ASIU GPIO controller, the
0009  * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
0010  * PINCONF such as bias pull up/down, and drive strength are also supported
0011  * in this driver.
0012  *
0013  * It provides the functionality where pins from the GPIO can be
0014  * individually muxed to GPIO function, if individual pad
0015  * configuration is supported, through the interaction with respective
0016  * SoCs IOMUX controller.
0017  */
0018 
0019 #include <linux/kernel.h>
0020 #include <linux/slab.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/io.h>
0023 #include <linux/gpio/driver.h>
0024 #include <linux/ioport.h>
0025 #include <linux/of_device.h>
0026 #include <linux/of_irq.h>
0027 #include <linux/pinctrl/pinctrl.h>
0028 #include <linux/pinctrl/pinconf.h>
0029 #include <linux/pinctrl/pinconf-generic.h>
0030 
0031 #include "../pinctrl-utils.h"
0032 
0033 #define IPROC_GPIO_DATA_IN_OFFSET   0x00
0034 #define IPROC_GPIO_DATA_OUT_OFFSET  0x04
0035 #define IPROC_GPIO_OUT_EN_OFFSET    0x08
0036 #define IPROC_GPIO_INT_TYPE_OFFSET  0x0c
0037 #define IPROC_GPIO_INT_DE_OFFSET    0x10
0038 #define IPROC_GPIO_INT_EDGE_OFFSET  0x14
0039 #define IPROC_GPIO_INT_MSK_OFFSET   0x18
0040 #define IPROC_GPIO_INT_STAT_OFFSET  0x1c
0041 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
0042 #define IPROC_GPIO_INT_CLR_OFFSET   0x24
0043 #define IPROC_GPIO_PAD_RES_OFFSET   0x34
0044 #define IPROC_GPIO_RES_EN_OFFSET    0x38
0045 
0046 /* drive strength control for ASIU GPIO */
0047 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
0048 
0049 /* pinconf for CCM GPIO */
0050 #define IPROC_GPIO_PULL_DN_OFFSET   0x10
0051 #define IPROC_GPIO_PULL_UP_OFFSET   0x14
0052 
0053 /* pinconf for CRMU(aon) GPIO and CCM GPIO*/
0054 #define IPROC_GPIO_DRV_CTRL_OFFSET  0x00
0055 
0056 #define GPIO_BANK_SIZE 0x200
0057 #define NGPIOS_PER_BANK 32
0058 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
0059 
0060 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
0061 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
0062 
0063 #define GPIO_DRV_STRENGTH_BIT_SHIFT  20
0064 #define GPIO_DRV_STRENGTH_BITS       3
0065 #define GPIO_DRV_STRENGTH_BIT_MASK   ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
0066 
0067 enum iproc_pinconf_param {
0068     IPROC_PINCONF_DRIVE_STRENGTH = 0,
0069     IPROC_PINCONF_BIAS_DISABLE,
0070     IPROC_PINCONF_BIAS_PULL_UP,
0071     IPROC_PINCONF_BIAS_PULL_DOWN,
0072     IPROC_PINCON_MAX,
0073 };
0074 
0075 enum iproc_pinconf_ctrl_type {
0076     IOCTRL_TYPE_AON = 1,
0077     IOCTRL_TYPE_CDRU,
0078     IOCTRL_TYPE_INVALID,
0079 };
0080 
0081 /*
0082  * Iproc GPIO core
0083  *
0084  * @dev: pointer to device
0085  * @base: I/O register base for Iproc GPIO controller
0086  * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
0087  * has the PINCONF support implemented outside of the GPIO block
0088  * @lock: lock to protect access to I/O registers
0089  * @gc: GPIO chip
0090  * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
0091  * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
0092  * that can be individually muxed to GPIO
0093  * @pinconf_disable: contains a list of PINCONF parameters that need to be
0094  * disabled
0095  * @nr_pinconf_disable: total number of PINCONF parameters that need to be
0096  * disabled
0097  * @pctl: pointer to pinctrl_dev
0098  * @pctldesc: pinctrl descriptor
0099  */
0100 struct iproc_gpio {
0101     struct device *dev;
0102 
0103     void __iomem *base;
0104     void __iomem *io_ctrl;
0105     enum iproc_pinconf_ctrl_type io_ctrl_type;
0106 
0107     raw_spinlock_t lock;
0108 
0109     struct irq_chip irqchip;
0110     struct gpio_chip gc;
0111     unsigned num_banks;
0112 
0113     bool pinmux_is_supported;
0114 
0115     enum pin_config_param *pinconf_disable;
0116     unsigned int nr_pinconf_disable;
0117 
0118     struct pinctrl_dev *pctl;
0119     struct pinctrl_desc pctldesc;
0120 };
0121 
0122 /*
0123  * Mapping from PINCONF pins to GPIO pins is 1-to-1
0124  */
0125 static inline unsigned iproc_pin_to_gpio(unsigned pin)
0126 {
0127     return pin;
0128 }
0129 
0130 /**
0131  *  iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
0132  *  Iproc GPIO register
0133  *
0134  *  @chip: Iproc GPIO device
0135  *  @reg: register offset
0136  *  @gpio: GPIO pin
0137  *  @set: set or clear
0138  */
0139 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
0140                   unsigned gpio, bool set)
0141 {
0142     unsigned int offset = IPROC_GPIO_REG(gpio, reg);
0143     unsigned int shift = IPROC_GPIO_SHIFT(gpio);
0144     u32 val;
0145 
0146     val = readl(chip->base + offset);
0147     if (set)
0148         val |= BIT(shift);
0149     else
0150         val &= ~BIT(shift);
0151     writel(val, chip->base + offset);
0152 }
0153 
0154 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
0155                   unsigned gpio)
0156 {
0157     unsigned int offset = IPROC_GPIO_REG(gpio, reg);
0158     unsigned int shift = IPROC_GPIO_SHIFT(gpio);
0159 
0160     return !!(readl(chip->base + offset) & BIT(shift));
0161 }
0162 
0163 static void iproc_gpio_irq_handler(struct irq_desc *desc)
0164 {
0165     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0166     struct iproc_gpio *chip = gpiochip_get_data(gc);
0167     struct irq_chip *irq_chip = irq_desc_get_chip(desc);
0168     int i, bit;
0169 
0170     chained_irq_enter(irq_chip, desc);
0171 
0172     /* go through the entire GPIO banks and handle all interrupts */
0173     for (i = 0; i < chip->num_banks; i++) {
0174         unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
0175                       IPROC_GPIO_INT_MSTAT_OFFSET);
0176 
0177         for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
0178             unsigned pin = NGPIOS_PER_BANK * i + bit;
0179 
0180             /*
0181              * Clear the interrupt before invoking the
0182              * handler, so we do not leave any window
0183              */
0184             writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
0185                    IPROC_GPIO_INT_CLR_OFFSET);
0186 
0187             generic_handle_domain_irq(gc->irq.domain, pin);
0188         }
0189     }
0190 
0191     chained_irq_exit(irq_chip, desc);
0192 }
0193 
0194 
0195 static void iproc_gpio_irq_ack(struct irq_data *d)
0196 {
0197     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0198     struct iproc_gpio *chip = gpiochip_get_data(gc);
0199     unsigned gpio = d->hwirq;
0200     unsigned int offset = IPROC_GPIO_REG(gpio,
0201             IPROC_GPIO_INT_CLR_OFFSET);
0202     unsigned int shift = IPROC_GPIO_SHIFT(gpio);
0203     u32 val = BIT(shift);
0204 
0205     writel(val, chip->base + offset);
0206 }
0207 
0208 /**
0209  *  iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
0210  *
0211  *  @d: IRQ chip data
0212  *  @unmask: mask/unmask GPIO interrupt
0213  */
0214 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
0215 {
0216     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0217     struct iproc_gpio *chip = gpiochip_get_data(gc);
0218     unsigned gpio = d->hwirq;
0219 
0220     iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
0221 }
0222 
0223 static void iproc_gpio_irq_mask(struct irq_data *d)
0224 {
0225     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0226     struct iproc_gpio *chip = gpiochip_get_data(gc);
0227     unsigned long flags;
0228 
0229     raw_spin_lock_irqsave(&chip->lock, flags);
0230     iproc_gpio_irq_set_mask(d, false);
0231     raw_spin_unlock_irqrestore(&chip->lock, flags);
0232 }
0233 
0234 static void iproc_gpio_irq_unmask(struct irq_data *d)
0235 {
0236     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0237     struct iproc_gpio *chip = gpiochip_get_data(gc);
0238     unsigned long flags;
0239 
0240     raw_spin_lock_irqsave(&chip->lock, flags);
0241     iproc_gpio_irq_set_mask(d, true);
0242     raw_spin_unlock_irqrestore(&chip->lock, flags);
0243 }
0244 
0245 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0246 {
0247     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0248     struct iproc_gpio *chip = gpiochip_get_data(gc);
0249     unsigned gpio = d->hwirq;
0250     bool level_triggered = false;
0251     bool dual_edge = false;
0252     bool rising_or_high = false;
0253     unsigned long flags;
0254 
0255     switch (type & IRQ_TYPE_SENSE_MASK) {
0256     case IRQ_TYPE_EDGE_RISING:
0257         rising_or_high = true;
0258         break;
0259 
0260     case IRQ_TYPE_EDGE_FALLING:
0261         break;
0262 
0263     case IRQ_TYPE_EDGE_BOTH:
0264         dual_edge = true;
0265         break;
0266 
0267     case IRQ_TYPE_LEVEL_HIGH:
0268         level_triggered = true;
0269         rising_or_high = true;
0270         break;
0271 
0272     case IRQ_TYPE_LEVEL_LOW:
0273         level_triggered = true;
0274         break;
0275 
0276     default:
0277         dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
0278             type);
0279         return -EINVAL;
0280     }
0281 
0282     raw_spin_lock_irqsave(&chip->lock, flags);
0283     iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
0284                level_triggered);
0285     iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
0286     iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
0287                rising_or_high);
0288 
0289     if (type & IRQ_TYPE_EDGE_BOTH)
0290         irq_set_handler_locked(d, handle_edge_irq);
0291     else
0292         irq_set_handler_locked(d, handle_level_irq);
0293 
0294     raw_spin_unlock_irqrestore(&chip->lock, flags);
0295 
0296     dev_dbg(chip->dev,
0297         "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
0298         gpio, level_triggered, dual_edge, rising_or_high);
0299 
0300     return 0;
0301 }
0302 
0303 /*
0304  * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
0305  */
0306 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
0307 {
0308     struct iproc_gpio *chip = gpiochip_get_data(gc);
0309     unsigned gpio = gc->base + offset;
0310 
0311     /* not all Iproc GPIO pins can be muxed individually */
0312     if (!chip->pinmux_is_supported)
0313         return 0;
0314 
0315     return pinctrl_gpio_request(gpio);
0316 }
0317 
0318 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
0319 {
0320     struct iproc_gpio *chip = gpiochip_get_data(gc);
0321     unsigned gpio = gc->base + offset;
0322 
0323     if (!chip->pinmux_is_supported)
0324         return;
0325 
0326     pinctrl_gpio_free(gpio);
0327 }
0328 
0329 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
0330 {
0331     struct iproc_gpio *chip = gpiochip_get_data(gc);
0332     unsigned long flags;
0333 
0334     raw_spin_lock_irqsave(&chip->lock, flags);
0335     iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
0336     raw_spin_unlock_irqrestore(&chip->lock, flags);
0337 
0338     dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
0339 
0340     return 0;
0341 }
0342 
0343 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
0344                     int val)
0345 {
0346     struct iproc_gpio *chip = gpiochip_get_data(gc);
0347     unsigned long flags;
0348 
0349     raw_spin_lock_irqsave(&chip->lock, flags);
0350     iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
0351     iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
0352     raw_spin_unlock_irqrestore(&chip->lock, flags);
0353 
0354     dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
0355 
0356     return 0;
0357 }
0358 
0359 static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
0360 {
0361     struct iproc_gpio *chip = gpiochip_get_data(gc);
0362     unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
0363     unsigned int shift = IPROC_GPIO_SHIFT(gpio);
0364 
0365     if (readl(chip->base + offset) & BIT(shift))
0366         return GPIO_LINE_DIRECTION_OUT;
0367 
0368     return GPIO_LINE_DIRECTION_IN;
0369 }
0370 
0371 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
0372 {
0373     struct iproc_gpio *chip = gpiochip_get_data(gc);
0374     unsigned long flags;
0375 
0376     raw_spin_lock_irqsave(&chip->lock, flags);
0377     iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
0378     raw_spin_unlock_irqrestore(&chip->lock, flags);
0379 
0380     dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
0381 }
0382 
0383 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
0384 {
0385     struct iproc_gpio *chip = gpiochip_get_data(gc);
0386     unsigned int offset = IPROC_GPIO_REG(gpio,
0387                           IPROC_GPIO_DATA_IN_OFFSET);
0388     unsigned int shift = IPROC_GPIO_SHIFT(gpio);
0389 
0390     return !!(readl(chip->base + offset) & BIT(shift));
0391 }
0392 
0393 /*
0394  * Mapping of the iProc PINCONF parameters to the generic pin configuration
0395  * parameters
0396  */
0397 static const enum pin_config_param iproc_pinconf_disable_map[] = {
0398     [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
0399     [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
0400     [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
0401     [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
0402 };
0403 
0404 static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
0405                         enum pin_config_param param)
0406 {
0407     unsigned int i;
0408 
0409     if (!chip->nr_pinconf_disable)
0410         return false;
0411 
0412     for (i = 0; i < chip->nr_pinconf_disable; i++)
0413         if (chip->pinconf_disable[i] == param)
0414             return true;
0415 
0416     return false;
0417 }
0418 
0419 static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
0420                         unsigned long disable_mask)
0421 {
0422     unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
0423     unsigned int bit, nbits = 0;
0424 
0425     /* figure out total number of PINCONF parameters to disable */
0426     for_each_set_bit(bit, &disable_mask, map_size)
0427         nbits++;
0428 
0429     if (!nbits)
0430         return 0;
0431 
0432     /*
0433      * Allocate an array to store PINCONF parameters that need to be
0434      * disabled
0435      */
0436     chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
0437                          sizeof(*chip->pinconf_disable),
0438                          GFP_KERNEL);
0439     if (!chip->pinconf_disable)
0440         return -ENOMEM;
0441 
0442     chip->nr_pinconf_disable = nbits;
0443 
0444     /* now store these parameters */
0445     nbits = 0;
0446     for_each_set_bit(bit, &disable_mask, map_size)
0447         chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
0448 
0449     return 0;
0450 }
0451 
0452 static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
0453 {
0454     return 1;
0455 }
0456 
0457 /*
0458  * Only one group: "gpio_grp", since this local pinctrl device only performs
0459  * GPIO specific PINCONF configurations
0460  */
0461 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
0462                      unsigned selector)
0463 {
0464     return "gpio_grp";
0465 }
0466 
0467 static const struct pinctrl_ops iproc_pctrl_ops = {
0468     .get_groups_count = iproc_get_groups_count,
0469     .get_group_name = iproc_get_group_name,
0470     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0471     .dt_free_map = pinctrl_utils_free_map,
0472 };
0473 
0474 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
0475                 bool disable, bool pull_up)
0476 {
0477     void __iomem *base;
0478     unsigned long flags;
0479     unsigned int shift;
0480     u32 val_1, val_2;
0481 
0482     raw_spin_lock_irqsave(&chip->lock, flags);
0483     if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
0484         base = chip->io_ctrl;
0485         shift = IPROC_GPIO_SHIFT(gpio);
0486 
0487         val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
0488         val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
0489         if (disable) {
0490             /* no pull-up or pull-down */
0491             val_1 &= ~BIT(shift);
0492             val_2 &= ~BIT(shift);
0493         } else if (pull_up) {
0494             val_1 |= BIT(shift);
0495             val_2 &= ~BIT(shift);
0496         } else {
0497             val_1 &= ~BIT(shift);
0498             val_2 |= BIT(shift);
0499         }
0500         writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
0501         writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
0502     } else {
0503         if (disable) {
0504             iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
0505                       false);
0506         } else {
0507             iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
0508                       pull_up);
0509             iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
0510                       true);
0511         }
0512     }
0513 
0514     raw_spin_unlock_irqrestore(&chip->lock, flags);
0515     dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
0516 
0517     return 0;
0518 }
0519 
0520 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
0521                  bool *disable, bool *pull_up)
0522 {
0523     void __iomem *base;
0524     unsigned long flags;
0525     unsigned int shift;
0526     u32 val_1, val_2;
0527 
0528     raw_spin_lock_irqsave(&chip->lock, flags);
0529     if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
0530         base = chip->io_ctrl;
0531         shift = IPROC_GPIO_SHIFT(gpio);
0532 
0533         val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
0534         val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
0535 
0536         *pull_up = val_1 ? true : false;
0537         *disable = (val_1 | val_2) ? false : true;
0538 
0539     } else {
0540         *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
0541         *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
0542     }
0543     raw_spin_unlock_irqrestore(&chip->lock, flags);
0544 }
0545 
0546 #define DRV_STRENGTH_OFFSET(gpio, bit, type)  ((type) == IOCTRL_TYPE_AON ? \
0547     ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
0548     ((type) == IOCTRL_TYPE_CDRU) ? \
0549     ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
0550     ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
0551 
0552 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
0553                     unsigned strength)
0554 {
0555     void __iomem *base;
0556     unsigned int i, offset, shift;
0557     u32 val;
0558     unsigned long flags;
0559 
0560     /* make sure drive strength is supported */
0561     if (strength < 2 ||  strength > 16 || (strength % 2))
0562         return -ENOTSUPP;
0563 
0564     if (chip->io_ctrl) {
0565         base = chip->io_ctrl;
0566     } else {
0567         base = chip->base;
0568     }
0569 
0570     shift = IPROC_GPIO_SHIFT(gpio);
0571 
0572     dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
0573         strength);
0574 
0575     raw_spin_lock_irqsave(&chip->lock, flags);
0576     strength = (strength / 2) - 1;
0577     for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
0578         offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
0579         val = readl(base + offset);
0580         val &= ~BIT(shift);
0581         val |= ((strength >> i) & 0x1) << shift;
0582         writel(val, base + offset);
0583     }
0584     raw_spin_unlock_irqrestore(&chip->lock, flags);
0585 
0586     return 0;
0587 }
0588 
0589 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
0590                     u16 *strength)
0591 {
0592     void __iomem *base;
0593     unsigned int i, offset, shift;
0594     u32 val;
0595     unsigned long flags;
0596 
0597     if (chip->io_ctrl) {
0598         base = chip->io_ctrl;
0599     } else {
0600         base = chip->base;
0601     }
0602 
0603     shift = IPROC_GPIO_SHIFT(gpio);
0604 
0605     raw_spin_lock_irqsave(&chip->lock, flags);
0606     *strength = 0;
0607     for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
0608         offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
0609         val = readl(base + offset) & BIT(shift);
0610         val >>= shift;
0611         *strength += (val << i);
0612     }
0613 
0614     /* convert to mA */
0615     *strength = (*strength + 1) * 2;
0616     raw_spin_unlock_irqrestore(&chip->lock, flags);
0617 
0618     return 0;
0619 }
0620 
0621 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
0622                  unsigned long *config)
0623 {
0624     struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
0625     enum pin_config_param param = pinconf_to_config_param(*config);
0626     unsigned gpio = iproc_pin_to_gpio(pin);
0627     u16 arg;
0628     bool disable, pull_up;
0629     int ret;
0630 
0631     if (iproc_pinconf_param_is_disabled(chip, param))
0632         return -ENOTSUPP;
0633 
0634     switch (param) {
0635     case PIN_CONFIG_BIAS_DISABLE:
0636         iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
0637         if (disable)
0638             return 0;
0639         else
0640             return -EINVAL;
0641 
0642     case PIN_CONFIG_BIAS_PULL_UP:
0643         iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
0644         if (!disable && pull_up)
0645             return 0;
0646         else
0647             return -EINVAL;
0648 
0649     case PIN_CONFIG_BIAS_PULL_DOWN:
0650         iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
0651         if (!disable && !pull_up)
0652             return 0;
0653         else
0654             return -EINVAL;
0655 
0656     case PIN_CONFIG_DRIVE_STRENGTH:
0657         ret = iproc_gpio_get_strength(chip, gpio, &arg);
0658         if (ret)
0659             return ret;
0660         *config = pinconf_to_config_packed(param, arg);
0661 
0662         return 0;
0663 
0664     default:
0665         return -ENOTSUPP;
0666     }
0667 
0668     return -ENOTSUPP;
0669 }
0670 
0671 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
0672                  unsigned long *configs, unsigned num_configs)
0673 {
0674     struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
0675     enum pin_config_param param;
0676     u32 arg;
0677     unsigned i, gpio = iproc_pin_to_gpio(pin);
0678     int ret = -ENOTSUPP;
0679 
0680     for (i = 0; i < num_configs; i++) {
0681         param = pinconf_to_config_param(configs[i]);
0682 
0683         if (iproc_pinconf_param_is_disabled(chip, param))
0684             return -ENOTSUPP;
0685 
0686         arg = pinconf_to_config_argument(configs[i]);
0687 
0688         switch (param) {
0689         case PIN_CONFIG_BIAS_DISABLE:
0690             ret = iproc_gpio_set_pull(chip, gpio, true, false);
0691             if (ret < 0)
0692                 goto out;
0693             break;
0694 
0695         case PIN_CONFIG_BIAS_PULL_UP:
0696             ret = iproc_gpio_set_pull(chip, gpio, false, true);
0697             if (ret < 0)
0698                 goto out;
0699             break;
0700 
0701         case PIN_CONFIG_BIAS_PULL_DOWN:
0702             ret = iproc_gpio_set_pull(chip, gpio, false, false);
0703             if (ret < 0)
0704                 goto out;
0705             break;
0706 
0707         case PIN_CONFIG_DRIVE_STRENGTH:
0708             ret = iproc_gpio_set_strength(chip, gpio, arg);
0709             if (ret < 0)
0710                 goto out;
0711             break;
0712 
0713         default:
0714             dev_err(chip->dev, "invalid configuration\n");
0715             return -ENOTSUPP;
0716         }
0717     } /* for each config */
0718 
0719 out:
0720     return ret;
0721 }
0722 
0723 static const struct pinconf_ops iproc_pconf_ops = {
0724     .is_generic = true,
0725     .pin_config_get = iproc_pin_config_get,
0726     .pin_config_set = iproc_pin_config_set,
0727 };
0728 
0729 /*
0730  * Iproc GPIO controller supports some PINCONF related configurations such as
0731  * pull up, pull down, and drive strength, when the pin is configured to GPIO
0732  *
0733  * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
0734  * local GPIO pins
0735  */
0736 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
0737 {
0738     struct pinctrl_desc *pctldesc = &chip->pctldesc;
0739     struct pinctrl_pin_desc *pins;
0740     struct gpio_chip *gc = &chip->gc;
0741     int i;
0742 
0743     pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
0744     if (!pins)
0745         return -ENOMEM;
0746 
0747     for (i = 0; i < gc->ngpio; i++) {
0748         pins[i].number = i;
0749         pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
0750                           "gpio-%d", i);
0751         if (!pins[i].name)
0752             return -ENOMEM;
0753     }
0754 
0755     pctldesc->name = dev_name(chip->dev);
0756     pctldesc->pctlops = &iproc_pctrl_ops;
0757     pctldesc->pins = pins;
0758     pctldesc->npins = gc->ngpio;
0759     pctldesc->confops = &iproc_pconf_ops;
0760 
0761     chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
0762     if (IS_ERR(chip->pctl)) {
0763         dev_err(chip->dev, "unable to register pinctrl device\n");
0764         return PTR_ERR(chip->pctl);
0765     }
0766 
0767     return 0;
0768 }
0769 
0770 static const struct of_device_id iproc_gpio_of_match[] = {
0771     { .compatible = "brcm,iproc-gpio" },
0772     { .compatible = "brcm,cygnus-ccm-gpio" },
0773     { .compatible = "brcm,cygnus-asiu-gpio" },
0774     { .compatible = "brcm,cygnus-crmu-gpio" },
0775     { .compatible = "brcm,iproc-nsp-gpio" },
0776     { .compatible = "brcm,iproc-stingray-gpio" },
0777     { /* sentinel */ }
0778 };
0779 
0780 static int iproc_gpio_probe(struct platform_device *pdev)
0781 {
0782     struct device *dev = &pdev->dev;
0783     struct resource *res;
0784     struct iproc_gpio *chip;
0785     struct gpio_chip *gc;
0786     u32 ngpios, pinconf_disable_mask = 0;
0787     int irq, ret;
0788     bool no_pinconf = false;
0789     enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
0790 
0791     /* NSP does not support drive strength config */
0792     if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
0793         pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
0794     /* Stingray does not support pinconf in this controller */
0795     else if (of_device_is_compatible(dev->of_node,
0796                      "brcm,iproc-stingray-gpio"))
0797         no_pinconf = true;
0798 
0799     chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
0800     if (!chip)
0801         return -ENOMEM;
0802 
0803     chip->dev = dev;
0804     platform_set_drvdata(pdev, chip);
0805 
0806     chip->base = devm_platform_ioremap_resource(pdev, 0);
0807     if (IS_ERR(chip->base)) {
0808         dev_err(dev, "unable to map I/O memory\n");
0809         return PTR_ERR(chip->base);
0810     }
0811 
0812     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0813     if (res) {
0814         chip->io_ctrl = devm_ioremap_resource(dev, res);
0815         if (IS_ERR(chip->io_ctrl))
0816             return PTR_ERR(chip->io_ctrl);
0817         if (of_device_is_compatible(dev->of_node,
0818                         "brcm,cygnus-ccm-gpio"))
0819             io_ctrl_type = IOCTRL_TYPE_CDRU;
0820         else
0821             io_ctrl_type = IOCTRL_TYPE_AON;
0822     }
0823 
0824     chip->io_ctrl_type = io_ctrl_type;
0825 
0826     if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
0827         dev_err(&pdev->dev, "missing ngpios DT property\n");
0828         return -ENODEV;
0829     }
0830 
0831     raw_spin_lock_init(&chip->lock);
0832 
0833     gc = &chip->gc;
0834     gc->base = -1;
0835     gc->ngpio = ngpios;
0836     chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
0837     gc->label = dev_name(dev);
0838     gc->parent = dev;
0839     gc->request = iproc_gpio_request;
0840     gc->free = iproc_gpio_free;
0841     gc->direction_input = iproc_gpio_direction_input;
0842     gc->direction_output = iproc_gpio_direction_output;
0843     gc->get_direction = iproc_gpio_get_direction;
0844     gc->set = iproc_gpio_set;
0845     gc->get = iproc_gpio_get;
0846 
0847     chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
0848                             "gpio-ranges");
0849 
0850     /* optional GPIO interrupt support */
0851     irq = platform_get_irq_optional(pdev, 0);
0852     if (irq > 0) {
0853         struct irq_chip *irqc;
0854         struct gpio_irq_chip *girq;
0855 
0856         irqc = &chip->irqchip;
0857         irqc->name = dev_name(dev);
0858         irqc->irq_ack = iproc_gpio_irq_ack;
0859         irqc->irq_mask = iproc_gpio_irq_mask;
0860         irqc->irq_unmask = iproc_gpio_irq_unmask;
0861         irqc->irq_set_type = iproc_gpio_irq_set_type;
0862         irqc->irq_enable = iproc_gpio_irq_unmask;
0863         irqc->irq_disable = iproc_gpio_irq_mask;
0864 
0865         girq = &gc->irq;
0866         girq->chip = irqc;
0867         girq->parent_handler = iproc_gpio_irq_handler;
0868         girq->num_parents = 1;
0869         girq->parents = devm_kcalloc(dev, 1,
0870                          sizeof(*girq->parents),
0871                          GFP_KERNEL);
0872         if (!girq->parents)
0873             return -ENOMEM;
0874         girq->parents[0] = irq;
0875         girq->default_type = IRQ_TYPE_NONE;
0876         girq->handler = handle_bad_irq;
0877     }
0878 
0879     ret = gpiochip_add_data(gc, chip);
0880     if (ret < 0) {
0881         dev_err(dev, "unable to add GPIO chip\n");
0882         return ret;
0883     }
0884 
0885     if (!no_pinconf) {
0886         ret = iproc_gpio_register_pinconf(chip);
0887         if (ret) {
0888             dev_err(dev, "unable to register pinconf\n");
0889             goto err_rm_gpiochip;
0890         }
0891 
0892         if (pinconf_disable_mask) {
0893             ret = iproc_pinconf_disable_map_create(chip,
0894                              pinconf_disable_mask);
0895             if (ret) {
0896                 dev_err(dev,
0897                     "unable to create pinconf disable map\n");
0898                 goto err_rm_gpiochip;
0899             }
0900         }
0901     }
0902 
0903     return 0;
0904 
0905 err_rm_gpiochip:
0906     gpiochip_remove(gc);
0907 
0908     return ret;
0909 }
0910 
0911 static struct platform_driver iproc_gpio_driver = {
0912     .driver = {
0913         .name = "iproc-gpio",
0914         .of_match_table = iproc_gpio_of_match,
0915     },
0916     .probe = iproc_gpio_probe,
0917 };
0918 
0919 static int __init iproc_gpio_init(void)
0920 {
0921     return platform_driver_register(&iproc_gpio_driver);
0922 }
0923 arch_initcall_sync(iproc_gpio_init);
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