pinctrl/bcm/pinctrl-bcm63268.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Driver for BCM63268 GPIO unit (pinctrl + GPIO)
0004  *
0005  * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
0006  * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
0007  */
0008
0009 #include <linux/bits.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/kernel.h>
0012 #include <linux/of.h>
0013 #include <linux/pinctrl/pinmux.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/regmap.h>
0016
0017 #include "../pinctrl-utils.h"
0018
0019 #include "pinctrl-bcm63xx.h"
0020
0021 #define BCM63268_NUM_GPIOS      52
0022 #define BCM63268_NUM_LEDS       24
0023
0024 #define BCM63268_LED_REG        0x10
0025 #define BCM63268_MODE_REG       0x18
0026 #define BCM63268_CTRL_REG       0x1c
0027 #define BCM63268_BASEMODE_REG       0x38
0028 #define  BCM63268_BASEMODE_NAND     BIT(2) /* GPIOs 2-7, 24-31 */
0029 #define  BCM63268_BASEMODE_GPIO35   BIT(4) /* GPIO 35 */
0030 #define  BCM63268_BASEMODE_DECTPD   BIT(5) /* GPIOs 8/9 */
0031 #define  BCM63268_BASEMODE_VDSL_PHY_0   BIT(6) /* GPIOs 10/11 */
0032 #define  BCM63268_BASEMODE_VDSL_PHY_1   BIT(7) /* GPIOs 12/13 */
0033 #define  BCM63268_BASEMODE_VDSL_PHY_2   BIT(8) /* GPIOs 24/25 */
0034 #define  BCM63268_BASEMODE_VDSL_PHY_3   BIT(9) /* GPIOs 26/27 */
0035
0036 enum bcm63268_pinctrl_reg {
0037     BCM63268_LEDCTRL,
0038     BCM63268_MODE,
0039     BCM63268_CTRL,
0040     BCM63268_BASEMODE,
0041 };
0042
0043 struct bcm63268_pingroup {
0044     const char *name;
0045     const unsigned * const pins;
0046     const unsigned num_pins;
0047 };
0048
0049 struct bcm63268_function {
0050     const char *name;
0051     const char * const *groups;
0052     const unsigned num_groups;
0053
0054     enum bcm63268_pinctrl_reg reg;
0055     uint32_t mask;
0056 };
0057
0058 #define BCM63268_PIN(a, b, basemode)            \
0059     {                       \
0060         .number = a,                \
0061         .name = b,              \
0062         .drv_data = (void *)(basemode)      \
0063     }
0064
0065 static const struct pinctrl_pin_desc bcm63268_pins[] = {
0066     PINCTRL_PIN(0, "gpio0"),
0067     PINCTRL_PIN(1, "gpio1"),
0068     BCM63268_PIN(2, "gpio2", BCM63268_BASEMODE_NAND),
0069     BCM63268_PIN(3, "gpio3", BCM63268_BASEMODE_NAND),
0070     BCM63268_PIN(4, "gpio4", BCM63268_BASEMODE_NAND),
0071     BCM63268_PIN(5, "gpio5", BCM63268_BASEMODE_NAND),
0072     BCM63268_PIN(6, "gpio6", BCM63268_BASEMODE_NAND),
0073     BCM63268_PIN(7, "gpio7", BCM63268_BASEMODE_NAND),
0074     BCM63268_PIN(8, "gpio8", BCM63268_BASEMODE_DECTPD),
0075     BCM63268_PIN(9, "gpio9", BCM63268_BASEMODE_DECTPD),
0076     BCM63268_PIN(10, "gpio10", BCM63268_BASEMODE_VDSL_PHY_0),
0077     BCM63268_PIN(11, "gpio11", BCM63268_BASEMODE_VDSL_PHY_0),
0078     BCM63268_PIN(12, "gpio12", BCM63268_BASEMODE_VDSL_PHY_1),
0079     BCM63268_PIN(13, "gpio13", BCM63268_BASEMODE_VDSL_PHY_1),
0080     PINCTRL_PIN(14, "gpio14"),
0081     PINCTRL_PIN(15, "gpio15"),
0082     PINCTRL_PIN(16, "gpio16"),
0083     PINCTRL_PIN(17, "gpio17"),
0084     PINCTRL_PIN(18, "gpio18"),
0085     PINCTRL_PIN(19, "gpio19"),
0086     PINCTRL_PIN(20, "gpio20"),
0087     PINCTRL_PIN(21, "gpio21"),
0088     PINCTRL_PIN(22, "gpio22"),
0089     PINCTRL_PIN(23, "gpio23"),
0090     BCM63268_PIN(24, "gpio24",
0091              BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
0092     BCM63268_PIN(25, "gpio25",
0093              BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
0094     BCM63268_PIN(26, "gpio26",
0095              BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
0096     BCM63268_PIN(27, "gpio27",
0097              BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
0098     BCM63268_PIN(28, "gpio28", BCM63268_BASEMODE_NAND),
0099     BCM63268_PIN(29, "gpio29", BCM63268_BASEMODE_NAND),
0100     BCM63268_PIN(30, "gpio30", BCM63268_BASEMODE_NAND),
0101     BCM63268_PIN(31, "gpio31", BCM63268_BASEMODE_NAND),
0102     PINCTRL_PIN(32, "gpio32"),
0103     PINCTRL_PIN(33, "gpio33"),
0104     PINCTRL_PIN(34, "gpio34"),
0105     PINCTRL_PIN(35, "gpio35"),
0106     PINCTRL_PIN(36, "gpio36"),
0107     PINCTRL_PIN(37, "gpio37"),
0108     PINCTRL_PIN(38, "gpio38"),
0109     PINCTRL_PIN(39, "gpio39"),
0110     PINCTRL_PIN(40, "gpio40"),
0111     PINCTRL_PIN(41, "gpio41"),
0112     PINCTRL_PIN(42, "gpio42"),
0113     PINCTRL_PIN(43, "gpio43"),
0114     PINCTRL_PIN(44, "gpio44"),
0115     PINCTRL_PIN(45, "gpio45"),
0116     PINCTRL_PIN(46, "gpio46"),
0117     PINCTRL_PIN(47, "gpio47"),
0118     PINCTRL_PIN(48, "gpio48"),
0119     PINCTRL_PIN(49, "gpio49"),
0120     PINCTRL_PIN(50, "gpio50"),
0121     PINCTRL_PIN(51, "gpio51"),
0122 };
0123
0124 static unsigned gpio0_pins[] = { 0 };
0125 static unsigned gpio1_pins[] = { 1 };
0126 static unsigned gpio2_pins[] = { 2 };
0127 static unsigned gpio3_pins[] = { 3 };
0128 static unsigned gpio4_pins[] = { 4 };
0129 static unsigned gpio5_pins[] = { 5 };
0130 static unsigned gpio6_pins[] = { 6 };
0131 static unsigned gpio7_pins[] = { 7 };
0132 static unsigned gpio8_pins[] = { 8 };
0133 static unsigned gpio9_pins[] = { 9 };
0134 static unsigned gpio10_pins[] = { 10 };
0135 static unsigned gpio11_pins[] = { 11 };
0136 static unsigned gpio12_pins[] = { 12 };
0137 static unsigned gpio13_pins[] = { 13 };
0138 static unsigned gpio14_pins[] = { 14 };
0139 static unsigned gpio15_pins[] = { 15 };
0140 static unsigned gpio16_pins[] = { 16 };
0141 static unsigned gpio17_pins[] = { 17 };
0142 static unsigned gpio18_pins[] = { 18 };
0143 static unsigned gpio19_pins[] = { 19 };
0144 static unsigned gpio20_pins[] = { 20 };
0145 static unsigned gpio21_pins[] = { 21 };
0146 static unsigned gpio22_pins[] = { 22 };
0147 static unsigned gpio23_pins[] = { 23 };
0148 static unsigned gpio24_pins[] = { 24 };
0149 static unsigned gpio25_pins[] = { 25 };
0150 static unsigned gpio26_pins[] = { 26 };
0151 static unsigned gpio27_pins[] = { 27 };
0152 static unsigned gpio28_pins[] = { 28 };
0153 static unsigned gpio29_pins[] = { 29 };
0154 static unsigned gpio30_pins[] = { 30 };
0155 static unsigned gpio31_pins[] = { 31 };
0156 static unsigned gpio32_pins[] = { 32 };
0157 static unsigned gpio33_pins[] = { 33 };
0158 static unsigned gpio34_pins[] = { 34 };
0159 static unsigned gpio35_pins[] = { 35 };
0160 static unsigned gpio36_pins[] = { 36 };
0161 static unsigned gpio37_pins[] = { 37 };
0162 static unsigned gpio38_pins[] = { 38 };
0163 static unsigned gpio39_pins[] = { 39 };
0164 static unsigned gpio40_pins[] = { 40 };
0165 static unsigned gpio41_pins[] = { 41 };
0166 static unsigned gpio42_pins[] = { 42 };
0167 static unsigned gpio43_pins[] = { 43 };
0168 static unsigned gpio44_pins[] = { 44 };
0169 static unsigned gpio45_pins[] = { 45 };
0170 static unsigned gpio46_pins[] = { 46 };
0171 static unsigned gpio47_pins[] = { 47 };
0172 static unsigned gpio48_pins[] = { 48 };
0173 static unsigned gpio49_pins[] = { 49 };
0174 static unsigned gpio50_pins[] = { 50 };
0175 static unsigned gpio51_pins[] = { 51 };
0176
0177 static unsigned nand_grp_pins[] = {
0178     2, 3, 4, 5, 6, 7, 24,
0179     25, 26, 27, 28, 29, 30, 31,
0180 };
0181
0182 static unsigned dectpd_grp_pins[] = { 8, 9 };
0183 static unsigned vdsl_phy0_grp_pins[] = { 10, 11 };
0184 static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };
0185 static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };
0186 static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };
0187
0188 #define BCM63268_GROUP(n)                   \
0189     {                           \
0190         .name = #n,                 \
0191         .pins = n##_pins,               \
0192         .num_pins = ARRAY_SIZE(n##_pins),       \
0193     }
0194
0195 static struct bcm63268_pingroup bcm63268_groups[] = {
0196     BCM63268_GROUP(gpio0),
0197     BCM63268_GROUP(gpio1),
0198     BCM63268_GROUP(gpio2),
0199     BCM63268_GROUP(gpio3),
0200     BCM63268_GROUP(gpio4),
0201     BCM63268_GROUP(gpio5),
0202     BCM63268_GROUP(gpio6),
0203     BCM63268_GROUP(gpio7),
0204     BCM63268_GROUP(gpio8),
0205     BCM63268_GROUP(gpio9),
0206     BCM63268_GROUP(gpio10),
0207     BCM63268_GROUP(gpio11),
0208     BCM63268_GROUP(gpio12),
0209     BCM63268_GROUP(gpio13),
0210     BCM63268_GROUP(gpio14),
0211     BCM63268_GROUP(gpio15),
0212     BCM63268_GROUP(gpio16),
0213     BCM63268_GROUP(gpio17),
0214     BCM63268_GROUP(gpio18),
0215     BCM63268_GROUP(gpio19),
0216     BCM63268_GROUP(gpio20),
0217     BCM63268_GROUP(gpio21),
0218     BCM63268_GROUP(gpio22),
0219     BCM63268_GROUP(gpio23),
0220     BCM63268_GROUP(gpio24),
0221     BCM63268_GROUP(gpio25),
0222     BCM63268_GROUP(gpio26),
0223     BCM63268_GROUP(gpio27),
0224     BCM63268_GROUP(gpio28),
0225     BCM63268_GROUP(gpio29),
0226     BCM63268_GROUP(gpio30),
0227     BCM63268_GROUP(gpio31),
0228     BCM63268_GROUP(gpio32),
0229     BCM63268_GROUP(gpio33),
0230     BCM63268_GROUP(gpio34),
0231     BCM63268_GROUP(gpio35),
0232     BCM63268_GROUP(gpio36),
0233     BCM63268_GROUP(gpio37),
0234     BCM63268_GROUP(gpio38),
0235     BCM63268_GROUP(gpio39),
0236     BCM63268_GROUP(gpio40),
0237     BCM63268_GROUP(gpio41),
0238     BCM63268_GROUP(gpio42),
0239     BCM63268_GROUP(gpio43),
0240     BCM63268_GROUP(gpio44),
0241     BCM63268_GROUP(gpio45),
0242     BCM63268_GROUP(gpio46),
0243     BCM63268_GROUP(gpio47),
0244     BCM63268_GROUP(gpio48),
0245     BCM63268_GROUP(gpio49),
0246     BCM63268_GROUP(gpio50),
0247     BCM63268_GROUP(gpio51),
0248
0249     /* multi pin groups */
0250     BCM63268_GROUP(nand_grp),
0251     BCM63268_GROUP(dectpd_grp),
0252     BCM63268_GROUP(vdsl_phy0_grp),
0253     BCM63268_GROUP(vdsl_phy1_grp),
0254     BCM63268_GROUP(vdsl_phy2_grp),
0255     BCM63268_GROUP(vdsl_phy3_grp),
0256 };
0257
0258 static const char * const led_groups[] = {
0259     "gpio0",
0260     "gpio1",
0261     "gpio2",
0262     "gpio3",
0263     "gpio4",
0264     "gpio5",
0265     "gpio6",
0266     "gpio7",
0267     "gpio8",
0268     "gpio9",
0269     "gpio10",
0270     "gpio11",
0271     "gpio12",
0272     "gpio13",
0273     "gpio14",
0274     "gpio15",
0275     "gpio16",
0276     "gpio17",
0277     "gpio18",
0278     "gpio19",
0279     "gpio20",
0280     "gpio21",
0281     "gpio22",
0282     "gpio23",
0283 };
0284
0285 static const char * const serial_led_clk_groups[] = {
0286     "gpio0",
0287 };
0288
0289 static const char * const serial_led_data_groups[] = {
0290     "gpio1",
0291 };
0292
0293 static const char * const hsspi_cs4_groups[] = {
0294     "gpio16",
0295 };
0296
0297 static const char * const hsspi_cs5_groups[] = {
0298     "gpio17",
0299 };
0300
0301 static const char * const hsspi_cs6_groups[] = {
0302     "gpio8",
0303 };
0304
0305 static const char * const hsspi_cs7_groups[] = {
0306     "gpio9",
0307 };
0308
0309 static const char * const uart1_scts_groups[] = {
0310     "gpio10",
0311     "gpio24",
0312 };
0313
0314 static const char * const uart1_srts_groups[] = {
0315     "gpio11",
0316     "gpio25",
0317 };
0318
0319 static const char * const uart1_sdin_groups[] = {
0320     "gpio12",
0321     "gpio26",
0322 };
0323
0324 static const char * const uart1_sdout_groups[] = {
0325     "gpio13",
0326     "gpio27",
0327 };
0328
0329 static const char * const ntr_pulse_in_groups[] = {
0330     "gpio14",
0331     "gpio28",
0332 };
0333
0334 static const char * const dsl_ntr_pulse_out_groups[] = {
0335     "gpio15",
0336     "gpio29",
0337 };
0338
0339 static const char * const adsl_spi_miso_groups[] = {
0340     "gpio18",
0341 };
0342
0343 static const char * const adsl_spi_mosi_groups[] = {
0344     "gpio19",
0345 };
0346
0347 static const char * const vreg_clk_groups[] = {
0348     "gpio22",
0349 };
0350
0351 static const char * const pcie_clkreq_b_groups[] = {
0352     "gpio23",
0353 };
0354
0355 static const char * const switch_led_clk_groups[] = {
0356     "gpio30",
0357 };
0358
0359 static const char * const switch_led_data_groups[] = {
0360     "gpio31",
0361 };
0362
0363 static const char * const wifi_groups[] = {
0364     "gpio32",
0365     "gpio33",
0366     "gpio34",
0367     "gpio35",
0368     "gpio36",
0369     "gpio37",
0370     "gpio38",
0371     "gpio39",
0372     "gpio40",
0373     "gpio41",
0374     "gpio42",
0375     "gpio43",
0376     "gpio44",
0377     "gpio45",
0378     "gpio46",
0379     "gpio47",
0380     "gpio48",
0381     "gpio49",
0382     "gpio50",
0383     "gpio51",
0384 };
0385
0386 static const char * const nand_groups[] = {
0387     "nand_grp",
0388 };
0389
0390 static const char * const dectpd_groups[] = {
0391     "dectpd_grp",
0392 };
0393
0394 static const char * const vdsl_phy_override_0_groups[] = {
0395     "vdsl_phy_override_0_grp",
0396 };
0397
0398 static const char * const vdsl_phy_override_1_groups[] = {
0399     "vdsl_phy_override_1_grp",
0400 };
0401
0402 static const char * const vdsl_phy_override_2_groups[] = {
0403     "vdsl_phy_override_2_grp",
0404 };
0405
0406 static const char * const vdsl_phy_override_3_groups[] = {
0407     "vdsl_phy_override_3_grp",
0408 };
0409
0410 #define BCM63268_LED_FUN(n)             \
0411     {                       \
0412         .name = #n,             \
0413         .groups = n##_groups,           \
0414         .num_groups = ARRAY_SIZE(n##_groups),   \
0415         .reg = BCM63268_LEDCTRL,        \
0416     }
0417
0418 #define BCM63268_MODE_FUN(n)                \
0419     {                       \
0420         .name = #n,             \
0421         .groups = n##_groups,           \
0422         .num_groups = ARRAY_SIZE(n##_groups),   \
0423         .reg = BCM63268_MODE,           \
0424     }
0425
0426 #define BCM63268_CTRL_FUN(n)                \
0427     {                       \
0428         .name = #n,             \
0429         .groups = n##_groups,           \
0430         .num_groups = ARRAY_SIZE(n##_groups),   \
0431         .reg = BCM63268_CTRL,           \
0432     }
0433
0434 #define BCM63268_BASEMODE_FUN(n, val)           \
0435     {                       \
0436         .name = #n,             \
0437         .groups = n##_groups,           \
0438         .num_groups = ARRAY_SIZE(n##_groups),   \
0439         .reg = BCM63268_BASEMODE,       \
0440         .mask = val,                \
0441     }
0442
0443 static const struct bcm63268_function bcm63268_funcs[] = {
0444     BCM63268_LED_FUN(led),
0445     BCM63268_MODE_FUN(serial_led_clk),
0446     BCM63268_MODE_FUN(serial_led_data),
0447     BCM63268_MODE_FUN(hsspi_cs6),
0448     BCM63268_MODE_FUN(hsspi_cs7),
0449     BCM63268_MODE_FUN(uart1_scts),
0450     BCM63268_MODE_FUN(uart1_srts),
0451     BCM63268_MODE_FUN(uart1_sdin),
0452     BCM63268_MODE_FUN(uart1_sdout),
0453     BCM63268_MODE_FUN(ntr_pulse_in),
0454     BCM63268_MODE_FUN(dsl_ntr_pulse_out),
0455     BCM63268_MODE_FUN(hsspi_cs4),
0456     BCM63268_MODE_FUN(hsspi_cs5),
0457     BCM63268_MODE_FUN(adsl_spi_miso),
0458     BCM63268_MODE_FUN(adsl_spi_mosi),
0459     BCM63268_MODE_FUN(vreg_clk),
0460     BCM63268_MODE_FUN(pcie_clkreq_b),
0461     BCM63268_MODE_FUN(switch_led_clk),
0462     BCM63268_MODE_FUN(switch_led_data),
0463     BCM63268_CTRL_FUN(wifi),
0464     BCM63268_BASEMODE_FUN(nand, BCM63268_BASEMODE_NAND),
0465     BCM63268_BASEMODE_FUN(dectpd, BCM63268_BASEMODE_DECTPD),
0466     BCM63268_BASEMODE_FUN(vdsl_phy_override_0,
0467                   BCM63268_BASEMODE_VDSL_PHY_0),
0468     BCM63268_BASEMODE_FUN(vdsl_phy_override_1,
0469                   BCM63268_BASEMODE_VDSL_PHY_1),
0470     BCM63268_BASEMODE_FUN(vdsl_phy_override_2,
0471                   BCM63268_BASEMODE_VDSL_PHY_2),
0472     BCM63268_BASEMODE_FUN(vdsl_phy_override_3,
0473                   BCM63268_BASEMODE_VDSL_PHY_3),
0474 };
0475
0476 static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
0477 {
0478     return ARRAY_SIZE(bcm63268_groups);
0479 }
0480
0481 static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0482                            unsigned group)
0483 {
0484     return bcm63268_groups[group].name;
0485 }
0486
0487 static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0488                        unsigned group,
0489                        const unsigned **pins,
0490                        unsigned *num_pins)
0491 {
0492     *pins = bcm63268_groups[group].pins;
0493     *num_pins = bcm63268_groups[group].num_pins;
0494
0495     return 0;
0496 }
0497
0498 static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
0499 {
0500     return ARRAY_SIZE(bcm63268_funcs);
0501 }
0502
0503 static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
0504                           unsigned selector)
0505 {
0506     return bcm63268_funcs[selector].name;
0507 }
0508
0509 static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev,
0510                        unsigned selector,
0511                        const char * const **groups,
0512                        unsigned * const num_groups)
0513 {
0514     *groups = bcm63268_funcs[selector].groups;
0515     *num_groups = bcm63268_funcs[selector].num_groups;
0516
0517     return 0;
0518 }
0519
0520 static void bcm63268_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)
0521 {
0522     const struct pinctrl_pin_desc *desc = &bcm63268_pins[pin];
0523     unsigned int basemode = (unsigned long) desc->drv_data;
0524     unsigned int mask = BIT(bcm63xx_bank_pin(pin));
0525
0526     if (basemode)
0527         regmap_update_bits(pc->regs, BCM63268_BASEMODE_REG, basemode,
0528                    0);
0529
0530     if (pin < BCM63XX_BANK_GPIOS) {
0531         /* base mode: 0 => gpio, 1 => mux function */
0532         regmap_update_bits(pc->regs, BCM63268_MODE_REG, mask, 0);
0533
0534         /* pins 0-23 might be muxed to led */
0535         if (pin < BCM63268_NUM_LEDS)
0536             regmap_update_bits(pc->regs, BCM63268_LED_REG, mask,
0537                        0);
0538     } else if (pin < BCM63268_NUM_GPIOS) {
0539         /* ctrl reg: 0 => wifi function, 1 => gpio */
0540         regmap_update_bits(pc->regs, BCM63268_CTRL_REG, mask, mask);
0541     }
0542 }
0543
0544 static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,
0545                     unsigned selector, unsigned group)
0546 {
0547     struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
0548     const struct bcm63268_pingroup *pg = &bcm63268_groups[group];
0549     const struct bcm63268_function *f = &bcm63268_funcs[selector];
0550     unsigned i;
0551     unsigned int reg;
0552     unsigned int val, mask;
0553
0554     for (i = 0; i < pg->num_pins; i++)
0555         bcm63268_set_gpio(pc, pg->pins[i]);
0556
0557     switch (f->reg) {
0558     case BCM63268_LEDCTRL:
0559         reg = BCM63268_LED_REG;
0560         mask = BIT(pg->pins[0]);
0561         val = BIT(pg->pins[0]);
0562         break;
0563     case BCM63268_MODE:
0564         reg = BCM63268_MODE_REG;
0565         mask = BIT(pg->pins[0]);
0566         val = BIT(pg->pins[0]);
0567         break;
0568     case BCM63268_CTRL:
0569         reg = BCM63268_CTRL_REG;
0570         mask = BIT(pg->pins[0]);
0571         val = 0;
0572         break;
0573     case BCM63268_BASEMODE:
0574         reg = BCM63268_BASEMODE_REG;
0575         mask = f->mask;
0576         val = f->mask;
0577         break;
0578     default:
0579         WARN_ON(1);
0580         return -EINVAL;
0581     }
0582
0583     regmap_update_bits(pc->regs, reg, mask, val);
0584
0585     return 0;
0586 }
0587
0588 static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev,
0589                     struct pinctrl_gpio_range *range,
0590                     unsigned offset)
0591 {
0592     struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
0593
0594     /* disable all functions using this pin */
0595     bcm63268_set_gpio(pc, offset);
0596
0597     return 0;
0598 }
0599
0600 static const struct pinctrl_ops bcm63268_pctl_ops = {
0601     .dt_free_map = pinctrl_utils_free_map,
0602     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0603     .get_group_name = bcm63268_pinctrl_get_group_name,
0604     .get_group_pins = bcm63268_pinctrl_get_group_pins,
0605     .get_groups_count = bcm63268_pinctrl_get_group_count,
0606 };
0607
0608 static const struct pinmux_ops bcm63268_pmx_ops = {
0609     .get_function_groups = bcm63268_pinctrl_get_groups,
0610     .get_function_name = bcm63268_pinctrl_get_func_name,
0611     .get_functions_count = bcm63268_pinctrl_get_func_count,
0612     .gpio_request_enable = bcm63268_gpio_request_enable,
0613     .set_mux = bcm63268_pinctrl_set_mux,
0614     .strict = true,
0615 };
0616
0617 static const struct bcm63xx_pinctrl_soc bcm63268_soc = {
0618     .ngpios = BCM63268_NUM_GPIOS,
0619     .npins = ARRAY_SIZE(bcm63268_pins),
0620     .pctl_ops = &bcm63268_pctl_ops,
0621     .pins = bcm63268_pins,
0622     .pmx_ops = &bcm63268_pmx_ops,
0623 };
0624
0625 static int bcm63268_pinctrl_probe(struct platform_device *pdev)
0626 {
0627     return bcm63xx_pinctrl_probe(pdev, &bcm63268_soc, NULL);
0628 }
0629
0630 static const struct of_device_id bcm63268_pinctrl_match[] = {
0631     { .compatible = "brcm,bcm63268-pinctrl", },
0632     { /* sentinel */ }
0633 };
0634
0635 static struct platform_driver bcm63268_pinctrl_driver = {
0636     .probe = bcm63268_pinctrl_probe,
0637     .driver = {
0638         .name = "bcm63268-pinctrl",
0639         .of_match_table = bcm63268_pinctrl_match,
0640     },
0641 };
0642
0643 builtin_platform_driver(bcm63268_pinctrl_driver);