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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
0004  *
0005  * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
0006  *
0007  * This driver is inspired by:
0008  * pinctrl-nomadik.c, please see original file for copyright information
0009  * pinctrl-tegra.c, please see original file for copyright information
0010  */
0011 
0012 #include <linux/bitmap.h>
0013 #include <linux/bug.h>
0014 #include <linux/delay.h>
0015 #include <linux/device.h>
0016 #include <linux/err.h>
0017 #include <linux/gpio/driver.h>
0018 #include <linux/io.h>
0019 #include <linux/irq.h>
0020 #include <linux/irqdesc.h>
0021 #include <linux/init.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/module.h>
0024 #include <linux/of_address.h>
0025 #include <linux/of.h>
0026 #include <linux/of_irq.h>
0027 #include <linux/pinctrl/consumer.h>
0028 #include <linux/pinctrl/machine.h>
0029 #include <linux/pinctrl/pinconf.h>
0030 #include <linux/pinctrl/pinctrl.h>
0031 #include <linux/pinctrl/pinmux.h>
0032 #include <linux/pinctrl/pinconf-generic.h>
0033 #include <linux/platform_device.h>
0034 #include <linux/seq_file.h>
0035 #include <linux/slab.h>
0036 #include <linux/spinlock.h>
0037 #include <linux/types.h>
0038 #include <dt-bindings/pinctrl/bcm2835.h>
0039 
0040 #define MODULE_NAME "pinctrl-bcm2835"
0041 #define BCM2835_NUM_GPIOS 54
0042 #define BCM2711_NUM_GPIOS 58
0043 #define BCM2835_NUM_BANKS 2
0044 #define BCM2835_NUM_IRQS  3
0045 
0046 /* GPIO register offsets */
0047 #define GPFSEL0     0x0 /* Function Select */
0048 #define GPSET0      0x1c    /* Pin Output Set */
0049 #define GPCLR0      0x28    /* Pin Output Clear */
0050 #define GPLEV0      0x34    /* Pin Level */
0051 #define GPEDS0      0x40    /* Pin Event Detect Status */
0052 #define GPREN0      0x4c    /* Pin Rising Edge Detect Enable */
0053 #define GPFEN0      0x58    /* Pin Falling Edge Detect Enable */
0054 #define GPHEN0      0x64    /* Pin High Detect Enable */
0055 #define GPLEN0      0x70    /* Pin Low Detect Enable */
0056 #define GPAREN0     0x7c    /* Pin Async Rising Edge Detect */
0057 #define GPAFEN0     0x88    /* Pin Async Falling Edge Detect */
0058 #define GPPUD       0x94    /* Pin Pull-up/down Enable */
0059 #define GPPUDCLK0   0x98    /* Pin Pull-up/down Enable Clock */
0060 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
0061 
0062 #define FSEL_REG(p)     (GPFSEL0 + (((p) / 10) * 4))
0063 #define FSEL_SHIFT(p)       (((p) % 10) * 3)
0064 #define GPIO_REG_OFFSET(p)  ((p) / 32)
0065 #define GPIO_REG_SHIFT(p)   ((p) % 32)
0066 
0067 #define PUD_2711_MASK       0x3
0068 #define PUD_2711_REG_OFFSET(p)  ((p) / 16)
0069 #define PUD_2711_REG_SHIFT(p)   (((p) % 16) * 2)
0070 
0071 /* argument: bcm2835_pinconf_pull */
0072 #define BCM2835_PINCONF_PARAM_PULL  (PIN_CONFIG_END + 1)
0073 
0074 #define BCM2711_PULL_NONE   0x0
0075 #define BCM2711_PULL_UP     0x1
0076 #define BCM2711_PULL_DOWN   0x2
0077 
0078 struct bcm2835_pinctrl {
0079     struct device *dev;
0080     void __iomem *base;
0081     int *wake_irq;
0082 
0083     /* note: locking assumes each bank will have its own unsigned long */
0084     unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
0085     unsigned int irq_type[BCM2711_NUM_GPIOS];
0086 
0087     struct pinctrl_dev *pctl_dev;
0088     struct gpio_chip gpio_chip;
0089     struct pinctrl_desc pctl_desc;
0090     struct pinctrl_gpio_range gpio_range;
0091 
0092     raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
0093 };
0094 
0095 /* pins are just named GPIO0..GPIO53 */
0096 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
0097 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
0098     BCM2835_GPIO_PIN(0),
0099     BCM2835_GPIO_PIN(1),
0100     BCM2835_GPIO_PIN(2),
0101     BCM2835_GPIO_PIN(3),
0102     BCM2835_GPIO_PIN(4),
0103     BCM2835_GPIO_PIN(5),
0104     BCM2835_GPIO_PIN(6),
0105     BCM2835_GPIO_PIN(7),
0106     BCM2835_GPIO_PIN(8),
0107     BCM2835_GPIO_PIN(9),
0108     BCM2835_GPIO_PIN(10),
0109     BCM2835_GPIO_PIN(11),
0110     BCM2835_GPIO_PIN(12),
0111     BCM2835_GPIO_PIN(13),
0112     BCM2835_GPIO_PIN(14),
0113     BCM2835_GPIO_PIN(15),
0114     BCM2835_GPIO_PIN(16),
0115     BCM2835_GPIO_PIN(17),
0116     BCM2835_GPIO_PIN(18),
0117     BCM2835_GPIO_PIN(19),
0118     BCM2835_GPIO_PIN(20),
0119     BCM2835_GPIO_PIN(21),
0120     BCM2835_GPIO_PIN(22),
0121     BCM2835_GPIO_PIN(23),
0122     BCM2835_GPIO_PIN(24),
0123     BCM2835_GPIO_PIN(25),
0124     BCM2835_GPIO_PIN(26),
0125     BCM2835_GPIO_PIN(27),
0126     BCM2835_GPIO_PIN(28),
0127     BCM2835_GPIO_PIN(29),
0128     BCM2835_GPIO_PIN(30),
0129     BCM2835_GPIO_PIN(31),
0130     BCM2835_GPIO_PIN(32),
0131     BCM2835_GPIO_PIN(33),
0132     BCM2835_GPIO_PIN(34),
0133     BCM2835_GPIO_PIN(35),
0134     BCM2835_GPIO_PIN(36),
0135     BCM2835_GPIO_PIN(37),
0136     BCM2835_GPIO_PIN(38),
0137     BCM2835_GPIO_PIN(39),
0138     BCM2835_GPIO_PIN(40),
0139     BCM2835_GPIO_PIN(41),
0140     BCM2835_GPIO_PIN(42),
0141     BCM2835_GPIO_PIN(43),
0142     BCM2835_GPIO_PIN(44),
0143     BCM2835_GPIO_PIN(45),
0144     BCM2835_GPIO_PIN(46),
0145     BCM2835_GPIO_PIN(47),
0146     BCM2835_GPIO_PIN(48),
0147     BCM2835_GPIO_PIN(49),
0148     BCM2835_GPIO_PIN(50),
0149     BCM2835_GPIO_PIN(51),
0150     BCM2835_GPIO_PIN(52),
0151     BCM2835_GPIO_PIN(53),
0152     BCM2835_GPIO_PIN(54),
0153     BCM2835_GPIO_PIN(55),
0154     BCM2835_GPIO_PIN(56),
0155     BCM2835_GPIO_PIN(57),
0156 };
0157 
0158 /* one pin per group */
0159 static const char * const bcm2835_gpio_groups[] = {
0160     "gpio0",
0161     "gpio1",
0162     "gpio2",
0163     "gpio3",
0164     "gpio4",
0165     "gpio5",
0166     "gpio6",
0167     "gpio7",
0168     "gpio8",
0169     "gpio9",
0170     "gpio10",
0171     "gpio11",
0172     "gpio12",
0173     "gpio13",
0174     "gpio14",
0175     "gpio15",
0176     "gpio16",
0177     "gpio17",
0178     "gpio18",
0179     "gpio19",
0180     "gpio20",
0181     "gpio21",
0182     "gpio22",
0183     "gpio23",
0184     "gpio24",
0185     "gpio25",
0186     "gpio26",
0187     "gpio27",
0188     "gpio28",
0189     "gpio29",
0190     "gpio30",
0191     "gpio31",
0192     "gpio32",
0193     "gpio33",
0194     "gpio34",
0195     "gpio35",
0196     "gpio36",
0197     "gpio37",
0198     "gpio38",
0199     "gpio39",
0200     "gpio40",
0201     "gpio41",
0202     "gpio42",
0203     "gpio43",
0204     "gpio44",
0205     "gpio45",
0206     "gpio46",
0207     "gpio47",
0208     "gpio48",
0209     "gpio49",
0210     "gpio50",
0211     "gpio51",
0212     "gpio52",
0213     "gpio53",
0214     "gpio54",
0215     "gpio55",
0216     "gpio56",
0217     "gpio57",
0218 };
0219 
0220 enum bcm2835_fsel {
0221     BCM2835_FSEL_COUNT = 8,
0222     BCM2835_FSEL_MASK = 0x7,
0223 };
0224 
0225 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
0226     [BCM2835_FSEL_GPIO_IN] = "gpio_in",
0227     [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
0228     [BCM2835_FSEL_ALT0] = "alt0",
0229     [BCM2835_FSEL_ALT1] = "alt1",
0230     [BCM2835_FSEL_ALT2] = "alt2",
0231     [BCM2835_FSEL_ALT3] = "alt3",
0232     [BCM2835_FSEL_ALT4] = "alt4",
0233     [BCM2835_FSEL_ALT5] = "alt5",
0234 };
0235 
0236 static const char * const irq_type_names[] = {
0237     [IRQ_TYPE_NONE] = "none",
0238     [IRQ_TYPE_EDGE_RISING] = "edge-rising",
0239     [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
0240     [IRQ_TYPE_EDGE_BOTH] = "edge-both",
0241     [IRQ_TYPE_LEVEL_HIGH] = "level-high",
0242     [IRQ_TYPE_LEVEL_LOW] = "level-low",
0243 };
0244 
0245 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
0246 {
0247     return readl(pc->base + reg);
0248 }
0249 
0250 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
0251         u32 val)
0252 {
0253     writel(val, pc->base + reg);
0254 }
0255 
0256 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
0257         unsigned bit)
0258 {
0259     reg += GPIO_REG_OFFSET(bit) * 4;
0260     return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
0261 }
0262 
0263 /* note NOT a read/modify/write cycle */
0264 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
0265         unsigned reg, unsigned bit)
0266 {
0267     reg += GPIO_REG_OFFSET(bit) * 4;
0268     bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
0269 }
0270 
0271 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
0272         struct bcm2835_pinctrl *pc, unsigned pin)
0273 {
0274     u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
0275     enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
0276 
0277     dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
0278             bcm2835_functions[status]);
0279 
0280     return status;
0281 }
0282 
0283 static inline void bcm2835_pinctrl_fsel_set(
0284         struct bcm2835_pinctrl *pc, unsigned pin,
0285         enum bcm2835_fsel fsel)
0286 {
0287     u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
0288     enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
0289 
0290     dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
0291             bcm2835_functions[cur]);
0292 
0293     if (cur == fsel)
0294         return;
0295 
0296     if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
0297         /* always transition through GPIO_IN */
0298         val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
0299         val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
0300 
0301         dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
0302                 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
0303         bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
0304     }
0305 
0306     val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
0307     val |= fsel << FSEL_SHIFT(pin);
0308 
0309     dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
0310             bcm2835_functions[fsel]);
0311     bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
0312 }
0313 
0314 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
0315 {
0316     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0317 
0318     bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
0319     return 0;
0320 }
0321 
0322 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
0323 {
0324     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0325 
0326     return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
0327 }
0328 
0329 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
0330 {
0331     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0332     enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
0333 
0334     /* Alternative function doesn't clearly provide a direction */
0335     if (fsel > BCM2835_FSEL_GPIO_OUT)
0336         return -EINVAL;
0337 
0338     if (fsel == BCM2835_FSEL_GPIO_IN)
0339         return GPIO_LINE_DIRECTION_IN;
0340 
0341     return GPIO_LINE_DIRECTION_OUT;
0342 }
0343 
0344 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0345 {
0346     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0347 
0348     bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
0349 }
0350 
0351 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
0352         unsigned offset, int value)
0353 {
0354     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0355 
0356     bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
0357     bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
0358     return 0;
0359 }
0360 
0361 static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc,
0362                        struct device_node *np)
0363 {
0364     struct pinctrl_dev *pctldev = of_pinctrl_get(np);
0365 
0366     of_node_put(np);
0367 
0368     if (!pctldev)
0369         return 0;
0370 
0371     gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
0372                    gc->ngpio);
0373 
0374     return 0;
0375 }
0376 
0377 static const struct gpio_chip bcm2835_gpio_chip = {
0378     .label = MODULE_NAME,
0379     .owner = THIS_MODULE,
0380     .request = gpiochip_generic_request,
0381     .free = gpiochip_generic_free,
0382     .direction_input = bcm2835_gpio_direction_input,
0383     .direction_output = bcm2835_gpio_direction_output,
0384     .get_direction = bcm2835_gpio_get_direction,
0385     .get = bcm2835_gpio_get,
0386     .set = bcm2835_gpio_set,
0387     .set_config = gpiochip_generic_config,
0388     .base = -1,
0389     .ngpio = BCM2835_NUM_GPIOS,
0390     .can_sleep = false,
0391     .of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
0392 };
0393 
0394 static const struct gpio_chip bcm2711_gpio_chip = {
0395     .label = "pinctrl-bcm2711",
0396     .owner = THIS_MODULE,
0397     .request = gpiochip_generic_request,
0398     .free = gpiochip_generic_free,
0399     .direction_input = bcm2835_gpio_direction_input,
0400     .direction_output = bcm2835_gpio_direction_output,
0401     .get_direction = bcm2835_gpio_get_direction,
0402     .get = bcm2835_gpio_get,
0403     .set = bcm2835_gpio_set,
0404     .set_config = gpiochip_generic_config,
0405     .base = -1,
0406     .ngpio = BCM2711_NUM_GPIOS,
0407     .can_sleep = false,
0408     .of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
0409 };
0410 
0411 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
0412                      unsigned int bank, u32 mask)
0413 {
0414     unsigned long events;
0415     unsigned offset;
0416     unsigned gpio;
0417 
0418     events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
0419     events &= mask;
0420     events &= pc->enabled_irq_map[bank];
0421     for_each_set_bit(offset, &events, 32) {
0422         gpio = (32 * bank) + offset;
0423         generic_handle_domain_irq(pc->gpio_chip.irq.domain,
0424                       gpio);
0425     }
0426 }
0427 
0428 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
0429 {
0430     struct gpio_chip *chip = irq_desc_get_handler_data(desc);
0431     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0432     struct irq_chip *host_chip = irq_desc_get_chip(desc);
0433     int irq = irq_desc_get_irq(desc);
0434     int group = 0;
0435     int i;
0436 
0437     for (i = 0; i < BCM2835_NUM_IRQS; i++) {
0438         if (chip->irq.parents[i] == irq) {
0439             group = i;
0440             break;
0441         }
0442     }
0443     /* This should not happen, every IRQ has a bank */
0444     BUG_ON(i == BCM2835_NUM_IRQS);
0445 
0446     chained_irq_enter(host_chip, desc);
0447 
0448     switch (group) {
0449     case 0: /* IRQ0 covers GPIOs 0-27 */
0450         bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
0451         break;
0452     case 1: /* IRQ1 covers GPIOs 28-45 */
0453         bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
0454         bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
0455         break;
0456     case 2: /* IRQ2 covers GPIOs 46-57 */
0457         bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
0458         break;
0459     }
0460 
0461     chained_irq_exit(host_chip, desc);
0462 }
0463 
0464 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
0465 {
0466     return IRQ_HANDLED;
0467 }
0468 
0469 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
0470     unsigned reg, unsigned offset, bool enable)
0471 {
0472     u32 value;
0473     reg += GPIO_REG_OFFSET(offset) * 4;
0474     value = bcm2835_gpio_rd(pc, reg);
0475     if (enable)
0476         value |= BIT(GPIO_REG_SHIFT(offset));
0477     else
0478         value &= ~(BIT(GPIO_REG_SHIFT(offset)));
0479     bcm2835_gpio_wr(pc, reg, value);
0480 }
0481 
0482 /* fast path for IRQ handler */
0483 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
0484     unsigned offset, bool enable)
0485 {
0486     switch (pc->irq_type[offset]) {
0487     case IRQ_TYPE_EDGE_RISING:
0488         __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
0489         break;
0490 
0491     case IRQ_TYPE_EDGE_FALLING:
0492         __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
0493         break;
0494 
0495     case IRQ_TYPE_EDGE_BOTH:
0496         __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
0497         __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
0498         break;
0499 
0500     case IRQ_TYPE_LEVEL_HIGH:
0501         __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
0502         break;
0503 
0504     case IRQ_TYPE_LEVEL_LOW:
0505         __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
0506         break;
0507     }
0508 }
0509 
0510 static void bcm2835_gpio_irq_unmask(struct irq_data *data)
0511 {
0512     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0513     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0514     unsigned gpio = irqd_to_hwirq(data);
0515     unsigned offset = GPIO_REG_SHIFT(gpio);
0516     unsigned bank = GPIO_REG_OFFSET(gpio);
0517     unsigned long flags;
0518 
0519     gpiochip_enable_irq(chip, gpio);
0520 
0521     raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
0522     set_bit(offset, &pc->enabled_irq_map[bank]);
0523     bcm2835_gpio_irq_config(pc, gpio, true);
0524     raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
0525 }
0526 
0527 static void bcm2835_gpio_irq_mask(struct irq_data *data)
0528 {
0529     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0530     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0531     unsigned gpio = irqd_to_hwirq(data);
0532     unsigned offset = GPIO_REG_SHIFT(gpio);
0533     unsigned bank = GPIO_REG_OFFSET(gpio);
0534     unsigned long flags;
0535 
0536     raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
0537     bcm2835_gpio_irq_config(pc, gpio, false);
0538     /* Clear events that were latched prior to clearing event sources */
0539     bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
0540     clear_bit(offset, &pc->enabled_irq_map[bank]);
0541     raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
0542 
0543     gpiochip_disable_irq(chip, gpio);
0544 }
0545 
0546 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
0547     unsigned offset, unsigned int type)
0548 {
0549     switch (type) {
0550     case IRQ_TYPE_NONE:
0551     case IRQ_TYPE_EDGE_RISING:
0552     case IRQ_TYPE_EDGE_FALLING:
0553     case IRQ_TYPE_EDGE_BOTH:
0554     case IRQ_TYPE_LEVEL_HIGH:
0555     case IRQ_TYPE_LEVEL_LOW:
0556         pc->irq_type[offset] = type;
0557         break;
0558 
0559     default:
0560         return -EINVAL;
0561     }
0562     return 0;
0563 }
0564 
0565 /* slower path for reconfiguring IRQ type */
0566 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
0567     unsigned offset, unsigned int type)
0568 {
0569     switch (type) {
0570     case IRQ_TYPE_NONE:
0571         if (pc->irq_type[offset] != type) {
0572             bcm2835_gpio_irq_config(pc, offset, false);
0573             pc->irq_type[offset] = type;
0574         }
0575         break;
0576 
0577     case IRQ_TYPE_EDGE_RISING:
0578         if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
0579             /* RISING already enabled, disable FALLING */
0580             pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
0581             bcm2835_gpio_irq_config(pc, offset, false);
0582             pc->irq_type[offset] = type;
0583         } else if (pc->irq_type[offset] != type) {
0584             bcm2835_gpio_irq_config(pc, offset, false);
0585             pc->irq_type[offset] = type;
0586             bcm2835_gpio_irq_config(pc, offset, true);
0587         }
0588         break;
0589 
0590     case IRQ_TYPE_EDGE_FALLING:
0591         if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
0592             /* FALLING already enabled, disable RISING */
0593             pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
0594             bcm2835_gpio_irq_config(pc, offset, false);
0595             pc->irq_type[offset] = type;
0596         } else if (pc->irq_type[offset] != type) {
0597             bcm2835_gpio_irq_config(pc, offset, false);
0598             pc->irq_type[offset] = type;
0599             bcm2835_gpio_irq_config(pc, offset, true);
0600         }
0601         break;
0602 
0603     case IRQ_TYPE_EDGE_BOTH:
0604         if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
0605             /* RISING already enabled, enable FALLING too */
0606             pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
0607             bcm2835_gpio_irq_config(pc, offset, true);
0608             pc->irq_type[offset] = type;
0609         } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
0610             /* FALLING already enabled, enable RISING too */
0611             pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
0612             bcm2835_gpio_irq_config(pc, offset, true);
0613             pc->irq_type[offset] = type;
0614         } else if (pc->irq_type[offset] != type) {
0615             bcm2835_gpio_irq_config(pc, offset, false);
0616             pc->irq_type[offset] = type;
0617             bcm2835_gpio_irq_config(pc, offset, true);
0618         }
0619         break;
0620 
0621     case IRQ_TYPE_LEVEL_HIGH:
0622     case IRQ_TYPE_LEVEL_LOW:
0623         if (pc->irq_type[offset] != type) {
0624             bcm2835_gpio_irq_config(pc, offset, false);
0625             pc->irq_type[offset] = type;
0626             bcm2835_gpio_irq_config(pc, offset, true);
0627         }
0628         break;
0629 
0630     default:
0631         return -EINVAL;
0632     }
0633     return 0;
0634 }
0635 
0636 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
0637 {
0638     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0639     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0640     unsigned gpio = irqd_to_hwirq(data);
0641     unsigned offset = GPIO_REG_SHIFT(gpio);
0642     unsigned bank = GPIO_REG_OFFSET(gpio);
0643     unsigned long flags;
0644     int ret;
0645 
0646     raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
0647 
0648     if (test_bit(offset, &pc->enabled_irq_map[bank]))
0649         ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
0650     else
0651         ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
0652 
0653     if (type & IRQ_TYPE_EDGE_BOTH)
0654         irq_set_handler_locked(data, handle_edge_irq);
0655     else
0656         irq_set_handler_locked(data, handle_level_irq);
0657 
0658     raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
0659 
0660     return ret;
0661 }
0662 
0663 static void bcm2835_gpio_irq_ack(struct irq_data *data)
0664 {
0665     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0666     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0667     unsigned gpio = irqd_to_hwirq(data);
0668 
0669     bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
0670 }
0671 
0672 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
0673 {
0674     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0675     struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
0676     unsigned gpio = irqd_to_hwirq(data);
0677     unsigned int irqgroup;
0678     int ret = -EINVAL;
0679 
0680     if (!pc->wake_irq)
0681         return ret;
0682 
0683     if (gpio <= 27)
0684         irqgroup = 0;
0685     else if (gpio >= 28 && gpio <= 45)
0686         irqgroup = 1;
0687     else if (gpio >= 46 && gpio <= 57)
0688         irqgroup = 2;
0689     else
0690         return ret;
0691 
0692     if (on)
0693         ret = enable_irq_wake(pc->wake_irq[irqgroup]);
0694     else
0695         ret = disable_irq_wake(pc->wake_irq[irqgroup]);
0696 
0697     return ret;
0698 }
0699 
0700 static const struct irq_chip bcm2835_gpio_irq_chip = {
0701     .name = MODULE_NAME,
0702     .irq_set_type = bcm2835_gpio_irq_set_type,
0703     .irq_ack = bcm2835_gpio_irq_ack,
0704     .irq_mask = bcm2835_gpio_irq_mask,
0705     .irq_unmask = bcm2835_gpio_irq_unmask,
0706     .irq_set_wake = bcm2835_gpio_irq_set_wake,
0707     .flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE),
0708     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0709 };
0710 
0711 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
0712 {
0713     return BCM2835_NUM_GPIOS;
0714 }
0715 
0716 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
0717         unsigned selector)
0718 {
0719     return bcm2835_gpio_groups[selector];
0720 }
0721 
0722 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
0723         unsigned selector,
0724         const unsigned **pins,
0725         unsigned *num_pins)
0726 {
0727     *pins = &bcm2835_gpio_pins[selector].number;
0728     *num_pins = 1;
0729 
0730     return 0;
0731 }
0732 
0733 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
0734         struct seq_file *s,
0735         unsigned offset)
0736 {
0737     struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
0738     struct gpio_chip *chip = &pc->gpio_chip;
0739     enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
0740     const char *fname = bcm2835_functions[fsel];
0741     int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
0742     int irq = irq_find_mapping(chip->irq.domain, offset);
0743 
0744     seq_printf(s, "function %s in %s; irq %d (%s)",
0745         fname, value ? "hi" : "lo",
0746         irq, irq_type_names[pc->irq_type[offset]]);
0747 }
0748 
0749 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
0750         struct pinctrl_map *maps, unsigned num_maps)
0751 {
0752     int i;
0753 
0754     for (i = 0; i < num_maps; i++)
0755         if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
0756             kfree(maps[i].data.configs.configs);
0757 
0758     kfree(maps);
0759 }
0760 
0761 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
0762         struct device_node *np, u32 pin, u32 fnum,
0763         struct pinctrl_map **maps)
0764 {
0765     struct pinctrl_map *map = *maps;
0766 
0767     if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
0768         dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
0769         return -EINVAL;
0770     }
0771 
0772     map->type = PIN_MAP_TYPE_MUX_GROUP;
0773     map->data.mux.group = bcm2835_gpio_groups[pin];
0774     map->data.mux.function = bcm2835_functions[fnum];
0775     (*maps)++;
0776 
0777     return 0;
0778 }
0779 
0780 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
0781         struct device_node *np, u32 pin, u32 pull,
0782         struct pinctrl_map **maps)
0783 {
0784     struct pinctrl_map *map = *maps;
0785     unsigned long *configs;
0786 
0787     if (pull > 2) {
0788         dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
0789         return -EINVAL;
0790     }
0791 
0792     configs = kzalloc(sizeof(*configs), GFP_KERNEL);
0793     if (!configs)
0794         return -ENOMEM;
0795     configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
0796 
0797     map->type = PIN_MAP_TYPE_CONFIGS_PIN;
0798     map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
0799     map->data.configs.configs = configs;
0800     map->data.configs.num_configs = 1;
0801     (*maps)++;
0802 
0803     return 0;
0804 }
0805 
0806 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
0807         struct device_node *np,
0808         struct pinctrl_map **map, unsigned int *num_maps)
0809 {
0810     struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
0811     struct property *pins, *funcs, *pulls;
0812     int num_pins, num_funcs, num_pulls, maps_per_pin;
0813     struct pinctrl_map *maps, *cur_map;
0814     int i, err;
0815     u32 pin, func, pull;
0816 
0817     /* Check for generic binding in this node */
0818     err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
0819     if (err || *num_maps)
0820         return err;
0821 
0822     /* Generic binding did not find anything continue with legacy parse */
0823     pins = of_find_property(np, "brcm,pins", NULL);
0824     if (!pins) {
0825         dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
0826         return -EINVAL;
0827     }
0828 
0829     funcs = of_find_property(np, "brcm,function", NULL);
0830     pulls = of_find_property(np, "brcm,pull", NULL);
0831 
0832     if (!funcs && !pulls) {
0833         dev_err(pc->dev,
0834             "%pOF: neither brcm,function nor brcm,pull specified\n",
0835             np);
0836         return -EINVAL;
0837     }
0838 
0839     num_pins = pins->length / 4;
0840     num_funcs = funcs ? (funcs->length / 4) : 0;
0841     num_pulls = pulls ? (pulls->length / 4) : 0;
0842 
0843     if (num_funcs > 1 && num_funcs != num_pins) {
0844         dev_err(pc->dev,
0845             "%pOF: brcm,function must have 1 or %d entries\n",
0846             np, num_pins);
0847         return -EINVAL;
0848     }
0849 
0850     if (num_pulls > 1 && num_pulls != num_pins) {
0851         dev_err(pc->dev,
0852             "%pOF: brcm,pull must have 1 or %d entries\n",
0853             np, num_pins);
0854         return -EINVAL;
0855     }
0856 
0857     maps_per_pin = 0;
0858     if (num_funcs)
0859         maps_per_pin++;
0860     if (num_pulls)
0861         maps_per_pin++;
0862     cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
0863                  GFP_KERNEL);
0864     if (!maps)
0865         return -ENOMEM;
0866 
0867     for (i = 0; i < num_pins; i++) {
0868         err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
0869         if (err)
0870             goto out;
0871         if (pin >= pc->pctl_desc.npins) {
0872             dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
0873                 np, pin);
0874             err = -EINVAL;
0875             goto out;
0876         }
0877 
0878         if (num_funcs) {
0879             err = of_property_read_u32_index(np, "brcm,function",
0880                     (num_funcs > 1) ? i : 0, &func);
0881             if (err)
0882                 goto out;
0883             err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
0884                             func, &cur_map);
0885             if (err)
0886                 goto out;
0887         }
0888         if (num_pulls) {
0889             err = of_property_read_u32_index(np, "brcm,pull",
0890                     (num_pulls > 1) ? i : 0, &pull);
0891             if (err)
0892                 goto out;
0893             err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
0894                             pull, &cur_map);
0895             if (err)
0896                 goto out;
0897         }
0898     }
0899 
0900     *map = maps;
0901     *num_maps = num_pins * maps_per_pin;
0902 
0903     return 0;
0904 
0905 out:
0906     bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
0907     return err;
0908 }
0909 
0910 static const struct pinctrl_ops bcm2835_pctl_ops = {
0911     .get_groups_count = bcm2835_pctl_get_groups_count,
0912     .get_group_name = bcm2835_pctl_get_group_name,
0913     .get_group_pins = bcm2835_pctl_get_group_pins,
0914     .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
0915     .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
0916     .dt_free_map = bcm2835_pctl_dt_free_map,
0917 };
0918 
0919 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
0920         unsigned offset)
0921 {
0922     struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
0923 
0924     /* disable by setting to GPIO_IN */
0925     bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
0926     return 0;
0927 }
0928 
0929 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
0930 {
0931     return BCM2835_FSEL_COUNT;
0932 }
0933 
0934 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
0935         unsigned selector)
0936 {
0937     return bcm2835_functions[selector];
0938 }
0939 
0940 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
0941         unsigned selector,
0942         const char * const **groups,
0943         unsigned * const num_groups)
0944 {
0945     /* every pin can do every function */
0946     *groups = bcm2835_gpio_groups;
0947     *num_groups = BCM2835_NUM_GPIOS;
0948 
0949     return 0;
0950 }
0951 
0952 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
0953         unsigned func_selector,
0954         unsigned group_selector)
0955 {
0956     struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
0957 
0958     bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
0959 
0960     return 0;
0961 }
0962 
0963 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
0964         struct pinctrl_gpio_range *range,
0965         unsigned offset)
0966 {
0967     struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
0968 
0969     /* disable by setting to GPIO_IN */
0970     bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
0971 }
0972 
0973 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
0974         struct pinctrl_gpio_range *range,
0975         unsigned offset,
0976         bool input)
0977 {
0978     struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
0979     enum bcm2835_fsel fsel = input ?
0980         BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
0981 
0982     bcm2835_pinctrl_fsel_set(pc, offset, fsel);
0983 
0984     return 0;
0985 }
0986 
0987 static const struct pinmux_ops bcm2835_pmx_ops = {
0988     .free = bcm2835_pmx_free,
0989     .get_functions_count = bcm2835_pmx_get_functions_count,
0990     .get_function_name = bcm2835_pmx_get_function_name,
0991     .get_function_groups = bcm2835_pmx_get_function_groups,
0992     .set_mux = bcm2835_pmx_set,
0993     .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
0994     .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
0995 };
0996 
0997 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
0998             unsigned pin, unsigned long *config)
0999 {
1000     /* No way to read back config in HW */
1001     return -ENOTSUPP;
1002 }
1003 
1004 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
1005         unsigned int pin, unsigned int arg)
1006 {
1007     u32 off, bit;
1008 
1009     off = GPIO_REG_OFFSET(pin);
1010     bit = GPIO_REG_SHIFT(pin);
1011 
1012     bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1013     /*
1014      * BCM2835 datasheet say to wait 150 cycles, but not of what.
1015      * But the VideoCore firmware delay for this operation
1016      * based nearly on the same amount of VPU cycles and this clock
1017      * runs at 250 MHz.
1018      */
1019     udelay(1);
1020     bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1021     udelay(1);
1022     bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1023 }
1024 
1025 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1026             unsigned int pin, unsigned long *configs,
1027             unsigned int num_configs)
1028 {
1029     struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1030     u32 param, arg;
1031     int i;
1032 
1033     for (i = 0; i < num_configs; i++) {
1034         param = pinconf_to_config_param(configs[i]);
1035         arg = pinconf_to_config_argument(configs[i]);
1036 
1037         switch (param) {
1038         /* Set legacy brcm,pull */
1039         case BCM2835_PINCONF_PARAM_PULL:
1040             bcm2835_pull_config_set(pc, pin, arg);
1041             break;
1042 
1043         /* Set pull generic bindings */
1044         case PIN_CONFIG_BIAS_DISABLE:
1045             bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1046             break;
1047 
1048         case PIN_CONFIG_BIAS_PULL_DOWN:
1049             bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1050             break;
1051 
1052         case PIN_CONFIG_BIAS_PULL_UP:
1053             bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1054             break;
1055 
1056         /* Set output-high or output-low */
1057         case PIN_CONFIG_OUTPUT:
1058             bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1059             break;
1060 
1061         default:
1062             return -ENOTSUPP;
1063 
1064         } /* switch param type */
1065     } /* for each config */
1066 
1067     return 0;
1068 }
1069 
1070 static const struct pinconf_ops bcm2835_pinconf_ops = {
1071     .is_generic = true,
1072     .pin_config_get = bcm2835_pinconf_get,
1073     .pin_config_set = bcm2835_pinconf_set,
1074 };
1075 
1076 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1077                     unsigned int pin, unsigned int arg)
1078 {
1079     u32 shifter;
1080     u32 value;
1081     u32 off;
1082 
1083     off = PUD_2711_REG_OFFSET(pin);
1084     shifter = PUD_2711_REG_SHIFT(pin);
1085 
1086     value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1087     value &= ~(PUD_2711_MASK << shifter);
1088     value |= (arg << shifter);
1089     bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1090 }
1091 
1092 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1093                    unsigned int pin, unsigned long *configs,
1094                    unsigned int num_configs)
1095 {
1096     struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1097     u32 param, arg;
1098     int i;
1099 
1100     for (i = 0; i < num_configs; i++) {
1101         param = pinconf_to_config_param(configs[i]);
1102         arg = pinconf_to_config_argument(configs[i]);
1103 
1104         switch (param) {
1105         /* convert legacy brcm,pull */
1106         case BCM2835_PINCONF_PARAM_PULL:
1107             if (arg == BCM2835_PUD_UP)
1108                 arg = BCM2711_PULL_UP;
1109             else if (arg == BCM2835_PUD_DOWN)
1110                 arg = BCM2711_PULL_DOWN;
1111             else
1112                 arg = BCM2711_PULL_NONE;
1113 
1114             bcm2711_pull_config_set(pc, pin, arg);
1115             break;
1116 
1117         /* Set pull generic bindings */
1118         case PIN_CONFIG_BIAS_DISABLE:
1119             bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1120             break;
1121         case PIN_CONFIG_BIAS_PULL_DOWN:
1122             bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1123             break;
1124         case PIN_CONFIG_BIAS_PULL_UP:
1125             bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1126             break;
1127 
1128         /* Set output-high or output-low */
1129         case PIN_CONFIG_OUTPUT:
1130             bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1131             break;
1132 
1133         default:
1134             return -ENOTSUPP;
1135         }
1136     } /* for each config */
1137 
1138     return 0;
1139 }
1140 
1141 static const struct pinconf_ops bcm2711_pinconf_ops = {
1142     .is_generic = true,
1143     .pin_config_get = bcm2835_pinconf_get,
1144     .pin_config_set = bcm2711_pinconf_set,
1145 };
1146 
1147 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1148     .name = MODULE_NAME,
1149     .pins = bcm2835_gpio_pins,
1150     .npins = BCM2835_NUM_GPIOS,
1151     .pctlops = &bcm2835_pctl_ops,
1152     .pmxops = &bcm2835_pmx_ops,
1153     .confops = &bcm2835_pinconf_ops,
1154     .owner = THIS_MODULE,
1155 };
1156 
1157 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1158     .name = "pinctrl-bcm2711",
1159     .pins = bcm2835_gpio_pins,
1160     .npins = BCM2711_NUM_GPIOS,
1161     .pctlops = &bcm2835_pctl_ops,
1162     .pmxops = &bcm2835_pmx_ops,
1163     .confops = &bcm2711_pinconf_ops,
1164     .owner = THIS_MODULE,
1165 };
1166 
1167 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1168     .name = MODULE_NAME,
1169     .npins = BCM2835_NUM_GPIOS,
1170 };
1171 
1172 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1173     .name = "pinctrl-bcm2711",
1174     .npins = BCM2711_NUM_GPIOS,
1175 };
1176 
1177 struct bcm_plat_data {
1178     const struct gpio_chip *gpio_chip;
1179     const struct pinctrl_desc *pctl_desc;
1180     const struct pinctrl_gpio_range *gpio_range;
1181 };
1182 
1183 static const struct bcm_plat_data bcm2835_plat_data = {
1184     .gpio_chip = &bcm2835_gpio_chip,
1185     .pctl_desc = &bcm2835_pinctrl_desc,
1186     .gpio_range = &bcm2835_pinctrl_gpio_range,
1187 };
1188 
1189 static const struct bcm_plat_data bcm2711_plat_data = {
1190     .gpio_chip = &bcm2711_gpio_chip,
1191     .pctl_desc = &bcm2711_pinctrl_desc,
1192     .gpio_range = &bcm2711_pinctrl_gpio_range,
1193 };
1194 
1195 static const struct of_device_id bcm2835_pinctrl_match[] = {
1196     {
1197         .compatible = "brcm,bcm2835-gpio",
1198         .data = &bcm2835_plat_data,
1199     },
1200     {
1201         .compatible = "brcm,bcm2711-gpio",
1202         .data = &bcm2711_plat_data,
1203     },
1204     {
1205         .compatible = "brcm,bcm7211-gpio",
1206         .data = &bcm2711_plat_data,
1207     },
1208     {}
1209 };
1210 
1211 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1212 {
1213     struct device *dev = &pdev->dev;
1214     struct device_node *np = dev->of_node;
1215     const struct bcm_plat_data *pdata;
1216     struct bcm2835_pinctrl *pc;
1217     struct gpio_irq_chip *girq;
1218     struct resource iomem;
1219     int err, i;
1220     const struct of_device_id *match;
1221     int is_7211 = 0;
1222 
1223     BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1224     BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1225 
1226     pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1227     if (!pc)
1228         return -ENOMEM;
1229 
1230     platform_set_drvdata(pdev, pc);
1231     pc->dev = dev;
1232 
1233     err = of_address_to_resource(np, 0, &iomem);
1234     if (err) {
1235         dev_err(dev, "could not get IO memory\n");
1236         return err;
1237     }
1238 
1239     pc->base = devm_ioremap_resource(dev, &iomem);
1240     if (IS_ERR(pc->base))
1241         return PTR_ERR(pc->base);
1242 
1243     match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1244     if (!match)
1245         return -EINVAL;
1246 
1247     pdata = match->data;
1248     is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1249 
1250     pc->gpio_chip = *pdata->gpio_chip;
1251     pc->gpio_chip.parent = dev;
1252 
1253     for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1254         unsigned long events;
1255         unsigned offset;
1256 
1257         /* clear event detection flags */
1258         bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1259         bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1260         bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1261         bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1262         bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1263         bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1264 
1265         /* clear all the events */
1266         events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1267         for_each_set_bit(offset, &events, 32)
1268             bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1269 
1270         raw_spin_lock_init(&pc->irq_lock[i]);
1271     }
1272 
1273     pc->pctl_desc = *pdata->pctl_desc;
1274     pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1275     if (IS_ERR(pc->pctl_dev)) {
1276         gpiochip_remove(&pc->gpio_chip);
1277         return PTR_ERR(pc->pctl_dev);
1278     }
1279 
1280     pc->gpio_range = *pdata->gpio_range;
1281     pc->gpio_range.base = pc->gpio_chip.base;
1282     pc->gpio_range.gc = &pc->gpio_chip;
1283     pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1284 
1285     girq = &pc->gpio_chip.irq;
1286     gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip);
1287     girq->parent_handler = bcm2835_gpio_irq_handler;
1288     girq->num_parents = BCM2835_NUM_IRQS;
1289     girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1290                      sizeof(*girq->parents),
1291                      GFP_KERNEL);
1292     if (!girq->parents) {
1293         err = -ENOMEM;
1294         goto out_remove;
1295     }
1296 
1297     if (is_7211) {
1298         pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1299                         sizeof(*pc->wake_irq),
1300                         GFP_KERNEL);
1301         if (!pc->wake_irq) {
1302             err = -ENOMEM;
1303             goto out_remove;
1304         }
1305     }
1306 
1307     /*
1308      * Use the same handler for all groups: this is necessary
1309      * since we use one gpiochip to cover all lines - the
1310      * irq handler then needs to figure out which group and
1311      * bank that was firing the IRQ and look up the per-group
1312      * and bank data.
1313      */
1314     for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1315         int len;
1316         char *name;
1317 
1318         girq->parents[i] = irq_of_parse_and_map(np, i);
1319         if (!is_7211) {
1320             if (!girq->parents[i]) {
1321                 girq->num_parents = i;
1322                 break;
1323             }
1324             continue;
1325         }
1326         /* Skip over the all banks interrupts */
1327         pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1328                                BCM2835_NUM_IRQS + 1);
1329 
1330         len = strlen(dev_name(pc->dev)) + 16;
1331         name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1332         if (!name) {
1333             err = -ENOMEM;
1334             goto out_remove;
1335         }
1336 
1337         snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1338 
1339         /* These are optional interrupts */
1340         err = devm_request_irq(dev, pc->wake_irq[i],
1341                        bcm2835_gpio_wake_irq_handler,
1342                        IRQF_SHARED, name, pc);
1343         if (err)
1344             dev_warn(dev, "unable to request wake IRQ %d\n",
1345                  pc->wake_irq[i]);
1346     }
1347 
1348     girq->default_type = IRQ_TYPE_NONE;
1349     girq->handler = handle_level_irq;
1350 
1351     err = gpiochip_add_data(&pc->gpio_chip, pc);
1352     if (err) {
1353         dev_err(dev, "could not add GPIO chip\n");
1354         goto out_remove;
1355     }
1356 
1357     return 0;
1358 
1359 out_remove:
1360     pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1361     return err;
1362 }
1363 
1364 static struct platform_driver bcm2835_pinctrl_driver = {
1365     .probe = bcm2835_pinctrl_probe,
1366     .driver = {
1367         .name = MODULE_NAME,
1368         .of_match_table = bcm2835_pinctrl_match,
1369         .suppress_bind_attrs = true,
1370     },
1371 };
1372 module_platform_driver(bcm2835_pinctrl_driver);
1373 
1374 MODULE_AUTHOR("Chris Boot");
1375 MODULE_AUTHOR("Simon Arlott");
1376 MODULE_AUTHOR("Stephen Warren");
1377 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver");
1378 MODULE_LICENSE("GPL");
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