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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2013-2017 Broadcom
0003 
0004 #include <linux/err.h>
0005 #include <linux/io.h>
0006 #include <linux/init.h>
0007 #include <linux/of.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/pinctrl/pinctrl.h>
0010 #include <linux/pinctrl/pinmux.h>
0011 #include <linux/pinctrl/pinconf.h>
0012 #include <linux/pinctrl/pinconf-generic.h>
0013 #include <linux/regmap.h>
0014 #include <linux/slab.h>
0015 #include "../core.h"
0016 #include "../pinctrl-utils.h"
0017 
0018 /* BCM281XX Pin Control Registers Definitions */
0019 
0020 /* Function Select bits are the same for all pin control registers */
0021 #define BCM281XX_PIN_REG_F_SEL_MASK     0x0700
0022 #define BCM281XX_PIN_REG_F_SEL_SHIFT        8
0023 
0024 /* Standard pin register */
0025 #define BCM281XX_STD_PIN_REG_DRV_STR_MASK   0x0007
0026 #define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT  0
0027 #define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008
0028 #define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT    3
0029 #define BCM281XX_STD_PIN_REG_SLEW_MASK      0x0010
0030 #define BCM281XX_STD_PIN_REG_SLEW_SHIFT     4
0031 #define BCM281XX_STD_PIN_REG_PULL_UP_MASK   0x0020
0032 #define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT  5
0033 #define BCM281XX_STD_PIN_REG_PULL_DN_MASK   0x0040
0034 #define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT  6
0035 #define BCM281XX_STD_PIN_REG_HYST_MASK      0x0080
0036 #define BCM281XX_STD_PIN_REG_HYST_SHIFT     7
0037 
0038 /* I2C pin register */
0039 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004
0040 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT    2
0041 #define BCM281XX_I2C_PIN_REG_SLEW_MASK      0x0008
0042 #define BCM281XX_I2C_PIN_REG_SLEW_SHIFT     3
0043 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK   0x0070
0044 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT  4
0045 
0046 /* HDMI pin register */
0047 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK    0x0008
0048 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT   3
0049 #define BCM281XX_HDMI_PIN_REG_MODE_MASK     0x0010
0050 #define BCM281XX_HDMI_PIN_REG_MODE_SHIFT    4
0051 
0052 /*
0053  * bcm281xx_pin_type - types of pin register
0054  */
0055 enum bcm281xx_pin_type {
0056     BCM281XX_PIN_TYPE_UNKNOWN = 0,
0057     BCM281XX_PIN_TYPE_STD,
0058     BCM281XX_PIN_TYPE_I2C,
0059     BCM281XX_PIN_TYPE_HDMI,
0060 };
0061 
0062 static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD;
0063 static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;
0064 static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;
0065 
0066 /*
0067  * bcm281xx_pin_function- define pin function
0068  */
0069 struct bcm281xx_pin_function {
0070     const char *name;
0071     const char * const *groups;
0072     const unsigned ngroups;
0073 };
0074 
0075 /*
0076  * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
0077  * @reg_base - base of pinctrl registers
0078  */
0079 struct bcm281xx_pinctrl_data {
0080     void __iomem *reg_base;
0081 
0082     /* List of all pins */
0083     const struct pinctrl_pin_desc *pins;
0084     const unsigned npins;
0085 
0086     const struct bcm281xx_pin_function *functions;
0087     const unsigned nfunctions;
0088 
0089     struct regmap *regmap;
0090 };
0091 
0092 /*
0093  * Pin number definition.  The order here must be the same as defined in the
0094  * PADCTRLREG block in the RDB.
0095  */
0096 #define BCM281XX_PIN_ADCSYNC        0
0097 #define BCM281XX_PIN_BAT_RM     1
0098 #define BCM281XX_PIN_BSC1_SCL       2
0099 #define BCM281XX_PIN_BSC1_SDA       3
0100 #define BCM281XX_PIN_BSC2_SCL       4
0101 #define BCM281XX_PIN_BSC2_SDA       5
0102 #define BCM281XX_PIN_CLASSGPWR      6
0103 #define BCM281XX_PIN_CLK_CX8        7
0104 #define BCM281XX_PIN_CLKOUT_0       8
0105 #define BCM281XX_PIN_CLKOUT_1       9
0106 #define BCM281XX_PIN_CLKOUT_2       10
0107 #define BCM281XX_PIN_CLKOUT_3       11
0108 #define BCM281XX_PIN_CLKREQ_IN_0    12
0109 #define BCM281XX_PIN_CLKREQ_IN_1    13
0110 #define BCM281XX_PIN_CWS_SYS_REQ1   14
0111 #define BCM281XX_PIN_CWS_SYS_REQ2   15
0112 #define BCM281XX_PIN_CWS_SYS_REQ3   16
0113 #define BCM281XX_PIN_DIGMIC1_CLK    17
0114 #define BCM281XX_PIN_DIGMIC1_DQ     18
0115 #define BCM281XX_PIN_DIGMIC2_CLK    19
0116 #define BCM281XX_PIN_DIGMIC2_DQ     20
0117 #define BCM281XX_PIN_GPEN13     21
0118 #define BCM281XX_PIN_GPEN14     22
0119 #define BCM281XX_PIN_GPEN15     23
0120 #define BCM281XX_PIN_GPIO00     24
0121 #define BCM281XX_PIN_GPIO01     25
0122 #define BCM281XX_PIN_GPIO02     26
0123 #define BCM281XX_PIN_GPIO03     27
0124 #define BCM281XX_PIN_GPIO04     28
0125 #define BCM281XX_PIN_GPIO05     29
0126 #define BCM281XX_PIN_GPIO06     30
0127 #define BCM281XX_PIN_GPIO07     31
0128 #define BCM281XX_PIN_GPIO08     32
0129 #define BCM281XX_PIN_GPIO09     33
0130 #define BCM281XX_PIN_GPIO10     34
0131 #define BCM281XX_PIN_GPIO11     35
0132 #define BCM281XX_PIN_GPIO12     36
0133 #define BCM281XX_PIN_GPIO13     37
0134 #define BCM281XX_PIN_GPIO14     38
0135 #define BCM281XX_PIN_GPS_PABLANK    39
0136 #define BCM281XX_PIN_GPS_TMARK      40
0137 #define BCM281XX_PIN_HDMI_SCL       41
0138 #define BCM281XX_PIN_HDMI_SDA       42
0139 #define BCM281XX_PIN_IC_DM      43
0140 #define BCM281XX_PIN_IC_DP      44
0141 #define BCM281XX_PIN_KP_COL_IP_0    45
0142 #define BCM281XX_PIN_KP_COL_IP_1    46
0143 #define BCM281XX_PIN_KP_COL_IP_2    47
0144 #define BCM281XX_PIN_KP_COL_IP_3    48
0145 #define BCM281XX_PIN_KP_ROW_OP_0    49
0146 #define BCM281XX_PIN_KP_ROW_OP_1    50
0147 #define BCM281XX_PIN_KP_ROW_OP_2    51
0148 #define BCM281XX_PIN_KP_ROW_OP_3    52
0149 #define BCM281XX_PIN_LCD_B_0        53
0150 #define BCM281XX_PIN_LCD_B_1        54
0151 #define BCM281XX_PIN_LCD_B_2        55
0152 #define BCM281XX_PIN_LCD_B_3        56
0153 #define BCM281XX_PIN_LCD_B_4        57
0154 #define BCM281XX_PIN_LCD_B_5        58
0155 #define BCM281XX_PIN_LCD_B_6        59
0156 #define BCM281XX_PIN_LCD_B_7        60
0157 #define BCM281XX_PIN_LCD_G_0        61
0158 #define BCM281XX_PIN_LCD_G_1        62
0159 #define BCM281XX_PIN_LCD_G_2        63
0160 #define BCM281XX_PIN_LCD_G_3        64
0161 #define BCM281XX_PIN_LCD_G_4        65
0162 #define BCM281XX_PIN_LCD_G_5        66
0163 #define BCM281XX_PIN_LCD_G_6        67
0164 #define BCM281XX_PIN_LCD_G_7        68
0165 #define BCM281XX_PIN_LCD_HSYNC      69
0166 #define BCM281XX_PIN_LCD_OE     70
0167 #define BCM281XX_PIN_LCD_PCLK       71
0168 #define BCM281XX_PIN_LCD_R_0        72
0169 #define BCM281XX_PIN_LCD_R_1        73
0170 #define BCM281XX_PIN_LCD_R_2        74
0171 #define BCM281XX_PIN_LCD_R_3        75
0172 #define BCM281XX_PIN_LCD_R_4        76
0173 #define BCM281XX_PIN_LCD_R_5        77
0174 #define BCM281XX_PIN_LCD_R_6        78
0175 #define BCM281XX_PIN_LCD_R_7        79
0176 #define BCM281XX_PIN_LCD_VSYNC      80
0177 #define BCM281XX_PIN_MDMGPIO0       81
0178 #define BCM281XX_PIN_MDMGPIO1       82
0179 #define BCM281XX_PIN_MDMGPIO2       83
0180 #define BCM281XX_PIN_MDMGPIO3       84
0181 #define BCM281XX_PIN_MDMGPIO4       85
0182 #define BCM281XX_PIN_MDMGPIO5       86
0183 #define BCM281XX_PIN_MDMGPIO6       87
0184 #define BCM281XX_PIN_MDMGPIO7       88
0185 #define BCM281XX_PIN_MDMGPIO8       89
0186 #define BCM281XX_PIN_MPHI_DATA_0    90
0187 #define BCM281XX_PIN_MPHI_DATA_1    91
0188 #define BCM281XX_PIN_MPHI_DATA_2    92
0189 #define BCM281XX_PIN_MPHI_DATA_3    93
0190 #define BCM281XX_PIN_MPHI_DATA_4    94
0191 #define BCM281XX_PIN_MPHI_DATA_5    95
0192 #define BCM281XX_PIN_MPHI_DATA_6    96
0193 #define BCM281XX_PIN_MPHI_DATA_7    97
0194 #define BCM281XX_PIN_MPHI_DATA_8    98
0195 #define BCM281XX_PIN_MPHI_DATA_9    99
0196 #define BCM281XX_PIN_MPHI_DATA_10   100
0197 #define BCM281XX_PIN_MPHI_DATA_11   101
0198 #define BCM281XX_PIN_MPHI_DATA_12   102
0199 #define BCM281XX_PIN_MPHI_DATA_13   103
0200 #define BCM281XX_PIN_MPHI_DATA_14   104
0201 #define BCM281XX_PIN_MPHI_DATA_15   105
0202 #define BCM281XX_PIN_MPHI_HA0       106
0203 #define BCM281XX_PIN_MPHI_HAT0      107
0204 #define BCM281XX_PIN_MPHI_HAT1      108
0205 #define BCM281XX_PIN_MPHI_HCE0_N    109
0206 #define BCM281XX_PIN_MPHI_HCE1_N    110
0207 #define BCM281XX_PIN_MPHI_HRD_N     111
0208 #define BCM281XX_PIN_MPHI_HWR_N     112
0209 #define BCM281XX_PIN_MPHI_RUN0      113
0210 #define BCM281XX_PIN_MPHI_RUN1      114
0211 #define BCM281XX_PIN_MTX_SCAN_CLK   115
0212 #define BCM281XX_PIN_MTX_SCAN_DATA  116
0213 #define BCM281XX_PIN_NAND_AD_0      117
0214 #define BCM281XX_PIN_NAND_AD_1      118
0215 #define BCM281XX_PIN_NAND_AD_2      119
0216 #define BCM281XX_PIN_NAND_AD_3      120
0217 #define BCM281XX_PIN_NAND_AD_4      121
0218 #define BCM281XX_PIN_NAND_AD_5      122
0219 #define BCM281XX_PIN_NAND_AD_6      123
0220 #define BCM281XX_PIN_NAND_AD_7      124
0221 #define BCM281XX_PIN_NAND_ALE       125
0222 #define BCM281XX_PIN_NAND_CEN_0     126
0223 #define BCM281XX_PIN_NAND_CEN_1     127
0224 #define BCM281XX_PIN_NAND_CLE       128
0225 #define BCM281XX_PIN_NAND_OEN       129
0226 #define BCM281XX_PIN_NAND_RDY_0     130
0227 #define BCM281XX_PIN_NAND_RDY_1     131
0228 #define BCM281XX_PIN_NAND_WEN       132
0229 #define BCM281XX_PIN_NAND_WP        133
0230 #define BCM281XX_PIN_PC1        134
0231 #define BCM281XX_PIN_PC2        135
0232 #define BCM281XX_PIN_PMU_INT        136
0233 #define BCM281XX_PIN_PMU_SCL        137
0234 #define BCM281XX_PIN_PMU_SDA        138
0235 #define BCM281XX_PIN_RFST2G_MTSLOTEN3G  139
0236 #define BCM281XX_PIN_RGMII_0_RX_CTL 140
0237 #define BCM281XX_PIN_RGMII_0_RXC    141
0238 #define BCM281XX_PIN_RGMII_0_RXD_0  142
0239 #define BCM281XX_PIN_RGMII_0_RXD_1  143
0240 #define BCM281XX_PIN_RGMII_0_RXD_2  144
0241 #define BCM281XX_PIN_RGMII_0_RXD_3  145
0242 #define BCM281XX_PIN_RGMII_0_TX_CTL 146
0243 #define BCM281XX_PIN_RGMII_0_TXC    147
0244 #define BCM281XX_PIN_RGMII_0_TXD_0  148
0245 #define BCM281XX_PIN_RGMII_0_TXD_1  149
0246 #define BCM281XX_PIN_RGMII_0_TXD_2  150
0247 #define BCM281XX_PIN_RGMII_0_TXD_3  151
0248 #define BCM281XX_PIN_RGMII_1_RX_CTL 152
0249 #define BCM281XX_PIN_RGMII_1_RXC    153
0250 #define BCM281XX_PIN_RGMII_1_RXD_0  154
0251 #define BCM281XX_PIN_RGMII_1_RXD_1  155
0252 #define BCM281XX_PIN_RGMII_1_RXD_2  156
0253 #define BCM281XX_PIN_RGMII_1_RXD_3  157
0254 #define BCM281XX_PIN_RGMII_1_TX_CTL 158
0255 #define BCM281XX_PIN_RGMII_1_TXC    159
0256 #define BCM281XX_PIN_RGMII_1_TXD_0  160
0257 #define BCM281XX_PIN_RGMII_1_TXD_1  161
0258 #define BCM281XX_PIN_RGMII_1_TXD_2  162
0259 #define BCM281XX_PIN_RGMII_1_TXD_3  163
0260 #define BCM281XX_PIN_RGMII_GPIO_0   164
0261 #define BCM281XX_PIN_RGMII_GPIO_1   165
0262 #define BCM281XX_PIN_RGMII_GPIO_2   166
0263 #define BCM281XX_PIN_RGMII_GPIO_3   167
0264 #define BCM281XX_PIN_RTXDATA2G_TXDATA3G1    168
0265 #define BCM281XX_PIN_RTXEN2G_TXDATA3G2  169
0266 #define BCM281XX_PIN_RXDATA3G0      170
0267 #define BCM281XX_PIN_RXDATA3G1      171
0268 #define BCM281XX_PIN_RXDATA3G2      172
0269 #define BCM281XX_PIN_SDIO1_CLK      173
0270 #define BCM281XX_PIN_SDIO1_CMD      174
0271 #define BCM281XX_PIN_SDIO1_DATA_0   175
0272 #define BCM281XX_PIN_SDIO1_DATA_1   176
0273 #define BCM281XX_PIN_SDIO1_DATA_2   177
0274 #define BCM281XX_PIN_SDIO1_DATA_3   178
0275 #define BCM281XX_PIN_SDIO4_CLK      179
0276 #define BCM281XX_PIN_SDIO4_CMD      180
0277 #define BCM281XX_PIN_SDIO4_DATA_0   181
0278 #define BCM281XX_PIN_SDIO4_DATA_1   182
0279 #define BCM281XX_PIN_SDIO4_DATA_2   183
0280 #define BCM281XX_PIN_SDIO4_DATA_3   184
0281 #define BCM281XX_PIN_SIM_CLK        185
0282 #define BCM281XX_PIN_SIM_DATA       186
0283 #define BCM281XX_PIN_SIM_DET        187
0284 #define BCM281XX_PIN_SIM_RESETN     188
0285 #define BCM281XX_PIN_SIM2_CLK       189
0286 #define BCM281XX_PIN_SIM2_DATA      190
0287 #define BCM281XX_PIN_SIM2_DET       191
0288 #define BCM281XX_PIN_SIM2_RESETN    192
0289 #define BCM281XX_PIN_SRI_C      193
0290 #define BCM281XX_PIN_SRI_D      194
0291 #define BCM281XX_PIN_SRI_E      195
0292 #define BCM281XX_PIN_SSP_EXTCLK     196
0293 #define BCM281XX_PIN_SSP0_CLK       197
0294 #define BCM281XX_PIN_SSP0_FS        198
0295 #define BCM281XX_PIN_SSP0_RXD       199
0296 #define BCM281XX_PIN_SSP0_TXD       200
0297 #define BCM281XX_PIN_SSP2_CLK       201
0298 #define BCM281XX_PIN_SSP2_FS_0      202
0299 #define BCM281XX_PIN_SSP2_FS_1      203
0300 #define BCM281XX_PIN_SSP2_FS_2      204
0301 #define BCM281XX_PIN_SSP2_FS_3      205
0302 #define BCM281XX_PIN_SSP2_RXD_0     206
0303 #define BCM281XX_PIN_SSP2_RXD_1     207
0304 #define BCM281XX_PIN_SSP2_TXD_0     208
0305 #define BCM281XX_PIN_SSP2_TXD_1     209
0306 #define BCM281XX_PIN_SSP3_CLK       210
0307 #define BCM281XX_PIN_SSP3_FS        211
0308 #define BCM281XX_PIN_SSP3_RXD       212
0309 #define BCM281XX_PIN_SSP3_TXD       213
0310 #define BCM281XX_PIN_SSP4_CLK       214
0311 #define BCM281XX_PIN_SSP4_FS        215
0312 #define BCM281XX_PIN_SSP4_RXD       216
0313 #define BCM281XX_PIN_SSP4_TXD       217
0314 #define BCM281XX_PIN_SSP5_CLK       218
0315 #define BCM281XX_PIN_SSP5_FS        219
0316 #define BCM281XX_PIN_SSP5_RXD       220
0317 #define BCM281XX_PIN_SSP5_TXD       221
0318 #define BCM281XX_PIN_SSP6_CLK       222
0319 #define BCM281XX_PIN_SSP6_FS        223
0320 #define BCM281XX_PIN_SSP6_RXD       224
0321 #define BCM281XX_PIN_SSP6_TXD       225
0322 #define BCM281XX_PIN_STAT_1     226
0323 #define BCM281XX_PIN_STAT_2     227
0324 #define BCM281XX_PIN_SYSCLKEN       228
0325 #define BCM281XX_PIN_TRACECLK       229
0326 #define BCM281XX_PIN_TRACEDT00      230
0327 #define BCM281XX_PIN_TRACEDT01      231
0328 #define BCM281XX_PIN_TRACEDT02      232
0329 #define BCM281XX_PIN_TRACEDT03      233
0330 #define BCM281XX_PIN_TRACEDT04      234
0331 #define BCM281XX_PIN_TRACEDT05      235
0332 #define BCM281XX_PIN_TRACEDT06      236
0333 #define BCM281XX_PIN_TRACEDT07      237
0334 #define BCM281XX_PIN_TRACEDT08      238
0335 #define BCM281XX_PIN_TRACEDT09      239
0336 #define BCM281XX_PIN_TRACEDT10      240
0337 #define BCM281XX_PIN_TRACEDT11      241
0338 #define BCM281XX_PIN_TRACEDT12      242
0339 #define BCM281XX_PIN_TRACEDT13      243
0340 #define BCM281XX_PIN_TRACEDT14      244
0341 #define BCM281XX_PIN_TRACEDT15      245
0342 #define BCM281XX_PIN_TXDATA3G0      246
0343 #define BCM281XX_PIN_TXPWRIND       247
0344 #define BCM281XX_PIN_UARTB1_UCTS    248
0345 #define BCM281XX_PIN_UARTB1_URTS    249
0346 #define BCM281XX_PIN_UARTB1_URXD    250
0347 #define BCM281XX_PIN_UARTB1_UTXD    251
0348 #define BCM281XX_PIN_UARTB2_URXD    252
0349 #define BCM281XX_PIN_UARTB2_UTXD    253
0350 #define BCM281XX_PIN_UARTB3_UCTS    254
0351 #define BCM281XX_PIN_UARTB3_URTS    255
0352 #define BCM281XX_PIN_UARTB3_URXD    256
0353 #define BCM281XX_PIN_UARTB3_UTXD    257
0354 #define BCM281XX_PIN_UARTB4_UCTS    258
0355 #define BCM281XX_PIN_UARTB4_URTS    259
0356 #define BCM281XX_PIN_UARTB4_URXD    260
0357 #define BCM281XX_PIN_UARTB4_UTXD    261
0358 #define BCM281XX_PIN_VC_CAM1_SCL    262
0359 #define BCM281XX_PIN_VC_CAM1_SDA    263
0360 #define BCM281XX_PIN_VC_CAM2_SCL    264
0361 #define BCM281XX_PIN_VC_CAM2_SDA    265
0362 #define BCM281XX_PIN_VC_CAM3_SCL    266
0363 #define BCM281XX_PIN_VC_CAM3_SDA    267
0364 
0365 #define BCM281XX_PIN_DESC(a, b, c) \
0366     { .number = a, .name = b, .drv_data = &c##_pin }
0367 
0368 /*
0369  * Pin description definition.  The order here must be the same as defined in
0370  * the PADCTRLREG block in the RDB, since the pin number is used as an index
0371  * into this array.
0372  */
0373 static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = {
0374     BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std),
0375     BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std),
0376     BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c),
0377     BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c),
0378     BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c),
0379     BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c),
0380     BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std),
0381     BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std),
0382     BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std),
0383     BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std),
0384     BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std),
0385     BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std),
0386     BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
0387     BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
0388     BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
0389     BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
0390     BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
0391     BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std),
0392     BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std),
0393     BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std),
0394     BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std),
0395     BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std),
0396     BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std),
0397     BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std),
0398     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std),
0399     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std),
0400     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std),
0401     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std),
0402     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std),
0403     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std),
0404     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std),
0405     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std),
0406     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std),
0407     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std),
0408     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std),
0409     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std),
0410     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std),
0411     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std),
0412     BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std),
0413     BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std),
0414     BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std),
0415     BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi),
0416     BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi),
0417     BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std),
0418     BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std),
0419     BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
0420     BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
0421     BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
0422     BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
0423     BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
0424     BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
0425     BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
0426     BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
0427     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std),
0428     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std),
0429     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std),
0430     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std),
0431     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std),
0432     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std),
0433     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std),
0434     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std),
0435     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std),
0436     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std),
0437     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std),
0438     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std),
0439     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std),
0440     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std),
0441     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std),
0442     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std),
0443     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std),
0444     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std),
0445     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std),
0446     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std),
0447     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std),
0448     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std),
0449     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std),
0450     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std),
0451     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std),
0452     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std),
0453     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std),
0454     BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std),
0455     BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std),
0456     BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std),
0457     BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std),
0458     BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std),
0459     BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std),
0460     BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std),
0461     BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std),
0462     BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std),
0463     BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std),
0464     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std),
0465     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std),
0466     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std),
0467     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std),
0468     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std),
0469     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std),
0470     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std),
0471     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std),
0472     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std),
0473     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std),
0474     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std),
0475     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std),
0476     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std),
0477     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std),
0478     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std),
0479     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std),
0480     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std),
0481     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std),
0482     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std),
0483     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
0484     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
0485     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
0486     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
0487     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std),
0488     BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std),
0489     BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
0490     BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
0491     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std),
0492     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std),
0493     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std),
0494     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std),
0495     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std),
0496     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std),
0497     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std),
0498     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std),
0499     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std),
0500     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std),
0501     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std),
0502     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std),
0503     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std),
0504     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std),
0505     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std),
0506     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std),
0507     BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std),
0508     BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std),
0509     BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std),
0510     BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std),
0511     BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c),
0512     BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c),
0513     BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g",
0514         std),
0515     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
0516     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
0517     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
0518     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
0519     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
0520     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
0521     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
0522     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
0523     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
0524     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
0525     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
0526     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
0527     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
0528     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
0529     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
0530     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
0531     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
0532     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
0533     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
0534     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
0535     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
0536     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
0537     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
0538     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
0539     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
0540     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
0541     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
0542     BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
0543     BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1,
0544         "rtxdata2g_txdata3g1", std),
0545     BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2",
0546         std),
0547     BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std),
0548     BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std),
0549     BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std),
0550     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std),
0551     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std),
0552     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
0553     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
0554     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
0555     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
0556     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std),
0557     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std),
0558     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
0559     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
0560     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
0561     BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
0562     BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std),
0563     BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std),
0564     BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std),
0565     BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std),
0566     BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std),
0567     BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std),
0568     BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std),
0569     BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std),
0570     BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std),
0571     BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std),
0572     BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std),
0573     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std),
0574     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std),
0575     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std),
0576     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std),
0577     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std),
0578     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std),
0579     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std),
0580     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std),
0581     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std),
0582     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std),
0583     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
0584     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
0585     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
0586     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
0587     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std),
0588     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std),
0589     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std),
0590     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std),
0591     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std),
0592     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std),
0593     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std),
0594     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std),
0595     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std),
0596     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std),
0597     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std),
0598     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std),
0599     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std),
0600     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std),
0601     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std),
0602     BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std),
0603     BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std),
0604     BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std),
0605     BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std),
0606     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std),
0607     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std),
0608     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std),
0609     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std),
0610     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std),
0611     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std),
0612     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std),
0613     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std),
0614     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std),
0615     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std),
0616     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std),
0617     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std),
0618     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std),
0619     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std),
0620     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std),
0621     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std),
0622     BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std),
0623     BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std),
0624     BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std),
0625     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std),
0626     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std),
0627     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std),
0628     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std),
0629     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std),
0630     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std),
0631     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std),
0632     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std),
0633     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std),
0634     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std),
0635     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std),
0636     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std),
0637     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std),
0638     BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std),
0639     BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
0640     BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
0641     BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
0642     BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
0643     BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
0644     BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
0645 };
0646 
0647 static const char * const bcm281xx_alt_groups[] = {
0648     "adcsync",
0649     "bat_rm",
0650     "bsc1_scl",
0651     "bsc1_sda",
0652     "bsc2_scl",
0653     "bsc2_sda",
0654     "classgpwr",
0655     "clk_cx8",
0656     "clkout_0",
0657     "clkout_1",
0658     "clkout_2",
0659     "clkout_3",
0660     "clkreq_in_0",
0661     "clkreq_in_1",
0662     "cws_sys_req1",
0663     "cws_sys_req2",
0664     "cws_sys_req3",
0665     "digmic1_clk",
0666     "digmic1_dq",
0667     "digmic2_clk",
0668     "digmic2_dq",
0669     "gpen13",
0670     "gpen14",
0671     "gpen15",
0672     "gpio00",
0673     "gpio01",
0674     "gpio02",
0675     "gpio03",
0676     "gpio04",
0677     "gpio05",
0678     "gpio06",
0679     "gpio07",
0680     "gpio08",
0681     "gpio09",
0682     "gpio10",
0683     "gpio11",
0684     "gpio12",
0685     "gpio13",
0686     "gpio14",
0687     "gps_pablank",
0688     "gps_tmark",
0689     "hdmi_scl",
0690     "hdmi_sda",
0691     "ic_dm",
0692     "ic_dp",
0693     "kp_col_ip_0",
0694     "kp_col_ip_1",
0695     "kp_col_ip_2",
0696     "kp_col_ip_3",
0697     "kp_row_op_0",
0698     "kp_row_op_1",
0699     "kp_row_op_2",
0700     "kp_row_op_3",
0701     "lcd_b_0",
0702     "lcd_b_1",
0703     "lcd_b_2",
0704     "lcd_b_3",
0705     "lcd_b_4",
0706     "lcd_b_5",
0707     "lcd_b_6",
0708     "lcd_b_7",
0709     "lcd_g_0",
0710     "lcd_g_1",
0711     "lcd_g_2",
0712     "lcd_g_3",
0713     "lcd_g_4",
0714     "lcd_g_5",
0715     "lcd_g_6",
0716     "lcd_g_7",
0717     "lcd_hsync",
0718     "lcd_oe",
0719     "lcd_pclk",
0720     "lcd_r_0",
0721     "lcd_r_1",
0722     "lcd_r_2",
0723     "lcd_r_3",
0724     "lcd_r_4",
0725     "lcd_r_5",
0726     "lcd_r_6",
0727     "lcd_r_7",
0728     "lcd_vsync",
0729     "mdmgpio0",
0730     "mdmgpio1",
0731     "mdmgpio2",
0732     "mdmgpio3",
0733     "mdmgpio4",
0734     "mdmgpio5",
0735     "mdmgpio6",
0736     "mdmgpio7",
0737     "mdmgpio8",
0738     "mphi_data_0",
0739     "mphi_data_1",
0740     "mphi_data_2",
0741     "mphi_data_3",
0742     "mphi_data_4",
0743     "mphi_data_5",
0744     "mphi_data_6",
0745     "mphi_data_7",
0746     "mphi_data_8",
0747     "mphi_data_9",
0748     "mphi_data_10",
0749     "mphi_data_11",
0750     "mphi_data_12",
0751     "mphi_data_13",
0752     "mphi_data_14",
0753     "mphi_data_15",
0754     "mphi_ha0",
0755     "mphi_hat0",
0756     "mphi_hat1",
0757     "mphi_hce0_n",
0758     "mphi_hce1_n",
0759     "mphi_hrd_n",
0760     "mphi_hwr_n",
0761     "mphi_run0",
0762     "mphi_run1",
0763     "mtx_scan_clk",
0764     "mtx_scan_data",
0765     "nand_ad_0",
0766     "nand_ad_1",
0767     "nand_ad_2",
0768     "nand_ad_3",
0769     "nand_ad_4",
0770     "nand_ad_5",
0771     "nand_ad_6",
0772     "nand_ad_7",
0773     "nand_ale",
0774     "nand_cen_0",
0775     "nand_cen_1",
0776     "nand_cle",
0777     "nand_oen",
0778     "nand_rdy_0",
0779     "nand_rdy_1",
0780     "nand_wen",
0781     "nand_wp",
0782     "pc1",
0783     "pc2",
0784     "pmu_int",
0785     "pmu_scl",
0786     "pmu_sda",
0787     "rfst2g_mtsloten3g",
0788     "rgmii_0_rx_ctl",
0789     "rgmii_0_rxc",
0790     "rgmii_0_rxd_0",
0791     "rgmii_0_rxd_1",
0792     "rgmii_0_rxd_2",
0793     "rgmii_0_rxd_3",
0794     "rgmii_0_tx_ctl",
0795     "rgmii_0_txc",
0796     "rgmii_0_txd_0",
0797     "rgmii_0_txd_1",
0798     "rgmii_0_txd_2",
0799     "rgmii_0_txd_3",
0800     "rgmii_1_rx_ctl",
0801     "rgmii_1_rxc",
0802     "rgmii_1_rxd_0",
0803     "rgmii_1_rxd_1",
0804     "rgmii_1_rxd_2",
0805     "rgmii_1_rxd_3",
0806     "rgmii_1_tx_ctl",
0807     "rgmii_1_txc",
0808     "rgmii_1_txd_0",
0809     "rgmii_1_txd_1",
0810     "rgmii_1_txd_2",
0811     "rgmii_1_txd_3",
0812     "rgmii_gpio_0",
0813     "rgmii_gpio_1",
0814     "rgmii_gpio_2",
0815     "rgmii_gpio_3",
0816     "rtxdata2g_txdata3g1",
0817     "rtxen2g_txdata3g2",
0818     "rxdata3g0",
0819     "rxdata3g1",
0820     "rxdata3g2",
0821     "sdio1_clk",
0822     "sdio1_cmd",
0823     "sdio1_data_0",
0824     "sdio1_data_1",
0825     "sdio1_data_2",
0826     "sdio1_data_3",
0827     "sdio4_clk",
0828     "sdio4_cmd",
0829     "sdio4_data_0",
0830     "sdio4_data_1",
0831     "sdio4_data_2",
0832     "sdio4_data_3",
0833     "sim_clk",
0834     "sim_data",
0835     "sim_det",
0836     "sim_resetn",
0837     "sim2_clk",
0838     "sim2_data",
0839     "sim2_det",
0840     "sim2_resetn",
0841     "sri_c",
0842     "sri_d",
0843     "sri_e",
0844     "ssp_extclk",
0845     "ssp0_clk",
0846     "ssp0_fs",
0847     "ssp0_rxd",
0848     "ssp0_txd",
0849     "ssp2_clk",
0850     "ssp2_fs_0",
0851     "ssp2_fs_1",
0852     "ssp2_fs_2",
0853     "ssp2_fs_3",
0854     "ssp2_rxd_0",
0855     "ssp2_rxd_1",
0856     "ssp2_txd_0",
0857     "ssp2_txd_1",
0858     "ssp3_clk",
0859     "ssp3_fs",
0860     "ssp3_rxd",
0861     "ssp3_txd",
0862     "ssp4_clk",
0863     "ssp4_fs",
0864     "ssp4_rxd",
0865     "ssp4_txd",
0866     "ssp5_clk",
0867     "ssp5_fs",
0868     "ssp5_rxd",
0869     "ssp5_txd",
0870     "ssp6_clk",
0871     "ssp6_fs",
0872     "ssp6_rxd",
0873     "ssp6_txd",
0874     "stat_1",
0875     "stat_2",
0876     "sysclken",
0877     "traceclk",
0878     "tracedt00",
0879     "tracedt01",
0880     "tracedt02",
0881     "tracedt03",
0882     "tracedt04",
0883     "tracedt05",
0884     "tracedt06",
0885     "tracedt07",
0886     "tracedt08",
0887     "tracedt09",
0888     "tracedt10",
0889     "tracedt11",
0890     "tracedt12",
0891     "tracedt13",
0892     "tracedt14",
0893     "tracedt15",
0894     "txdata3g0",
0895     "txpwrind",
0896     "uartb1_ucts",
0897     "uartb1_urts",
0898     "uartb1_urxd",
0899     "uartb1_utxd",
0900     "uartb2_urxd",
0901     "uartb2_utxd",
0902     "uartb3_ucts",
0903     "uartb3_urts",
0904     "uartb3_urxd",
0905     "uartb3_utxd",
0906     "uartb4_ucts",
0907     "uartb4_urts",
0908     "uartb4_urxd",
0909     "uartb4_utxd",
0910     "vc_cam1_scl",
0911     "vc_cam1_sda",
0912     "vc_cam2_scl",
0913     "vc_cam2_sda",
0914     "vc_cam3_scl",
0915     "vc_cam3_sda",
0916 };
0917 
0918 /* Every pin can implement all ALT1-ALT4 functions */
0919 #define BCM281XX_PIN_FUNCTION(fcn_name)         \
0920 {                           \
0921     .name = #fcn_name,              \
0922     .groups = bcm281xx_alt_groups,          \
0923     .ngroups = ARRAY_SIZE(bcm281xx_alt_groups), \
0924 }
0925 
0926 static const struct bcm281xx_pin_function bcm281xx_functions[] = {
0927     BCM281XX_PIN_FUNCTION(alt1),
0928     BCM281XX_PIN_FUNCTION(alt2),
0929     BCM281XX_PIN_FUNCTION(alt3),
0930     BCM281XX_PIN_FUNCTION(alt4),
0931 };
0932 
0933 static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = {
0934     .pins = bcm281xx_pinctrl_pins,
0935     .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins),
0936     .functions = bcm281xx_functions,
0937     .nfunctions = ARRAY_SIZE(bcm281xx_functions),
0938 };
0939 
0940 static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev,
0941                           unsigned pin)
0942 {
0943     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
0944 
0945     if (pin >= pdata->npins)
0946         return BCM281XX_PIN_TYPE_UNKNOWN;
0947 
0948     return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data);
0949 }
0950 
0951 #define BCM281XX_PIN_SHIFT(type, param) \
0952     (BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT)
0953 
0954 #define BCM281XX_PIN_MASK(type, param) \
0955     (BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK)
0956 
0957 /*
0958  * This helper function is used to build up the value and mask used to write to
0959  * a pin register, but does not actually write to the register.
0960  */
0961 static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,
0962                        u32 param_val, u32 param_shift,
0963                        u32 param_mask)
0964 {
0965     *reg_val &= ~param_mask;
0966     *reg_val |= (param_val << param_shift) & param_mask;
0967     *reg_mask |= param_mask;
0968 }
0969 
0970 static const struct regmap_config bcm281xx_pinctrl_regmap_config = {
0971     .reg_bits = 32,
0972     .reg_stride = 4,
0973     .val_bits = 32,
0974     .max_register = BCM281XX_PIN_VC_CAM3_SDA,
0975 };
0976 
0977 static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0978 {
0979     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
0980 
0981     return pdata->npins;
0982 }
0983 
0984 static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0985                            unsigned group)
0986 {
0987     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
0988 
0989     return pdata->pins[group].name;
0990 }
0991 
0992 static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0993                        unsigned group,
0994                        const unsigned **pins,
0995                        unsigned *num_pins)
0996 {
0997     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
0998 
0999     *pins = &pdata->pins[group].number;
1000     *num_pins = 1;
1001 
1002     return 0;
1003 }
1004 
1005 static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1006                       struct seq_file *s,
1007                       unsigned offset)
1008 {
1009     seq_printf(s, " %s", dev_name(pctldev->dev));
1010 }
1011 
1012 static const struct pinctrl_ops bcm281xx_pinctrl_ops = {
1013     .get_groups_count = bcm281xx_pinctrl_get_groups_count,
1014     .get_group_name = bcm281xx_pinctrl_get_group_name,
1015     .get_group_pins = bcm281xx_pinctrl_get_group_pins,
1016     .pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show,
1017     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1018     .dt_free_map = pinctrl_utils_free_map,
1019 };
1020 
1021 static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
1022 {
1023     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1024 
1025     return pdata->nfunctions;
1026 }
1027 
1028 static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
1029                          unsigned function)
1030 {
1031     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1032 
1033     return pdata->functions[function].name;
1034 }
1035 
1036 static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1037                        unsigned function,
1038                        const char * const **groups,
1039                        unsigned * const num_groups)
1040 {
1041     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1042 
1043     *groups = pdata->functions[function].groups;
1044     *num_groups = pdata->functions[function].ngroups;
1045 
1046     return 0;
1047 }
1048 
1049 static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
1050                    unsigned function,
1051                    unsigned group)
1052 {
1053     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1054     const struct bcm281xx_pin_function *f = &pdata->functions[function];
1055     u32 offset = 4 * pdata->pins[group].number;
1056     int rc = 0;
1057 
1058     dev_dbg(pctldev->dev,
1059         "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
1060         __func__, f->name, function, pdata->pins[group].name,
1061         pdata->pins[group].number, offset);
1062 
1063     rc = regmap_update_bits(pdata->regmap, offset,
1064         BCM281XX_PIN_REG_F_SEL_MASK,
1065         function << BCM281XX_PIN_REG_F_SEL_SHIFT);
1066     if (rc)
1067         dev_err(pctldev->dev,
1068             "Error updating register for pin %s (%d).\n",
1069             pdata->pins[group].name, pdata->pins[group].number);
1070 
1071     return rc;
1072 }
1073 
1074 static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
1075     .get_functions_count = bcm281xx_pinctrl_get_fcns_count,
1076     .get_function_name = bcm281xx_pinctrl_get_fcn_name,
1077     .get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
1078     .set_mux = bcm281xx_pinmux_set,
1079 };
1080 
1081 static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
1082                        unsigned pin,
1083                        unsigned long *config)
1084 {
1085     return -ENOTSUPP;
1086 }
1087 
1088 
1089 /* Goes through the configs and update register val/mask */
1090 static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev,
1091                    unsigned pin,
1092                    unsigned long *configs,
1093                    unsigned num_configs,
1094                    u32 *val,
1095                    u32 *mask)
1096 {
1097     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1098     int i;
1099     enum pin_config_param param;
1100     u32 arg;
1101 
1102     for (i = 0; i < num_configs; i++) {
1103         param = pinconf_to_config_param(configs[i]);
1104         arg = pinconf_to_config_argument(configs[i]);
1105 
1106         switch (param) {
1107         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1108             arg = (arg >= 1 ? 1 : 0);
1109             bcm281xx_pin_update(val, mask, arg,
1110                 BCM281XX_PIN_SHIFT(STD, HYST),
1111                 BCM281XX_PIN_MASK(STD, HYST));
1112             break;
1113         /*
1114          * The pin bias can only be one of pull-up, pull-down, or
1115          * disable.  The user does not need to specify a value for the
1116          * property, and the default value from pinconf-generic is
1117          * ignored.
1118          */
1119         case PIN_CONFIG_BIAS_DISABLE:
1120             bcm281xx_pin_update(val, mask, 0,
1121                 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1122                 BCM281XX_PIN_MASK(STD, PULL_UP));
1123             bcm281xx_pin_update(val, mask, 0,
1124                 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1125                 BCM281XX_PIN_MASK(STD, PULL_DN));
1126             break;
1127 
1128         case PIN_CONFIG_BIAS_PULL_UP:
1129             bcm281xx_pin_update(val, mask, 1,
1130                 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1131                 BCM281XX_PIN_MASK(STD, PULL_UP));
1132             bcm281xx_pin_update(val, mask, 0,
1133                 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1134                 BCM281XX_PIN_MASK(STD, PULL_DN));
1135             break;
1136 
1137         case PIN_CONFIG_BIAS_PULL_DOWN:
1138             bcm281xx_pin_update(val, mask, 0,
1139                 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1140                 BCM281XX_PIN_MASK(STD, PULL_UP));
1141             bcm281xx_pin_update(val, mask, 1,
1142                 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1143                 BCM281XX_PIN_MASK(STD, PULL_DN));
1144             break;
1145 
1146         case PIN_CONFIG_SLEW_RATE:
1147             arg = (arg >= 1 ? 1 : 0);
1148             bcm281xx_pin_update(val, mask, arg,
1149                 BCM281XX_PIN_SHIFT(STD, SLEW),
1150                 BCM281XX_PIN_MASK(STD, SLEW));
1151             break;
1152 
1153         case PIN_CONFIG_INPUT_ENABLE:
1154             /* inversed since register is for input _disable_ */
1155             arg = (arg >= 1 ? 0 : 1);
1156             bcm281xx_pin_update(val, mask, arg,
1157                 BCM281XX_PIN_SHIFT(STD, INPUT_DIS),
1158                 BCM281XX_PIN_MASK(STD, INPUT_DIS));
1159             break;
1160 
1161         case PIN_CONFIG_DRIVE_STRENGTH:
1162             /* Valid range is 2-16 mA, even numbers only */
1163             if ((arg < 2) || (arg > 16) || (arg % 2)) {
1164                 dev_err(pctldev->dev,
1165                     "Invalid Drive Strength value (%d) for "
1166                     "pin %s (%d). Valid values are "
1167                     "(2..16) mA, even numbers only.\n",
1168                     arg, pdata->pins[pin].name, pin);
1169                 return -EINVAL;
1170             }
1171             bcm281xx_pin_update(val, mask, (arg/2)-1,
1172                 BCM281XX_PIN_SHIFT(STD, DRV_STR),
1173                 BCM281XX_PIN_MASK(STD, DRV_STR));
1174             break;
1175 
1176         default:
1177             dev_err(pctldev->dev,
1178                 "Unrecognized pin config %d for pin %s (%d).\n",
1179                 param, pdata->pins[pin].name, pin);
1180             return -EINVAL;
1181 
1182         } /* switch config */
1183     } /* for each config */
1184 
1185     return 0;
1186 }
1187 
1188 /*
1189  * The pull-up strength for an I2C pin is represented by bits 4-6 in the
1190  * register with the following mapping:
1191  *   0b000: No pull-up
1192  *   0b001: 1200 Ohm
1193  *   0b010: 1800 Ohm
1194  *   0b011: 720 Ohm
1195  *   0b100: 2700 Ohm
1196  *   0b101: 831 Ohm
1197  *   0b110: 1080 Ohm
1198  *   0b111: 568 Ohm
1199  * This array maps pull-up strength in Ohms to register values (1+index).
1200  */
1201 static const u16 bcm281xx_pullup_map[] = {
1202     1200, 1800, 720, 2700, 831, 1080, 568
1203 };
1204 
1205 /* Goes through the configs and update register val/mask */
1206 static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev,
1207                    unsigned pin,
1208                    unsigned long *configs,
1209                    unsigned num_configs,
1210                    u32 *val,
1211                    u32 *mask)
1212 {
1213     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1214     int i, j;
1215     enum pin_config_param param;
1216     u32 arg;
1217 
1218     for (i = 0; i < num_configs; i++) {
1219         param = pinconf_to_config_param(configs[i]);
1220         arg = pinconf_to_config_argument(configs[i]);
1221 
1222         switch (param) {
1223         case PIN_CONFIG_BIAS_PULL_UP:
1224             for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++)
1225                 if (bcm281xx_pullup_map[j] == arg)
1226                     break;
1227 
1228             if (j == ARRAY_SIZE(bcm281xx_pullup_map)) {
1229                 dev_err(pctldev->dev,
1230                     "Invalid pull-up value (%d) for pin %s "
1231                     "(%d). Valid values are 568, 720, 831, "
1232                     "1080, 1200, 1800, 2700 Ohms.\n",
1233                     arg, pdata->pins[pin].name, pin);
1234                 return -EINVAL;
1235             }
1236 
1237             bcm281xx_pin_update(val, mask, j+1,
1238                 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1239                 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1240             break;
1241 
1242         case PIN_CONFIG_BIAS_DISABLE:
1243             bcm281xx_pin_update(val, mask, 0,
1244                 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1245                 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1246             break;
1247 
1248         case PIN_CONFIG_SLEW_RATE:
1249             arg = (arg >= 1 ? 1 : 0);
1250             bcm281xx_pin_update(val, mask, arg,
1251                 BCM281XX_PIN_SHIFT(I2C, SLEW),
1252                 BCM281XX_PIN_MASK(I2C, SLEW));
1253             break;
1254 
1255         case PIN_CONFIG_INPUT_ENABLE:
1256             /* inversed since register is for input _disable_ */
1257             arg = (arg >= 1 ? 0 : 1);
1258             bcm281xx_pin_update(val, mask, arg,
1259                 BCM281XX_PIN_SHIFT(I2C, INPUT_DIS),
1260                 BCM281XX_PIN_MASK(I2C, INPUT_DIS));
1261             break;
1262 
1263         default:
1264             dev_err(pctldev->dev,
1265                 "Unrecognized pin config %d for pin %s (%d).\n",
1266                 param, pdata->pins[pin].name, pin);
1267             return -EINVAL;
1268 
1269         } /* switch config */
1270     } /* for each config */
1271 
1272     return 0;
1273 }
1274 
1275 /* Goes through the configs and update register val/mask */
1276 static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev,
1277                     unsigned pin,
1278                     unsigned long *configs,
1279                     unsigned num_configs,
1280                     u32 *val,
1281                     u32 *mask)
1282 {
1283     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1284     int i;
1285     enum pin_config_param param;
1286     u32 arg;
1287 
1288     for (i = 0; i < num_configs; i++) {
1289         param = pinconf_to_config_param(configs[i]);
1290         arg = pinconf_to_config_argument(configs[i]);
1291 
1292         switch (param) {
1293         case PIN_CONFIG_SLEW_RATE:
1294             arg = (arg >= 1 ? 1 : 0);
1295             bcm281xx_pin_update(val, mask, arg,
1296                 BCM281XX_PIN_SHIFT(HDMI, MODE),
1297                 BCM281XX_PIN_MASK(HDMI, MODE));
1298             break;
1299 
1300         case PIN_CONFIG_INPUT_ENABLE:
1301             /* inversed since register is for input _disable_ */
1302             arg = (arg >= 1 ? 0 : 1);
1303             bcm281xx_pin_update(val, mask, arg,
1304                 BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS),
1305                 BCM281XX_PIN_MASK(HDMI, INPUT_DIS));
1306             break;
1307 
1308         default:
1309             dev_err(pctldev->dev,
1310                 "Unrecognized pin config %d for pin %s (%d).\n",
1311                 param, pdata->pins[pin].name, pin);
1312             return -EINVAL;
1313 
1314         } /* switch config */
1315     } /* for each config */
1316 
1317     return 0;
1318 }
1319 
1320 static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
1321                        unsigned pin,
1322                        unsigned long *configs,
1323                        unsigned num_configs)
1324 {
1325     struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1326     enum bcm281xx_pin_type pin_type;
1327     u32 offset = 4 * pin;
1328     u32 cfg_val, cfg_mask;
1329     int rc;
1330 
1331     cfg_val = 0;
1332     cfg_mask = 0;
1333     pin_type = pin_type_get(pctldev, pin);
1334 
1335     /* Different pins have different configuration options */
1336     switch (pin_type) {
1337     case BCM281XX_PIN_TYPE_STD:
1338         rc = bcm281xx_std_pin_update(pctldev, pin, configs,
1339             num_configs, &cfg_val, &cfg_mask);
1340         break;
1341 
1342     case BCM281XX_PIN_TYPE_I2C:
1343         rc = bcm281xx_i2c_pin_update(pctldev, pin, configs,
1344             num_configs, &cfg_val, &cfg_mask);
1345         break;
1346 
1347     case BCM281XX_PIN_TYPE_HDMI:
1348         rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs,
1349             num_configs, &cfg_val, &cfg_mask);
1350         break;
1351 
1352     default:
1353         dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
1354             pdata->pins[pin].name, pin);
1355         return -EINVAL;
1356 
1357     } /* switch pin type */
1358 
1359     if (rc)
1360         return rc;
1361 
1362     dev_dbg(pctldev->dev,
1363         "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
1364         __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
1365 
1366     rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
1367     if (rc) {
1368         dev_err(pctldev->dev,
1369             "Error updating register for pin %s (%d).\n",
1370             pdata->pins[pin].name, pin);
1371         return rc;
1372     }
1373 
1374     return 0;
1375 }
1376 
1377 static const struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
1378     .pin_config_get = bcm281xx_pinctrl_pin_config_get,
1379     .pin_config_set = bcm281xx_pinctrl_pin_config_set,
1380 };
1381 
1382 static struct pinctrl_desc bcm281xx_pinctrl_desc = {
1383     /* name, pins, npins members initialized in probe function */
1384     .pctlops = &bcm281xx_pinctrl_ops,
1385     .pmxops = &bcm281xx_pinctrl_pinmux_ops,
1386     .confops = &bcm281xx_pinctrl_pinconf_ops,
1387     .owner = THIS_MODULE,
1388 };
1389 
1390 static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
1391 {
1392     struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
1393     struct pinctrl_dev *pctl;
1394 
1395     /* So far We can assume there is only 1 bank of registers */
1396     pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
1397     if (IS_ERR(pdata->reg_base)) {
1398         dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
1399         return PTR_ERR(pdata->reg_base);
1400     }
1401 
1402     /* Initialize the dynamic part of pinctrl_desc */
1403     pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
1404         &bcm281xx_pinctrl_regmap_config);
1405     if (IS_ERR(pdata->regmap)) {
1406         dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
1407         return -ENODEV;
1408     }
1409 
1410     bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev);
1411     bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins;
1412     bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins;
1413 
1414     pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata);
1415     if (IS_ERR(pctl)) {
1416         dev_err(&pdev->dev, "Failed to register pinctrl\n");
1417         return PTR_ERR(pctl);
1418     }
1419 
1420     platform_set_drvdata(pdev, pdata);
1421 
1422     return 0;
1423 }
1424 
1425 static const struct of_device_id bcm281xx_pinctrl_of_match[] = {
1426     { .compatible = "brcm,bcm11351-pinctrl", },
1427     { },
1428 };
1429 
1430 static struct platform_driver bcm281xx_pinctrl_driver = {
1431     .driver = {
1432         .name = "bcm281xx-pinctrl",
1433         .of_match_table = bcm281xx_pinctrl_of_match,
1434     },
1435 };
1436 builtin_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe);
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