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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Actions Semi S500 SoC Pinctrl driver
0004  *
0005  * Copyright (c) 2014 Actions Semi Inc.
0006  * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/pinctrl/pinconf-generic.h>
0013 #include <linux/pinctrl/pinctrl.h>
0014 #include "pinctrl-owl.h"
0015 
0016 /* Pinctrl registers offset */
0017 #define MFCTL0          (0x0040)
0018 #define MFCTL1          (0x0044)
0019 #define MFCTL2          (0x0048)
0020 #define MFCTL3          (0x004C)
0021 #define PAD_PULLCTL0        (0x0060)
0022 #define PAD_PULLCTL1        (0x0064)
0023 #define PAD_PULLCTL2        (0x0068)
0024 #define PAD_ST0         (0x006C)
0025 #define PAD_ST1         (0x0070)
0026 #define PAD_CTL         (0x0074)
0027 #define PAD_DRV0        (0x0080)
0028 #define PAD_DRV1        (0x0084)
0029 #define PAD_DRV2        (0x0088)
0030 
0031 #define _GPIOA(offset)      (offset)
0032 #define _GPIOB(offset)      (32 + (offset))
0033 #define _GPIOC(offset)      (64 + (offset))
0034 #define _GPIOD(offset)      (96 + (offset))
0035 #define _GPIOE(offset)      (128 + (offset))
0036 
0037 #define NUM_GPIOS       (_GPIOE(3) + 1)
0038 #define _PIN(offset)        (NUM_GPIOS + (offset))
0039 
0040 #define DNAND_DQS       _GPIOA(12)
0041 #define DNAND_DQSN      _GPIOA(13)
0042 #define ETH_TXD0        _GPIOA(14)
0043 #define ETH_TXD1        _GPIOA(15)
0044 #define ETH_TXEN        _GPIOA(16)
0045 #define ETH_RXER        _GPIOA(17)
0046 #define ETH_CRS_DV      _GPIOA(18)
0047 #define ETH_RXD1        _GPIOA(19)
0048 #define ETH_RXD0        _GPIOA(20)
0049 #define ETH_REF_CLK     _GPIOA(21)
0050 #define ETH_MDC         _GPIOA(22)
0051 #define ETH_MDIO        _GPIOA(23)
0052 #define SIRQ0           _GPIOA(24)
0053 #define SIRQ1           _GPIOA(25)
0054 #define SIRQ2           _GPIOA(26)
0055 #define I2S_D0          _GPIOA(27)
0056 #define I2S_BCLK0       _GPIOA(28)
0057 #define I2S_LRCLK0      _GPIOA(29)
0058 #define I2S_MCLK0       _GPIOA(30)
0059 #define I2S_D1          _GPIOA(31)
0060 
0061 #define I2S_BCLK1       _GPIOB(0)
0062 #define I2S_LRCLK1      _GPIOB(1)
0063 #define I2S_MCLK1       _GPIOB(2)
0064 #define KS_IN0          _GPIOB(3)
0065 #define KS_IN1          _GPIOB(4)
0066 #define KS_IN2          _GPIOB(5)
0067 #define KS_IN3          _GPIOB(6)
0068 #define KS_OUT0         _GPIOB(7)
0069 #define KS_OUT1         _GPIOB(8)
0070 #define KS_OUT2         _GPIOB(9)
0071 #define LVDS_OEP        _GPIOB(10)
0072 #define LVDS_OEN        _GPIOB(11)
0073 #define LVDS_ODP        _GPIOB(12)
0074 #define LVDS_ODN        _GPIOB(13)
0075 #define LVDS_OCP        _GPIOB(14)
0076 #define LVDS_OCN        _GPIOB(15)
0077 #define LVDS_OBP        _GPIOB(16)
0078 #define LVDS_OBN        _GPIOB(17)
0079 #define LVDS_OAP        _GPIOB(18)
0080 #define LVDS_OAN        _GPIOB(19)
0081 #define LVDS_EEP        _GPIOB(20)
0082 #define LVDS_EEN        _GPIOB(21)
0083 #define LVDS_EDP        _GPIOB(22)
0084 #define LVDS_EDN        _GPIOB(23)
0085 #define LVDS_ECP        _GPIOB(24)
0086 #define LVDS_ECN        _GPIOB(25)
0087 #define LVDS_EBP        _GPIOB(26)
0088 #define LVDS_EBN        _GPIOB(27)
0089 #define LVDS_EAP        _GPIOB(28)
0090 #define LVDS_EAN        _GPIOB(29)
0091 #define LCD0_D18        _GPIOB(30)
0092 #define LCD0_D17        _GPIOB(31)
0093 
0094 #define DSI_DP3         _GPIOC(0)
0095 #define DSI_DN3         _GPIOC(1)
0096 #define DSI_DP1         _GPIOC(2)
0097 #define DSI_DN1         _GPIOC(3)
0098 #define DSI_CP          _GPIOC(4)
0099 #define DSI_CN          _GPIOC(5)
0100 #define DSI_DP0         _GPIOC(6)
0101 #define DSI_DN0         _GPIOC(7)
0102 #define DSI_DP2         _GPIOC(8)
0103 #define DSI_DN2         _GPIOC(9)
0104 #define SD0_D0          _GPIOC(10)
0105 #define SD0_D1          _GPIOC(11)
0106 #define SD0_D2          _GPIOC(12)
0107 #define SD0_D3          _GPIOC(13)
0108 #define SD1_D0          _GPIOC(14) /* SD0_D4 */
0109 #define SD1_D1          _GPIOC(15) /* SD0_D5 */
0110 #define SD1_D2          _GPIOC(16) /* SD0_D6 */
0111 #define SD1_D3          _GPIOC(17) /* SD0_D7 */
0112 #define SD0_CMD         _GPIOC(18)
0113 #define SD0_CLK         _GPIOC(19)
0114 #define SD1_CMD         _GPIOC(20)
0115 #define SD1_CLK         _GPIOC(21)
0116 #define SPI0_SCLK       _GPIOC(22)
0117 #define SPI0_SS         _GPIOC(23)
0118 #define SPI0_MISO       _GPIOC(24)
0119 #define SPI0_MOSI       _GPIOC(25)
0120 #define UART0_RX        _GPIOC(26)
0121 #define UART0_TX        _GPIOC(27)
0122 #define I2C0_SCLK       _GPIOC(28)
0123 #define I2C0_SDATA      _GPIOC(29)
0124 #define SENSOR0_PCLK        _GPIOC(31)
0125 
0126 #define SENSOR0_CKOUT       _GPIOD(10)
0127 #define DNAND_ALE       _GPIOD(12)
0128 #define DNAND_CLE       _GPIOD(13)
0129 #define DNAND_CEB0      _GPIOD(14)
0130 #define DNAND_CEB1      _GPIOD(15)
0131 #define DNAND_CEB2      _GPIOD(16)
0132 #define DNAND_CEB3      _GPIOD(17)
0133 #define UART2_RX        _GPIOD(18)
0134 #define UART2_TX        _GPIOD(19)
0135 #define UART2_RTSB      _GPIOD(20)
0136 #define UART2_CTSB      _GPIOD(21)
0137 #define UART3_RX        _GPIOD(22)
0138 #define UART3_TX        _GPIOD(23)
0139 #define UART3_RTSB      _GPIOD(24)
0140 #define UART3_CTSB      _GPIOD(25)
0141 #define PCM1_IN         _GPIOD(28)
0142 #define PCM1_CLK        _GPIOD(29)
0143 #define PCM1_SYNC       _GPIOD(30)
0144 #define PCM1_OUT        _GPIOD(31)
0145 
0146 #define I2C1_SCLK       _GPIOE(0)
0147 #define I2C1_SDATA      _GPIOE(1)
0148 #define I2C2_SCLK       _GPIOE(2)
0149 #define I2C2_SDATA      _GPIOE(3)
0150 
0151 #define CSI_DN0         _PIN(0)
0152 #define CSI_DP0         _PIN(1)
0153 #define CSI_DN1         _PIN(2)
0154 #define CSI_DP1         _PIN(3)
0155 #define CSI_CN          _PIN(4)
0156 #define CSI_CP          _PIN(5)
0157 #define CSI_DN2         _PIN(6)
0158 #define CSI_DP2         _PIN(7)
0159 #define CSI_DN3         _PIN(8)
0160 #define CSI_DP3         _PIN(9)
0161 
0162 #define DNAND_D0        _PIN(10)
0163 #define DNAND_D1        _PIN(11)
0164 #define DNAND_D2        _PIN(12)
0165 #define DNAND_D3        _PIN(13)
0166 #define DNAND_D4        _PIN(14)
0167 #define DNAND_D5        _PIN(15)
0168 #define DNAND_D6        _PIN(16)
0169 #define DNAND_D7        _PIN(17)
0170 #define DNAND_WRB       _PIN(18)
0171 #define DNAND_RDB       _PIN(19)
0172 #define DNAND_RDBN      _PIN(20)
0173 #define DNAND_RB        _PIN(21)
0174 
0175 #define PORB            _PIN(22)
0176 #define CLKO_25M        _PIN(23)
0177 #define BSEL            _PIN(24)
0178 #define PKG0            _PIN(25)
0179 #define PKG1            _PIN(26)
0180 #define PKG2            _PIN(27)
0181 #define PKG3            _PIN(28)
0182 
0183 #define _FIRSTPAD       _GPIOA(0)
0184 #define _LASTPAD        PKG3
0185 #define NUM_PADS        (_PIN(28) + 1)
0186 
0187 static const struct pinctrl_pin_desc s500_pads[] = {
0188     PINCTRL_PIN(DNAND_DQS, "dnand_dqs"),
0189     PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"),
0190     PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
0191     PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
0192     PINCTRL_PIN(ETH_TXEN, "eth_txen"),
0193     PINCTRL_PIN(ETH_RXER, "eth_rxer"),
0194     PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
0195     PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
0196     PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
0197     PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
0198     PINCTRL_PIN(ETH_MDC, "eth_mdc"),
0199     PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
0200     PINCTRL_PIN(SIRQ0, "sirq0"),
0201     PINCTRL_PIN(SIRQ1, "sirq1"),
0202     PINCTRL_PIN(SIRQ2, "sirq2"),
0203     PINCTRL_PIN(I2S_D0, "i2s_d0"),
0204     PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
0205     PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
0206     PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
0207     PINCTRL_PIN(I2S_D1, "i2s_d1"),
0208     PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
0209     PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
0210     PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
0211     PINCTRL_PIN(KS_IN0, "ks_in0"),
0212     PINCTRL_PIN(KS_IN1, "ks_in1"),
0213     PINCTRL_PIN(KS_IN2, "ks_in2"),
0214     PINCTRL_PIN(KS_IN3, "ks_in3"),
0215     PINCTRL_PIN(KS_OUT0, "ks_out0"),
0216     PINCTRL_PIN(KS_OUT1, "ks_out1"),
0217     PINCTRL_PIN(KS_OUT2, "ks_out2"),
0218     PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
0219     PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
0220     PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
0221     PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
0222     PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
0223     PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
0224     PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
0225     PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
0226     PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
0227     PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
0228     PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
0229     PINCTRL_PIN(LVDS_EEN, "lvds_een"),
0230     PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
0231     PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
0232     PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
0233     PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
0234     PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
0235     PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
0236     PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
0237     PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
0238     PINCTRL_PIN(LCD0_D18, "lcd0_d18"),
0239     PINCTRL_PIN(LCD0_D17, "lcd0_d17"),
0240     PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
0241     PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
0242     PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
0243     PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
0244     PINCTRL_PIN(DSI_CP, "dsi_cp"),
0245     PINCTRL_PIN(DSI_CN, "dsi_cn"),
0246     PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
0247     PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
0248     PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
0249     PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
0250     PINCTRL_PIN(SD0_D0, "sd0_d0"),
0251     PINCTRL_PIN(SD0_D1, "sd0_d1"),
0252     PINCTRL_PIN(SD0_D2, "sd0_d2"),
0253     PINCTRL_PIN(SD0_D3, "sd0_d3"),
0254     PINCTRL_PIN(SD1_D0, "sd1_d0"),
0255     PINCTRL_PIN(SD1_D1, "sd1_d1"),
0256     PINCTRL_PIN(SD1_D2, "sd1_d2"),
0257     PINCTRL_PIN(SD1_D3, "sd1_d3"),
0258     PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
0259     PINCTRL_PIN(SD0_CLK, "sd0_clk"),
0260     PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
0261     PINCTRL_PIN(SD1_CLK, "sd1_clk"),
0262     PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"),
0263     PINCTRL_PIN(SPI0_SS, "spi0_ss"),
0264     PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
0265     PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"),
0266     PINCTRL_PIN(UART0_RX, "uart0_rx"),
0267     PINCTRL_PIN(UART0_TX, "uart0_tx"),
0268     PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
0269     PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
0270     PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
0271     PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
0272     PINCTRL_PIN(DNAND_ALE, "dnand_ale"),
0273     PINCTRL_PIN(DNAND_CLE, "dnand_cle"),
0274     PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"),
0275     PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"),
0276     PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"),
0277     PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"),
0278     PINCTRL_PIN(UART2_RX, "uart2_rx"),
0279     PINCTRL_PIN(UART2_TX, "uart2_tx"),
0280     PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
0281     PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
0282     PINCTRL_PIN(UART3_RX, "uart3_rx"),
0283     PINCTRL_PIN(UART3_TX, "uart3_tx"),
0284     PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
0285     PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
0286     PINCTRL_PIN(PCM1_IN, "pcm1_in"),
0287     PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
0288     PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
0289     PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
0290     PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
0291     PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
0292     PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
0293     PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
0294     PINCTRL_PIN(CSI_DN0, "csi_dn0"),
0295     PINCTRL_PIN(CSI_DP0, "csi_dp0"),
0296     PINCTRL_PIN(CSI_DN1, "csi_dn1"),
0297     PINCTRL_PIN(CSI_DP1, "csi_dp1"),
0298     PINCTRL_PIN(CSI_DN2, "csi_dn2"),
0299     PINCTRL_PIN(CSI_DP2, "csi_dp2"),
0300     PINCTRL_PIN(CSI_DN3, "csi_dn3"),
0301     PINCTRL_PIN(CSI_DP3, "csi_dp3"),
0302     PINCTRL_PIN(CSI_CN, "csi_cn"),
0303     PINCTRL_PIN(CSI_CP, "csi_cp"),
0304     PINCTRL_PIN(DNAND_D0, "dnand_d0"),
0305     PINCTRL_PIN(DNAND_D1, "dnand_d1"),
0306     PINCTRL_PIN(DNAND_D2, "dnand_d2"),
0307     PINCTRL_PIN(DNAND_D3, "dnand_d3"),
0308     PINCTRL_PIN(DNAND_D4, "dnand_d4"),
0309     PINCTRL_PIN(DNAND_D5, "dnand_d5"),
0310     PINCTRL_PIN(DNAND_D6, "dnand_d6"),
0311     PINCTRL_PIN(DNAND_D7, "dnand_d7"),
0312     PINCTRL_PIN(DNAND_RB, "dnand_rb"),
0313     PINCTRL_PIN(DNAND_RDB, "dnand_rdb"),
0314     PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"),
0315     PINCTRL_PIN(DNAND_WRB, "dnand_wrb"),
0316     PINCTRL_PIN(PORB, "porb"),
0317     PINCTRL_PIN(CLKO_25M, "clko_25m"),
0318     PINCTRL_PIN(BSEL, "bsel"),
0319     PINCTRL_PIN(PKG0, "pkg0"),
0320     PINCTRL_PIN(PKG1, "pkg1"),
0321     PINCTRL_PIN(PKG2, "pkg2"),
0322     PINCTRL_PIN(PKG3, "pkg3"),
0323 };
0324 
0325 enum s500_pinmux_functions {
0326     S500_MUX_NOR,
0327     S500_MUX_ETH_RMII,
0328     S500_MUX_ETH_SMII,
0329     S500_MUX_SPI0,
0330     S500_MUX_SPI1,
0331     S500_MUX_SPI2,
0332     S500_MUX_SPI3,
0333     S500_MUX_SENS0,
0334     S500_MUX_SENS1,
0335     S500_MUX_UART0,
0336     S500_MUX_UART1,
0337     S500_MUX_UART2,
0338     S500_MUX_UART3,
0339     S500_MUX_UART4,
0340     S500_MUX_UART5,
0341     S500_MUX_UART6,
0342     S500_MUX_I2S0,
0343     S500_MUX_I2S1,
0344     S500_MUX_PCM1,
0345     S500_MUX_PCM0,
0346     S500_MUX_KS,
0347     S500_MUX_JTAG,
0348     S500_MUX_PWM0,
0349     S500_MUX_PWM1,
0350     S500_MUX_PWM2,
0351     S500_MUX_PWM3,
0352     S500_MUX_PWM4,
0353     S500_MUX_PWM5,
0354     S500_MUX_P0,
0355     S500_MUX_SD0,
0356     S500_MUX_SD1,
0357     S500_MUX_SD2,
0358     S500_MUX_I2C0,
0359     S500_MUX_I2C1,
0360     /*S500_MUX_I2C2,*/
0361     S500_MUX_I2C3,
0362     S500_MUX_DSI,
0363     S500_MUX_LVDS,
0364     S500_MUX_USB30,
0365     S500_MUX_CLKO_25M,
0366     S500_MUX_MIPI_CSI,
0367     S500_MUX_NAND,
0368     S500_MUX_SPDIF,
0369     /*S500_MUX_SIRQ0,*/
0370     /*S500_MUX_SIRQ1,*/
0371     /*S500_MUX_SIRQ2,*/
0372     S500_MUX_TS,
0373     S500_MUX_LCD0,
0374     S500_MUX_RESERVED,
0375 };
0376 
0377 /* MFPCTL group data */
0378 /* mfp0_31_26 reserved */
0379 /* mfp0_25_23 */
0380 static unsigned int lcd0_d18_mfp_pads[]     = { LCD0_D18 };
0381 static unsigned int lcd0_d18_mfp_funcs[]    = { S500_MUX_NOR,
0382                             S500_MUX_SENS1,
0383                             S500_MUX_PWM2,
0384                             S500_MUX_PWM4,
0385                             S500_MUX_LCD0 };
0386 /* mfp0_22_20 */
0387 static unsigned int rmii_crs_dv_mfp_pads[]  = { ETH_CRS_DV };
0388 static unsigned int rmii_crs_dv_mfp_funcs[] = { S500_MUX_ETH_RMII,
0389                             S500_MUX_ETH_SMII,
0390                             S500_MUX_SPI2,
0391                             S500_MUX_UART4,
0392                             S500_MUX_PWM4 };
0393 /* mfp0_18_16_eth_txd0 */
0394 static unsigned int rmii_txd0_mfp_pads[]    = { ETH_TXD0 };
0395 static unsigned int rmii_txd0_mfp_funcs[]   = { S500_MUX_ETH_RMII,
0396                             S500_MUX_ETH_SMII,
0397                             S500_MUX_SPI2,
0398                             S500_MUX_UART6,
0399                             S500_MUX_PWM4 };
0400 /* mfp0_18_16_eth_txd1 */
0401 static unsigned int rmii_txd1_mfp_pads[]    = { ETH_TXD1 };
0402 static unsigned int rmii_txd1_mfp_funcs[]   = { S500_MUX_ETH_RMII,
0403                             S500_MUX_ETH_SMII,
0404                             S500_MUX_SPI2,
0405                             S500_MUX_UART6,
0406                             S500_MUX_PWM5 };
0407 /* mfp0_15_13_rmii_txen */
0408 static unsigned int rmii_txen_mfp_pads[]    = { ETH_TXEN };
0409 static unsigned int rmii_txen_mfp_funcs[]   = { S500_MUX_ETH_RMII,
0410                             S500_MUX_UART2,
0411                             S500_MUX_SPI3,
0412                             S500_MUX_PWM0 };
0413 /* mfp0_15_13_rmii_rxen */
0414 static unsigned int rmii_rxen_mfp_pads[]    = { ETH_RXER };
0415 static unsigned int rmii_rxen_mfp_funcs[]   = { S500_MUX_ETH_RMII,
0416                             S500_MUX_UART2,
0417                             S500_MUX_SPI3,
0418                             S500_MUX_PWM1 };
0419 /* mfp0_12_11 reserved */
0420 
0421 /* mfp0_10_8_rmii_rxd1 */
0422 static unsigned int rmii_rxd1_mfp_pads[]    = { ETH_RXD1 };
0423 static unsigned int rmii_rxd1_mfp_funcs[]   = { S500_MUX_ETH_RMII,
0424                             S500_MUX_UART2,
0425                             S500_MUX_SPI3,
0426                             S500_MUX_PWM2,
0427                             S500_MUX_UART5 };
0428 /* mfp0_10_8_rmii_rxd0 */
0429 static unsigned int rmii_rxd0_mfp_pads[]    = { ETH_RXD0 };
0430 static unsigned int rmii_rxd0_mfp_funcs[]   = { S500_MUX_ETH_RMII,
0431                             S500_MUX_UART2,
0432                             S500_MUX_SPI3,
0433                             S500_MUX_PWM3,
0434                             S500_MUX_UART5 };
0435 /* mfp0_7_6 */
0436 static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };
0437 static unsigned int rmii_ref_clk_mfp_funcs[]    = { S500_MUX_ETH_RMII,
0438                             S500_MUX_UART4,
0439                             S500_MUX_SPI2,
0440                             S500_MUX_RESERVED,
0441                             S500_MUX_ETH_SMII };
0442 /* mfp0_5 */
0443 static unsigned int i2s_d0_mfp_pads[]       = { I2S_D0 };
0444 static unsigned int i2s_d0_mfp_funcs[]      = { S500_MUX_I2S0,
0445                             S500_MUX_NOR };
0446 /* mfp0_4_3 */
0447 static unsigned int i2s_pcm1_mfp_pads[]     = { I2S_LRCLK0, I2S_MCLK0 };
0448 static unsigned int i2s_pcm1_mfp_funcs[]    = { S500_MUX_I2S0,
0449                             S500_MUX_NOR,
0450                             S500_MUX_PCM1 };
0451 /* mfp0_2_1_i2s0 */
0452 static unsigned int i2s0_pcm0_mfp_pads[]    = { I2S_BCLK0 };
0453 static unsigned int i2s0_pcm0_mfp_funcs[]   = { S500_MUX_I2S0,
0454                             S500_MUX_NOR,
0455                             S500_MUX_PCM0 };
0456 /* mfp0_2_1_i2s1 */
0457 static unsigned int i2s1_pcm0_mfp_pads[]    = { I2S_BCLK1, I2S_LRCLK1,
0458                             I2S_MCLK1 };
0459 static unsigned int i2s1_pcm0_mfp_funcs[]   = { S500_MUX_I2S1,
0460                             S500_MUX_NOR,
0461                             S500_MUX_PCM0 };
0462 /* mfp0_0 */
0463 static unsigned int i2s_d1_mfp_pads[]       = { I2S_D1 };
0464 static unsigned int i2s_d1_mfp_funcs[]      = { S500_MUX_I2S1,
0465                             S500_MUX_NOR };
0466 /* mfp1_31_29_ks_in0 */
0467 static unsigned int ks_in0_mfp_pads[]       = { KS_IN0 };
0468 static unsigned int ks_in0_mfp_funcs[]      = { S500_MUX_KS,
0469                             S500_MUX_JTAG,
0470                             S500_MUX_NOR,
0471                             S500_MUX_PWM0,
0472                             S500_MUX_PWM4,
0473                             S500_MUX_SENS1,
0474                             S500_MUX_PWM4,
0475                             S500_MUX_P0 };
0476 /* mfp1_31_29_ks_in1 */
0477 static unsigned int ks_in1_mfp_pads[]       = { KS_IN1 };
0478 static unsigned int ks_in1_mfp_funcs[]      = { S500_MUX_KS,
0479                             S500_MUX_JTAG,
0480                             S500_MUX_NOR,
0481                             S500_MUX_PWM1,
0482                             S500_MUX_PWM5,
0483                             S500_MUX_SENS1,
0484                             S500_MUX_PWM1,
0485                             S500_MUX_USB30 };
0486 /* mfp1_31_29_ks_in2 */
0487 static unsigned int ks_in2_mfp_pads[]       = { KS_IN2 };
0488 static unsigned int ks_in2_mfp_funcs[]      = { S500_MUX_KS,
0489                             S500_MUX_JTAG,
0490                             S500_MUX_NOR,
0491                             S500_MUX_PWM0,
0492                             S500_MUX_PWM0,
0493                             S500_MUX_SENS1,
0494                             S500_MUX_PWM0,
0495                             S500_MUX_P0 };
0496 /* mfp1_28_26_ks_in3 */
0497 static unsigned int ks_in3_mfp_pads[]       = { KS_IN3 };
0498 static unsigned int ks_in3_mfp_funcs[]      = { S500_MUX_KS,
0499                             S500_MUX_JTAG,
0500                             S500_MUX_NOR,
0501                             S500_MUX_PWM1,
0502                             S500_MUX_RESERVED,
0503                             S500_MUX_SENS1 };
0504 /* mfp1_28_26_ks_out0 */
0505 static unsigned int ks_out0_mfp_pads[]      = { KS_OUT0 };
0506 static unsigned int ks_out0_mfp_funcs[]     = { S500_MUX_KS,
0507                             S500_MUX_UART5,
0508                             S500_MUX_NOR,
0509                             S500_MUX_PWM2,
0510                             S500_MUX_RESERVED,
0511                             S500_MUX_SENS1,
0512                             S500_MUX_SD0 };
0513 /* mfp1_28_26_ks_out1 */
0514 static unsigned int ks_out1_mfp_pads[]      = { KS_OUT1 };
0515 static unsigned int ks_out1_mfp_funcs[]     = { S500_MUX_KS,
0516                             S500_MUX_JTAG,
0517                             S500_MUX_NOR,
0518                             S500_MUX_PWM3,
0519                             S500_MUX_RESERVED,
0520                             S500_MUX_SENS1,
0521                             S500_MUX_SD0 };
0522 /* mfp1_25_23 */
0523 static unsigned int ks_out2_mfp_pads[]      = { KS_OUT2 };
0524 static unsigned int ks_out2_mfp_funcs[]     = { S500_MUX_SD0,
0525                             S500_MUX_KS,
0526                             S500_MUX_NOR,
0527                             S500_MUX_PWM2,
0528                             S500_MUX_UART5,
0529                             S500_MUX_SENS1 };
0530 /* mfp1_22_21 */
0531 static unsigned int lvds_o_pn_mfp_pads[]    = { LVDS_OEP, LVDS_OEN,
0532                             LVDS_ODP, LVDS_ODN,
0533                             LVDS_OCP, LVDS_OCN,
0534                             LVDS_OBP, LVDS_OBN,
0535                             LVDS_OAP, LVDS_OAN };
0536 static unsigned int lvds_o_pn_mfp_funcs[]   = { S500_MUX_LVDS,
0537                             S500_MUX_TS,
0538                             S500_MUX_LCD0 };
0539 /* mfp1_20_19 */
0540 static unsigned int dsi_dn0_mfp_pads[]      = { DSI_DN0 };
0541 static unsigned int dsi_dn0_mfp_funcs[]     = { S500_MUX_DSI,
0542                             S500_MUX_UART2,
0543                             S500_MUX_SPI0 };
0544 /* mfp1_18_17 */
0545 static unsigned int dsi_dp2_mfp_pads[]      = { DSI_DP2 };
0546 static unsigned int dsi_dp2_mfp_funcs[]     = { S500_MUX_DSI,
0547                             S500_MUX_UART2,
0548                             S500_MUX_SPI0,
0549                             S500_MUX_SD1 };
0550 /* mfp1_16_14 */
0551 static unsigned int lcd0_d17_mfp_pads[]     = { LCD0_D17 };
0552 static unsigned int lcd0_d17_mfp_funcs[]    = { S500_MUX_NOR,
0553                             S500_MUX_SD0,
0554                             S500_MUX_SD1,
0555                             S500_MUX_PWM3,
0556                             S500_MUX_LCD0 };
0557 /* mfp1_13_12 */
0558 static unsigned int dsi_dp3_mfp_pads[]      = { DSI_DP3 };
0559 static unsigned int dsi_dp3_mfp_funcs[]     = { S500_MUX_DSI,
0560                             S500_MUX_SD0,
0561                             S500_MUX_SD1,
0562                             S500_MUX_LCD0 };
0563 /* mfp1_11_10 */
0564 static unsigned int dsi_dn3_mfp_pads[]      = { DSI_DN3 };
0565 static unsigned int dsi_dn3_mfp_funcs[]     = { S500_MUX_DSI,
0566                             S500_MUX_RESERVED,
0567                             S500_MUX_SD1,
0568                             S500_MUX_LCD0 };
0569 /* mfp1_9_7 */
0570 static unsigned int dsi_dp0_mfp_pads[]      = { DSI_DP0 };
0571 static unsigned int dsi_dp0_mfp_funcs[]     = { S500_MUX_DSI,
0572                             S500_MUX_RESERVED,
0573                             S500_MUX_SD0,
0574                             S500_MUX_UART2,
0575                             S500_MUX_SPI0 };
0576 /* mfp1_6_5 */
0577 static unsigned int lvds_ee_pn_mfp_pads[]   = { LVDS_EEP, LVDS_EEN };
0578 static unsigned int lvds_ee_pn_mfp_funcs[]  = { S500_MUX_LVDS,
0579                             S500_MUX_NOR,
0580                             S500_MUX_TS,
0581                             S500_MUX_LCD0 };
0582 /* mfp1_4_3 */
0583 static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SCLK, SPI0_MOSI };
0584 static unsigned int spi0_i2c_pcm_mfp_funcs[]    = { S500_MUX_SPI0,
0585                             S500_MUX_NOR,
0586                             S500_MUX_I2C3,
0587                             S500_MUX_PCM0 };
0588 /* mfp1_2_0 */
0589 static unsigned int spi0_i2s_pcm_mfp_pads[] = { SPI0_SS, SPI0_MISO };
0590 static unsigned int spi0_i2s_pcm_mfp_funcs[]    = { S500_MUX_SPI0,
0591                             S500_MUX_NOR,
0592                             S500_MUX_I2S1,
0593                             S500_MUX_PCM1,
0594                             S500_MUX_PCM0 };
0595 /* mfp2_31 reserved */
0596 /* mfp2_30_29 */
0597 static unsigned int dsi_dnp1_cp_mfp_pads[]  = { DSI_DP1, DSI_CP, DSI_CN };
0598 static unsigned int dsi_dnp1_cp_mfp_funcs[] = { S500_MUX_DSI,
0599                             S500_MUX_SD1,
0600                             S500_MUX_LCD0 };
0601 /* mfp2_28_27 */
0602 static unsigned int lvds_e_pn_mfp_pads[]    = { LVDS_EDP, LVDS_EDN,
0603                             LVDS_ECP, LVDS_ECN,
0604                             LVDS_EBP, LVDS_EBN,
0605                             LVDS_EAP, LVDS_EAN };
0606 static unsigned int lvds_e_pn_mfp_funcs[]   = { S500_MUX_LVDS,
0607                             S500_MUX_NOR,
0608                             S500_MUX_LCD0 };
0609 /* mfp2_26_24 */
0610 static unsigned int dsi_dn2_mfp_pads[]      = { DSI_DN2 };
0611 static unsigned int dsi_dn2_mfp_funcs[]     = { S500_MUX_DSI,
0612                             S500_MUX_RESERVED,
0613                             S500_MUX_SD1,
0614                             S500_MUX_UART2,
0615                             S500_MUX_SPI0 };
0616 /* mfp2_23 */
0617 static unsigned int uart2_rtsb_mfp_pads[]   = { UART2_RTSB };
0618 static unsigned int uart2_rtsb_mfp_funcs[]  = { S500_MUX_UART2,
0619                             S500_MUX_UART0 };
0620 /* mfp2_22 */
0621 static unsigned int uart2_ctsb_mfp_pads[]   = { UART2_CTSB };
0622 static unsigned int uart2_ctsb_mfp_funcs[]  = { S500_MUX_UART2,
0623                             S500_MUX_UART0 };
0624 /* mfp2_21 */
0625 static unsigned int uart3_rtsb_mfp_pads[]   = { UART3_RTSB };
0626 static unsigned int uart3_rtsb_mfp_funcs[]  = { S500_MUX_UART3,
0627                             S500_MUX_UART5 };
0628 /* mfp2_20 */
0629 static unsigned int uart3_ctsb_mfp_pads[]   = { UART3_CTSB };
0630 static unsigned int uart3_ctsb_mfp_funcs[]  = { S500_MUX_UART3,
0631                             S500_MUX_UART5 };
0632 /* mfp2_19_17 */
0633 static unsigned int sd0_d0_mfp_pads[]       = { SD0_D0 };
0634 static unsigned int sd0_d0_mfp_funcs[]      = { S500_MUX_SD0,
0635                             S500_MUX_NOR,
0636                             S500_MUX_RESERVED,
0637                             S500_MUX_JTAG,
0638                             S500_MUX_UART2,
0639                             S500_MUX_UART5 };
0640 /* mfp2_16_14 */
0641 static unsigned int sd0_d1_mfp_pads[]       = { SD0_D1 };
0642 static unsigned int sd0_d1_mfp_funcs[]      = { S500_MUX_SD0,
0643                             S500_MUX_NOR,
0644                             S500_MUX_RESERVED,
0645                             S500_MUX_RESERVED,
0646                             S500_MUX_UART2,
0647                             S500_MUX_UART5 };
0648 /* mfp2_13_11 */
0649 static unsigned int sd0_d2_d3_mfp_pads[]    = { SD0_D2, SD0_D3 };
0650 static unsigned int sd0_d2_d3_mfp_funcs[]   = { S500_MUX_SD0,
0651                             S500_MUX_NOR,
0652                             S500_MUX_RESERVED,
0653                             S500_MUX_JTAG,
0654                             S500_MUX_UART2,
0655                             S500_MUX_UART1 };
0656 /* mfp2_10_9 */
0657 static unsigned int sd1_d0_d3_mfp_pads[]    = { SD1_D0, SD1_D1,
0658                             SD1_D2, SD1_D3 };
0659 static unsigned int sd1_d0_d3_mfp_funcs[]   = { S500_MUX_SD0,
0660                             S500_MUX_NOR,
0661                             S500_MUX_RESERVED,
0662                             S500_MUX_SD1 };
0663 /* mfp2_8_7 */
0664 static unsigned int sd0_cmd_mfp_pads[]      = { SD0_CMD };
0665 static unsigned int sd0_cmd_mfp_funcs[]     = { S500_MUX_SD0,
0666                             S500_MUX_NOR,
0667                             S500_MUX_RESERVED,
0668                             S500_MUX_JTAG };
0669 /* mfp2_6_5 */
0670 static unsigned int sd0_clk_mfp_pads[]      = { SD0_CLK };
0671 static unsigned int sd0_clk_mfp_funcs[]     = { S500_MUX_SD0,
0672                             S500_MUX_RESERVED,
0673                             S500_MUX_JTAG };
0674 /* mfp2_4_3 */
0675 static unsigned int sd1_cmd_mfp_pads[]      = { SD1_CMD };
0676 static unsigned int sd1_cmd_mfp_funcs[]     = { S500_MUX_SD1,
0677                             S500_MUX_NOR };
0678 /* mfp2_2_0 */
0679 static unsigned int uart0_rx_mfp_pads[]     = { UART0_RX };
0680 static unsigned int uart0_rx_mfp_funcs[]    = { S500_MUX_UART0,
0681                             S500_MUX_UART2,
0682                             S500_MUX_SPI1,
0683                             S500_MUX_I2C0,
0684                             S500_MUX_PCM1,
0685                             S500_MUX_I2S1 };
0686 /* mfp3_31 reserved */
0687 /* mfp3_30 */
0688 static unsigned int clko_25m_mfp_pads[]     = { CLKO_25M };
0689 static unsigned int clko_25m_mfp_funcs[]    = { S500_MUX_RESERVED,
0690                             S500_MUX_CLKO_25M };
0691 /* mfp3_29_28 */
0692 static unsigned int csi_cn_cp_mfp_pads[]    = { CSI_CN, CSI_CP };
0693 static unsigned int csi_cn_cp_mfp_funcs[]   = { S500_MUX_MIPI_CSI,
0694                             S500_MUX_SENS0 };
0695 /* mfp3_27_24 reserved */
0696 /* mfp3_23_22 */
0697 static unsigned int sens0_ckout_mfp_pads[]  = { SENSOR0_CKOUT };
0698 static unsigned int sens0_ckout_mfp_funcs[] = { S500_MUX_SENS0,
0699                             S500_MUX_NOR,
0700                             S500_MUX_SENS1,
0701                             S500_MUX_PWM1 };
0702 /* mfp3_21_19 */
0703 static unsigned int uart0_tx_mfp_pads[]     = { UART0_TX };
0704 static unsigned int uart0_tx_mfp_funcs[]    = { S500_MUX_UART0,
0705                             S500_MUX_UART2,
0706                             S500_MUX_SPI1,
0707                             S500_MUX_I2C0,
0708                             S500_MUX_SPDIF,
0709                             S500_MUX_PCM1,
0710                             S500_MUX_I2S1 };
0711 /* mfp3_18_16 */
0712 static unsigned int i2c0_mfp_pads[]     = { I2C0_SCLK,
0713                             I2C0_SDATA };
0714 static unsigned int i2c0_mfp_funcs[]        = { S500_MUX_I2C0,
0715                             S500_MUX_UART2,
0716                             S500_MUX_I2C1,
0717                             S500_MUX_UART1,
0718                             S500_MUX_SPI1 };
0719 /* mfp3_15_14 */
0720 static unsigned int csi_dn_dp_mfp_pads[]    = { CSI_DN0, CSI_DN1,
0721                             CSI_DN2, CSI_DN3,
0722                             CSI_DP0, CSI_DP1,
0723                             CSI_DP2, CSI_DP3 };
0724 static unsigned int csi_dn_dp_mfp_funcs[]   = { S500_MUX_MIPI_CSI,
0725                             S500_MUX_SENS0 };
0726 /* mfp3_13_12 */
0727 static unsigned int sen0_pclk_mfp_pads[]    = { SENSOR0_PCLK };
0728 static unsigned int sen0_pclk_mfp_funcs[]   = { S500_MUX_SENS0,
0729                             S500_MUX_NOR,
0730                             S500_MUX_PWM0 };
0731 /* mfp3_11_10 */
0732 static unsigned int pcm1_in_mfp_pads[]      = { PCM1_IN };
0733 static unsigned int pcm1_in_mfp_funcs[]     = { S500_MUX_PCM1,
0734                             S500_MUX_SENS1,
0735                             S500_MUX_UART4,
0736                             S500_MUX_PWM4 };
0737 /* mfp3_9_8 */
0738 static unsigned int pcm1_clk_mfp_pads[]     = { PCM1_CLK };
0739 static unsigned int pcm1_clk_mfp_funcs[]    = { S500_MUX_PCM1,
0740                             S500_MUX_SENS1,
0741                             S500_MUX_UART4,
0742                             S500_MUX_PWM5 };
0743 /* mfp3_7_6 */
0744 static unsigned int pcm1_sync_mfp_pads[]    = { PCM1_SYNC };
0745 static unsigned int pcm1_sync_mfp_funcs[]   = { S500_MUX_PCM1,
0746                             S500_MUX_SENS1,
0747                             S500_MUX_UART6,
0748                             S500_MUX_I2C3 };
0749 /* mfp3_5_4 */
0750 static unsigned int pcm1_out_mfp_pads[]     = { PCM1_OUT };
0751 static unsigned int pcm1_out_mfp_funcs[]    = { S500_MUX_PCM1,
0752                             S500_MUX_SENS1,
0753                             S500_MUX_UART6,
0754                             S500_MUX_I2C3 };
0755 /* mfp3_3 */
0756 static unsigned int dnand_data_wr_mfp_pads[]    = { DNAND_D0, DNAND_D1,
0757                             DNAND_D2, DNAND_D3,
0758                             DNAND_D4, DNAND_D5,
0759                             DNAND_D6, DNAND_D7,
0760                             DNAND_RDB, DNAND_RDBN };
0761 static unsigned int dnand_data_wr_mfp_funcs[]   = { S500_MUX_NAND,
0762                             S500_MUX_SD2 };
0763 /* mfp3_2 */
0764 static unsigned int dnand_acle_ce0_mfp_pads[]   = { DNAND_ALE,
0765                             DNAND_CLE,
0766                             DNAND_CEB0,
0767                             DNAND_CEB1 };
0768 static unsigned int dnand_acle_ce0_mfp_funcs[]  = { S500_MUX_NAND,
0769                             S500_MUX_SPI2 };
0770 /* mfp3_1_0_nand_ceb2 */
0771 static unsigned int nand_ceb2_mfp_pads[]    = { DNAND_CEB2 };
0772 static unsigned int nand_ceb2_mfp_funcs[]   = { S500_MUX_NAND,
0773                             S500_MUX_PWM5 };
0774 /* mfp3_1_0_nand_ceb3 */
0775 static unsigned int nand_ceb3_mfp_pads[]    = { DNAND_CEB3 };
0776 static unsigned int nand_ceb3_mfp_funcs[]   = { S500_MUX_NAND,
0777                             S500_MUX_PWM4 };
0778 
0779 /* PADDRV group data */
0780 /* paddrv0_29_28 */
0781 static unsigned int sirq_drv_pads[]     = { SIRQ0, SIRQ1, SIRQ2 };
0782 /* paddrv0_23_22 */
0783 static unsigned int rmii_txd01_txen_drv_pads[]  = { ETH_TXD0, ETH_TXD1,
0784                             ETH_TXEN };
0785 /* paddrv0_21_20 */
0786 static unsigned int rmii_rxer_drv_pads[]    = { ETH_RXER };
0787 /* paddrv0_19_18 */
0788 static unsigned int rmii_crs_drv_pads[]     = { ETH_CRS_DV };
0789 /* paddrv0_17_16 */
0790 static unsigned int rmii_rxd10_drv_pads[]   = { ETH_RXD0, ETH_RXD1 };
0791 /* paddrv0_15_14 */
0792 static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK };
0793 /* paddrv0_13_12 */
0794 static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO };
0795 /* paddrv0_11_10 */
0796 static unsigned int i2s_d0_drv_pads[]       = { I2S_D0 };
0797 /* paddrv0_9_8 */
0798 static unsigned int i2s_bclk0_drv_pads[]    = { I2S_BCLK0 };
0799 /* paddrv0_7_6 */
0800 static unsigned int i2s3_drv_pads[]     = { I2S_LRCLK0, I2S_MCLK0,
0801                             I2S_D1 };
0802 /* paddrv0_5_4 */
0803 static unsigned int i2s13_drv_pads[]        = { I2S_BCLK1, I2S_LRCLK1,
0804                             I2S_MCLK1 };
0805 /* paddrv0_3_2 */
0806 static unsigned int pcm1_drv_pads[]     = { PCM1_IN, PCM1_CLK,
0807                             PCM1_SYNC, PCM1_OUT };
0808 /* paddrv0_1_0 */
0809 static unsigned int ks_in_drv_pads[]        = { KS_IN0, KS_IN1,
0810                             KS_IN2, KS_IN3 };
0811 /* paddrv1_31_30 */
0812 static unsigned int ks_out_drv_pads[]       = { KS_OUT0, KS_OUT1, KS_OUT2 };
0813 /* paddrv1_29_28 */
0814 static unsigned int lvds_all_drv_pads[]     = { LVDS_OEP, LVDS_OEN,
0815                             LVDS_ODP, LVDS_ODN,
0816                             LVDS_OCP, LVDS_OCN,
0817                             LVDS_OBP, LVDS_OBN,
0818                             LVDS_OAP, LVDS_OAN,
0819                             LVDS_EEP, LVDS_EEN,
0820                             LVDS_EDP, LVDS_EDN,
0821                             LVDS_ECP, LVDS_ECN,
0822                             LVDS_EBP, LVDS_EBN,
0823                             LVDS_EAP, LVDS_EAN };
0824 /* paddrv1_27_26 */
0825 static unsigned int lcd_dsi_drv_pads[]      = { DSI_DP3, DSI_DN3, DSI_DP1,
0826                             DSI_DN1, DSI_CP, DSI_CN };
0827 /* paddrv1_25_24 */
0828 static unsigned int dsi_drv_pads[]      = { DSI_DP0, DSI_DN0,
0829                             DSI_DP2, DSI_DN2 };
0830 /* paddrv1_23_22 */
0831 static unsigned int sd0_d0_d3_drv_pads[]    = { SD0_D0, SD0_D1,
0832                             SD0_D2, SD0_D3 };
0833 /* paddrv1_21_20 */
0834 static unsigned int sd1_d0_d3_drv_pads[]    = { SD1_D0, SD1_D1,
0835                             SD1_D2, SD1_D3 };
0836 /* paddrv1_19_18 */
0837 static unsigned int sd0_cmd_drv_pads[]      = { SD0_CMD };
0838 /* paddrv1_17_16 */
0839 static unsigned int sd0_clk_drv_pads[]      = { SD0_CLK };
0840 /* paddrv1_15_14 */
0841 static unsigned int sd1_cmd_drv_pads[]      = { SD1_CMD };
0842 /* paddrv1_13_12 */
0843 static unsigned int sd1_clk_drv_pads[]      = { SD1_CLK };
0844 /* paddrv1_11_10 */
0845 static unsigned int spi0_all_drv_pads[]     = { SPI0_SCLK, SPI0_SS,
0846                             SPI0_MISO, SPI0_MOSI };
0847 /* paddrv2_31_30 */
0848 static unsigned int uart0_rx_drv_pads[]     = { UART0_RX };
0849 /* paddrv2_29_28 */
0850 static unsigned int uart0_tx_drv_pads[]     = { UART0_TX };
0851 /* paddrv2_27_26 */
0852 static unsigned int uart2_all_drv_pads[]    = { UART2_RX, UART2_TX,
0853                             UART2_RTSB, UART2_CTSB };
0854 /* paddrv2_24_23 */
0855 static unsigned int i2c0_all_drv_pads[]     = { I2C0_SCLK, I2C0_SDATA };
0856 /* paddrv2_22_21 */
0857 static unsigned int i2c12_all_drv_pads[]    = { I2C1_SCLK, I2C1_SDATA,
0858                             I2C2_SCLK, I2C2_SDATA };
0859 /* paddrv2_19_18 */
0860 static unsigned int sens0_pclk_drv_pads[]   = { SENSOR0_PCLK };
0861 /* paddrv2_13_12 */
0862 static unsigned int sens0_ckout_drv_pads[]  = { SENSOR0_CKOUT };
0863 /* paddrv2_3_2 */
0864 static unsigned int uart3_all_drv_pads[]    = { UART3_RX, UART3_TX,
0865                             UART3_RTSB, UART3_CTSB };
0866 
0867 /* Pinctrl groups */
0868 static const struct owl_pingroup s500_groups[] = {
0869     MUX_PG(lcd0_d18_mfp, 0, 23, 3),
0870     MUX_PG(rmii_crs_dv_mfp, 0, 20, 3),
0871     MUX_PG(rmii_txd0_mfp, 0, 16, 3),
0872     MUX_PG(rmii_txd1_mfp, 0, 16, 3),
0873     MUX_PG(rmii_txen_mfp, 0, 13, 3),
0874     MUX_PG(rmii_rxen_mfp, 0, 13, 3),
0875     MUX_PG(rmii_rxd1_mfp, 0, 8, 3),
0876     MUX_PG(rmii_rxd0_mfp, 0, 8, 3),
0877     MUX_PG(rmii_ref_clk_mfp, 0, 6, 2),
0878     MUX_PG(i2s_d0_mfp, 0, 5, 1),
0879     MUX_PG(i2s_pcm1_mfp, 0, 3, 2),
0880     MUX_PG(i2s0_pcm0_mfp, 0, 1, 2),
0881     MUX_PG(i2s1_pcm0_mfp, 0, 1, 2),
0882     MUX_PG(i2s_d1_mfp, 0, 0, 1),
0883     MUX_PG(ks_in2_mfp, 1, 29, 3),
0884     MUX_PG(ks_in1_mfp, 1, 29, 3),
0885     MUX_PG(ks_in0_mfp, 1, 29, 3),
0886     MUX_PG(ks_in3_mfp, 1, 26, 3),
0887     MUX_PG(ks_out0_mfp, 1, 26, 3),
0888     MUX_PG(ks_out1_mfp, 1, 26, 3),
0889     MUX_PG(ks_out2_mfp, 1, 23, 3),
0890     MUX_PG(lvds_o_pn_mfp, 1, 21, 2),
0891     MUX_PG(dsi_dn0_mfp, 1, 19, 2),
0892     MUX_PG(dsi_dp2_mfp, 1, 17, 2),
0893     MUX_PG(lcd0_d17_mfp, 1, 14, 3),
0894     MUX_PG(dsi_dp3_mfp, 1, 12, 2),
0895     MUX_PG(dsi_dn3_mfp, 1, 10, 2),
0896     MUX_PG(dsi_dp0_mfp, 1, 7, 3),
0897     MUX_PG(lvds_ee_pn_mfp, 1, 5, 2),
0898     MUX_PG(spi0_i2c_pcm_mfp, 1, 3, 2),
0899     MUX_PG(spi0_i2s_pcm_mfp, 1, 0, 3),
0900     MUX_PG(dsi_dnp1_cp_mfp, 2, 29, 2),
0901     MUX_PG(lvds_e_pn_mfp, 2, 27, 2),
0902     MUX_PG(dsi_dn2_mfp, 2, 24, 3),
0903     MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
0904     MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
0905     MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
0906     MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
0907     MUX_PG(sd0_d0_mfp, 2, 17, 3),
0908     MUX_PG(sd0_d1_mfp, 2, 14, 3),
0909     MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
0910     MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
0911     MUX_PG(sd0_cmd_mfp, 2, 7, 2),
0912     MUX_PG(sd0_clk_mfp, 2, 5, 2),
0913     MUX_PG(sd1_cmd_mfp, 2, 3, 2),
0914     MUX_PG(uart0_rx_mfp, 2, 0, 3),
0915     MUX_PG(clko_25m_mfp, 3, 30, 1),
0916     MUX_PG(csi_cn_cp_mfp, 3, 28, 2),
0917     MUX_PG(sens0_ckout_mfp, 3, 22, 2),
0918     MUX_PG(uart0_tx_mfp, 3, 19, 3),
0919     MUX_PG(i2c0_mfp, 3, 16, 3),
0920     MUX_PG(csi_dn_dp_mfp, 3, 14, 2),
0921     MUX_PG(sen0_pclk_mfp, 3, 12, 2),
0922     MUX_PG(pcm1_in_mfp, 3, 10, 2),
0923     MUX_PG(pcm1_clk_mfp, 3, 8, 2),
0924     MUX_PG(pcm1_sync_mfp, 3, 6, 2),
0925     MUX_PG(pcm1_out_mfp, 3, 4, 2),
0926     MUX_PG(dnand_data_wr_mfp, 3, 3, 1),
0927     MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1),
0928     MUX_PG(nand_ceb2_mfp, 3, 0, 2),
0929     MUX_PG(nand_ceb3_mfp, 3, 0, 2),
0930 
0931     DRV_PG(sirq_drv, 0, 28, 2),
0932     DRV_PG(rmii_txd01_txen_drv, 0, 22, 2),
0933     DRV_PG(rmii_rxer_drv, 0, 20, 2),
0934     DRV_PG(rmii_crs_drv, 0, 18, 2),
0935     DRV_PG(rmii_rxd10_drv, 0, 16, 2),
0936     DRV_PG(rmii_ref_clk_drv, 0, 14, 2),
0937     DRV_PG(smi_mdc_mdio_drv, 0, 12, 2),
0938     DRV_PG(i2s_d0_drv, 0, 10, 2),
0939     DRV_PG(i2s_bclk0_drv, 0, 8, 2),
0940     DRV_PG(i2s3_drv, 0, 6, 2),
0941     DRV_PG(i2s13_drv, 0, 4, 2),
0942     DRV_PG(pcm1_drv, 0, 2, 2),
0943     DRV_PG(ks_in_drv, 0, 0, 2),
0944     DRV_PG(ks_out_drv, 1, 30, 2),
0945     DRV_PG(lvds_all_drv, 1, 28, 2),
0946     DRV_PG(lcd_dsi_drv, 1, 26, 2),
0947     DRV_PG(dsi_drv, 1, 24, 2),
0948     DRV_PG(sd0_d0_d3_drv, 1, 22, 2),
0949     DRV_PG(sd1_d0_d3_drv, 1, 20, 2),
0950     DRV_PG(sd0_cmd_drv, 1, 18, 2),
0951     DRV_PG(sd0_clk_drv, 1, 16, 2),
0952     DRV_PG(sd1_cmd_drv, 1, 14, 2),
0953     DRV_PG(sd1_clk_drv, 1, 12, 2),
0954     DRV_PG(spi0_all_drv, 1, 10, 2),
0955     DRV_PG(uart0_rx_drv, 2, 30, 2),
0956     DRV_PG(uart0_tx_drv, 2, 28, 2),
0957     DRV_PG(uart2_all_drv, 2, 26, 2),
0958     DRV_PG(i2c0_all_drv, 2, 23, 2),
0959     DRV_PG(i2c12_all_drv, 2, 21, 2),
0960     DRV_PG(sens0_pclk_drv, 2, 18, 2),
0961     DRV_PG(sens0_ckout_drv, 2, 12, 2),
0962     DRV_PG(uart3_all_drv, 2, 2, 2),
0963 };
0964 
0965 static const char * const nor_groups[] = {
0966     "lcd0_d18_mfp",
0967     "i2s_d0_mfp",
0968     "i2s0_pcm0_mfp",
0969     "i2s1_pcm0_mfp",
0970     "i2s_d1_mfp",
0971     "ks_in2_mfp",
0972     "ks_in1_mfp",
0973     "ks_in0_mfp",
0974     "ks_in3_mfp",
0975     "ks_out0_mfp",
0976     "ks_out1_mfp",
0977     "ks_out2_mfp",
0978     "lcd0_d17_mfp",
0979     "lvds_ee_pn_mfp",
0980     "spi0_i2c_pcm_mfp",
0981     "spi0_i2s_pcm_mfp",
0982     "lvds_e_pn_mfp",
0983     "sd0_d0_mfp",
0984     "sd0_d1_mfp",
0985     "sd0_d2_d3_mfp",
0986     "sd1_d0_d3_mfp",
0987     "sd0_cmd_mfp",
0988     "sd1_cmd_mfp",
0989     "sens0_ckout_mfp",
0990     "sen0_pclk_mfp",
0991 };
0992 
0993 static const char * const eth_rmii_groups[] = {
0994     "rmii_crs_dv_mfp",
0995     "rmii_txd0_mfp",
0996     "rmii_txd1_mfp",
0997     "rmii_txen_mfp",
0998     "rmii_rxen_mfp",
0999     "rmii_rxd1_mfp",
1000     "rmii_rxd0_mfp",
1001     "rmii_ref_clk_mfp",
1002 };
1003 
1004 static const char * const eth_smii_groups[] = {
1005     "rmii_crs_dv_mfp",
1006     "rmii_txd0_mfp",
1007     "rmii_txd1_mfp",
1008     "rmii_ref_clk_mfp",
1009 };
1010 
1011 static const char * const spi0_groups[] = {
1012     "dsi_dn0_mfp",
1013     "dsi_dp2_mfp",
1014     "dsi_dp0_mfp",
1015     "spi0_i2c_pcm_mfp",
1016     "spi0_i2s_pcm_mfp",
1017     "dsi_dn2_mfp",
1018 };
1019 
1020 static const char * const spi1_groups[] = {
1021     "uart0_rx_mfp",
1022     "uart0_tx_mfp",
1023     "i2c0_mfp",
1024 };
1025 
1026 static const char * const spi2_groups[] = {
1027     "rmii_crs_dv_mfp",
1028     "rmii_txd0_mfp",
1029     "rmii_txd1_mfp",
1030     "rmii_ref_clk_mfp",
1031     "dnand_acle_ce0_mfp",
1032 };
1033 
1034 static const char * const spi3_groups[] = {
1035     "rmii_txen_mfp",
1036     "rmii_rxen_mfp",
1037     "rmii_rxd1_mfp",
1038     "rmii_rxd0_mfp",
1039 };
1040 
1041 static const char * const sens0_groups[] = {
1042     "csi_cn_cp_mfp",
1043     "sens0_ckout_mfp",
1044     "csi_dn_dp_mfp",
1045     "sen0_pclk_mfp",
1046 };
1047 
1048 static const char * const sens1_groups[] = {
1049     "lcd0_d18_mfp",
1050     "ks_in2_mfp",
1051     "ks_in1_mfp",
1052     "ks_in0_mfp",
1053     "ks_in3_mfp",
1054     "ks_out0_mfp",
1055     "ks_out1_mfp",
1056     "ks_out2_mfp",
1057     "sens0_ckout_mfp",
1058     "pcm1_in_mfp",
1059     "pcm1_clk_mfp",
1060     "pcm1_sync_mfp",
1061     "pcm1_out_mfp",
1062 };
1063 
1064 static const char * const uart0_groups[] = {
1065     "uart2_rtsb_mfp",
1066     "uart2_ctsb_mfp",
1067     "uart0_rx_mfp",
1068     "uart0_tx_mfp",
1069 };
1070 
1071 static const char * const uart1_groups[] = {
1072     "sd0_d2_d3_mfp",
1073     "i2c0_mfp",
1074 };
1075 
1076 static const char * const uart2_groups[] = {
1077     "rmii_txen_mfp",
1078     "rmii_rxen_mfp",
1079     "rmii_rxd1_mfp",
1080     "rmii_rxd0_mfp",
1081     "dsi_dn0_mfp",
1082     "dsi_dp2_mfp",
1083     "dsi_dp0_mfp",
1084     "dsi_dn2_mfp",
1085     "uart2_rtsb_mfp",
1086     "uart2_ctsb_mfp",
1087     "sd0_d0_mfp",
1088     "sd0_d1_mfp",
1089     "sd0_d2_d3_mfp",
1090     "uart0_rx_mfp",
1091     "uart0_tx_mfp",
1092     "i2c0_mfp",
1093 };
1094 
1095 static const char * const uart3_groups[] = {
1096     "uart3_rtsb_mfp",
1097     "uart3_ctsb_mfp",
1098 };
1099 
1100 static const char * const uart4_groups[] = {
1101     "rmii_crs_dv_mfp",
1102     "rmii_ref_clk_mfp",
1103     "pcm1_in_mfp",
1104     "pcm1_clk_mfp",
1105 };
1106 
1107 static const char * const uart5_groups[] = {
1108     "rmii_rxd1_mfp",
1109     "rmii_rxd0_mfp",
1110     "ks_out0_mfp",
1111     "ks_out2_mfp",
1112     "uart3_rtsb_mfp",
1113     "uart3_ctsb_mfp",
1114     "sd0_d0_mfp",
1115     "sd0_d1_mfp",
1116 };
1117 
1118 static const char * const uart6_groups[] = {
1119     "rmii_txd0_mfp",
1120     "rmii_txd1_mfp",
1121     "pcm1_sync_mfp",
1122     "pcm1_out_mfp",
1123 };
1124 
1125 static const char * const i2s0_groups[] = {
1126     "i2s_d0_mfp",
1127     "i2s_pcm1_mfp",
1128     "i2s0_pcm0_mfp",
1129 };
1130 
1131 static const char * const i2s1_groups[] = {
1132     "i2s1_pcm0_mfp",
1133     "i2s_d1_mfp",
1134     "spi0_i2s_pcm_mfp",
1135     "uart0_rx_mfp",
1136     "uart0_tx_mfp",
1137 };
1138 
1139 static const char * const pcm1_groups[] = {
1140     "i2s_pcm1_mfp",
1141     "spi0_i2s_pcm_mfp",
1142     "uart0_rx_mfp",
1143     "uart0_tx_mfp",
1144     "pcm1_in_mfp",
1145     "pcm1_clk_mfp",
1146     "pcm1_sync_mfp",
1147     "pcm1_out_mfp",
1148 };
1149 
1150 static const char * const pcm0_groups[] = {
1151     "i2s0_pcm0_mfp",
1152     "i2s1_pcm0_mfp",
1153     "spi0_i2c_pcm_mfp",
1154     "spi0_i2s_pcm_mfp",
1155 };
1156 
1157 static const char * const ks_groups[] = {
1158     "ks_in2_mfp",
1159     "ks_in1_mfp",
1160     "ks_in0_mfp",
1161     "ks_in3_mfp",
1162     "ks_out0_mfp",
1163     "ks_out1_mfp",
1164     "ks_out2_mfp",
1165 };
1166 
1167 static const char * const jtag_groups[] = {
1168     "ks_in2_mfp",
1169     "ks_in1_mfp",
1170     "ks_in0_mfp",
1171     "ks_in3_mfp",
1172     "ks_out1_mfp",
1173     "sd0_d0_mfp",
1174     "sd0_d2_d3_mfp",
1175     "sd0_cmd_mfp",
1176     "sd0_clk_mfp",
1177 };
1178 
1179 static const char * const pwm0_groups[] = {
1180     "ks_in2_mfp",
1181     "ks_in0_mfp",
1182     "rmii_txen_mfp",
1183     "sen0_pclk_mfp",
1184 };
1185 
1186 static const char * const pwm1_groups[] = {
1187     "rmii_rxen_mfp",
1188     "ks_in1_mfp",
1189     "ks_in3_mfp",
1190     "sens0_ckout_mfp",
1191 };
1192 
1193 static const char * const pwm2_groups[] = {
1194     "lcd0_d18_mfp",
1195     "rmii_rxd1_mfp",
1196     "ks_out0_mfp",
1197     "ks_out2_mfp",
1198 };
1199 
1200 static const char * const pwm3_groups[] = {
1201     "rmii_rxd0_mfp",
1202     "ks_out1_mfp",
1203     "lcd0_d17_mfp",
1204 };
1205 
1206 static const char * const pwm4_groups[] = {
1207     "lcd0_d18_mfp",
1208     "rmii_crs_dv_mfp",
1209     "rmii_txd0_mfp",
1210     "ks_in0_mfp",
1211     "pcm1_in_mfp",
1212     "nand_ceb3_mfp",
1213 };
1214 
1215 static const char * const pwm5_groups[] = {
1216     "rmii_txd1_mfp",
1217     "ks_in1_mfp",
1218     "pcm1_clk_mfp",
1219     "nand_ceb2_mfp",
1220 };
1221 
1222 static const char * const p0_groups[] = {
1223     "ks_in2_mfp",
1224     "ks_in0_mfp",
1225 };
1226 
1227 static const char * const sd0_groups[] = {
1228     "ks_out0_mfp",
1229     "ks_out1_mfp",
1230     "ks_out2_mfp",
1231     "lcd0_d17_mfp",
1232     "dsi_dp3_mfp",
1233     "dsi_dp0_mfp",
1234     "sd0_d0_mfp",
1235     "sd0_d1_mfp",
1236     "sd0_d2_d3_mfp",
1237     "sd1_d0_d3_mfp",
1238     "sd0_cmd_mfp",
1239     "sd0_clk_mfp",
1240 };
1241 
1242 static const char * const sd1_groups[] = {
1243     "dsi_dp2_mfp",
1244     "lcd0_d17_mfp",
1245     "dsi_dp3_mfp",
1246     "dsi_dn3_mfp",
1247     "dsi_dnp1_cp_mfp",
1248     "dsi_dn2_mfp",
1249     "sd1_d0_d3_mfp",
1250     "sd1_cmd_mfp",
1251 };
1252 
1253 static const char * const sd2_groups[] = {
1254     "dnand_data_wr_mfp",
1255 };
1256 
1257 static const char * const i2c0_groups[] = {
1258     "uart0_rx_mfp",
1259     "uart0_tx_mfp",
1260     "i2c0_mfp",
1261 };
1262 
1263 static const char * const i2c1_groups[] = {
1264     "i2c0_mfp",
1265 };
1266 
1267 static const char * const i2c3_groups[] = {
1268     "spi0_i2c_pcm_mfp",
1269     "pcm1_sync_mfp",
1270     "pcm1_out_mfp",
1271 };
1272 
1273 static const char * const lvds_groups[] = {
1274     "lvds_o_pn_mfp",
1275     "lvds_ee_pn_mfp",
1276     "lvds_e_pn_mfp",
1277 };
1278 
1279 static const char * const ts_groups[] = {
1280     "lvds_o_pn_mfp",
1281     "lvds_ee_pn_mfp",
1282 };
1283 
1284 static const char * const lcd0_groups[] = {
1285     "lcd0_d18_mfp",
1286     "lcd0_d17_mfp",
1287     "lvds_o_pn_mfp",
1288     "dsi_dp3_mfp",
1289     "dsi_dn3_mfp",
1290     "lvds_ee_pn_mfp",
1291     "dsi_dnp1_cp_mfp",
1292     "lvds_e_pn_mfp",
1293 };
1294 
1295 static const char * const usb30_groups[] = {
1296     "ks_in1_mfp",
1297 };
1298 
1299 static const char * const clko_25m_groups[] = {
1300     "clko_25m_mfp",
1301 };
1302 
1303 static const char * const mipi_csi_groups[] = {
1304     "csi_cn_cp_mfp",
1305     "csi_dn_dp_mfp",
1306 };
1307 
1308 static const char * const dsi_groups[] = {
1309     "dsi_dn0_mfp",
1310     "dsi_dp2_mfp",
1311     "dsi_dp3_mfp",
1312     "dsi_dn3_mfp",
1313     "dsi_dp0_mfp",
1314     "dsi_dnp1_cp_mfp",
1315     "dsi_dn2_mfp",
1316 };
1317 
1318 static const char * const nand_groups[] = {
1319     "dnand_data_wr_mfp",
1320     "dnand_acle_ce0_mfp",
1321     "nand_ceb2_mfp",
1322     "nand_ceb3_mfp",
1323 };
1324 
1325 static const char * const spdif_groups[] = {
1326     "uart0_tx_mfp",
1327 };
1328 
1329 static const struct owl_pinmux_func s500_functions[] = {
1330     [S500_MUX_NOR] = FUNCTION(nor),
1331     [S500_MUX_ETH_RMII] = FUNCTION(eth_rmii),
1332     [S500_MUX_ETH_SMII] = FUNCTION(eth_smii),
1333     [S500_MUX_SPI0] = FUNCTION(spi0),
1334     [S500_MUX_SPI1] = FUNCTION(spi1),
1335     [S500_MUX_SPI2] = FUNCTION(spi2),
1336     [S500_MUX_SPI3] = FUNCTION(spi3),
1337     [S500_MUX_SENS0] = FUNCTION(sens0),
1338     [S500_MUX_SENS1] = FUNCTION(sens1),
1339     [S500_MUX_UART0] = FUNCTION(uart0),
1340     [S500_MUX_UART1] = FUNCTION(uart1),
1341     [S500_MUX_UART2] = FUNCTION(uart2),
1342     [S500_MUX_UART3] = FUNCTION(uart3),
1343     [S500_MUX_UART4] = FUNCTION(uart4),
1344     [S500_MUX_UART5] = FUNCTION(uart5),
1345     [S500_MUX_UART6] = FUNCTION(uart6),
1346     [S500_MUX_I2S0] = FUNCTION(i2s0),
1347     [S500_MUX_I2S1] = FUNCTION(i2s1),
1348     [S500_MUX_PCM1] = FUNCTION(pcm1),
1349     [S500_MUX_PCM0] = FUNCTION(pcm0),
1350     [S500_MUX_KS] = FUNCTION(ks),
1351     [S500_MUX_JTAG] = FUNCTION(jtag),
1352     [S500_MUX_PWM0] = FUNCTION(pwm0),
1353     [S500_MUX_PWM1] = FUNCTION(pwm1),
1354     [S500_MUX_PWM2] = FUNCTION(pwm2),
1355     [S500_MUX_PWM3] = FUNCTION(pwm3),
1356     [S500_MUX_PWM4] = FUNCTION(pwm4),
1357     [S500_MUX_PWM5] = FUNCTION(pwm5),
1358     [S500_MUX_P0] = FUNCTION(p0),
1359     [S500_MUX_SD0] = FUNCTION(sd0),
1360     [S500_MUX_SD1] = FUNCTION(sd1),
1361     [S500_MUX_SD2] = FUNCTION(sd2),
1362     [S500_MUX_I2C0] = FUNCTION(i2c0),
1363     [S500_MUX_I2C1] = FUNCTION(i2c1),
1364     /*[S500_MUX_I2C2] = FUNCTION(i2c2),*/
1365     [S500_MUX_I2C3] = FUNCTION(i2c3),
1366     [S500_MUX_DSI] = FUNCTION(dsi),
1367     [S500_MUX_LVDS] = FUNCTION(lvds),
1368     [S500_MUX_USB30] = FUNCTION(usb30),
1369     [S500_MUX_CLKO_25M] = FUNCTION(clko_25m),
1370     [S500_MUX_MIPI_CSI] = FUNCTION(mipi_csi),
1371     [S500_MUX_NAND] = FUNCTION(nand),
1372     [S500_MUX_SPDIF] = FUNCTION(spdif),
1373     /*[S500_MUX_SIRQ0] = FUNCTION(sirq0),*/
1374     /*[S500_MUX_SIRQ1] = FUNCTION(sirq1),*/
1375     /*[S500_MUX_SIRQ2] = FUNCTION(sirq2),*/
1376     [S500_MUX_TS] = FUNCTION(ts),
1377     [S500_MUX_LCD0] = FUNCTION(lcd0),
1378 };
1379 
1380 /* PAD_ST0 */
1381 static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
1382 static PAD_ST_CONF(UART0_RX, 0, 29, 1);
1383 static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
1384 static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
1385 static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
1386 static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
1387 static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
1388 static PAD_ST_CONF(DSI_DP0, 0, 16, 1);
1389 static PAD_ST_CONF(DSI_DN0, 0, 15, 1);
1390 static PAD_ST_CONF(UART0_TX, 0, 14, 1);
1391 static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);
1392 static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
1393 static PAD_ST_CONF(KS_IN0, 0, 11, 1);
1394 static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1);
1395 static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
1396 static PAD_ST_CONF(KS_OUT0, 0, 6, 1);
1397 static PAD_ST_CONF(KS_OUT1, 0, 5, 1);
1398 static PAD_ST_CONF(KS_OUT2, 0, 4, 1);
1399 
1400 /* PAD_ST1 */
1401 static PAD_ST_CONF(DSI_DP2, 1, 31, 1);
1402 static PAD_ST_CONF(DSI_DN2, 1, 30, 1);
1403 static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
1404 static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
1405 static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
1406 static PAD_ST_CONF(UART3_RX, 1, 25, 1);
1407 static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
1408 static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
1409 static PAD_ST_CONF(UART2_RX, 1, 22, 1);
1410 static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
1411 static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
1412 static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
1413 static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
1414 static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
1415 static PAD_ST_CONF(LVDS_OAP, 1, 12, 1);
1416 static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
1417 static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
1418 static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
1419 static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
1420 static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
1421 static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
1422 static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
1423 static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);
1424 static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
1425 static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
1426 static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
1427 static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
1428 
1429 /* PAD_PULLCTL0 */
1430 static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1);
1431 static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1);
1432 static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1);
1433 static PAD_PULLCTL_CONF(LCD0_D17, 0, 27, 1);
1434 static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1);
1435 static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1);
1436 static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2);
1437 static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2);
1438 static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2);
1439 static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1);
1440 static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1);
1441 static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1);
1442 static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1);
1443 static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1);
1444 static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1);
1445 static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1);
1446 static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1);
1447 static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1);
1448 
1449 /* PAD_PULLCTL1 */
1450 static PAD_PULLCTL_CONF(DSI_CP, 1, 31, 1);
1451 static PAD_PULLCTL_CONF(DSI_CN, 1, 30, 1);
1452 static PAD_PULLCTL_CONF(DSI_DN2, 1, 28, 1);
1453 static PAD_PULLCTL_CONF(DNAND_RDBN, 1, 25, 1);
1454 static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1);
1455 static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1);
1456 static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1);
1457 static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1);
1458 static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1);
1459 static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1);
1460 static PAD_PULLCTL_CONF(SD1_CMD, 1, 11, 1);
1461 static PAD_PULLCTL_CONF(SD1_D0, 1, 6, 1);
1462 static PAD_PULLCTL_CONF(SD1_D1, 1, 5, 1);
1463 static PAD_PULLCTL_CONF(SD1_D2, 1, 4, 1);
1464 static PAD_PULLCTL_CONF(SD1_D3, 1, 3, 1);
1465 static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1);
1466 static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1);
1467 static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1);
1468 
1469 /* PAD_PULLCTL2 */
1470 static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 12, 1);
1471 static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 11, 1);
1472 static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1);
1473 static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1);
1474 static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);
1475 static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);
1476 static PAD_PULLCTL_CONF(DNAND_DQSN, 2, 5, 2);
1477 static PAD_PULLCTL_CONF(DNAND_DQS, 2, 3, 2);
1478 static PAD_PULLCTL_CONF(DNAND_D0, 2, 2, 1);
1479 static PAD_PULLCTL_CONF(DNAND_D1, 2, 2, 1);
1480 static PAD_PULLCTL_CONF(DNAND_D2, 2, 2, 1);
1481 static PAD_PULLCTL_CONF(DNAND_D3, 2, 2, 1);
1482 static PAD_PULLCTL_CONF(DNAND_D4, 2, 2, 1);
1483 static PAD_PULLCTL_CONF(DNAND_D5, 2, 2, 1);
1484 static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1);
1485 static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1);
1486 
1487 /* Pad info table */
1488 static const struct owl_padinfo s500_padinfo[NUM_PADS] = {
1489     [DNAND_DQS] = PAD_INFO_PULLCTL(DNAND_DQS),
1490     [DNAND_DQSN] = PAD_INFO_PULLCTL(DNAND_DQSN),
1491     [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
1492     [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
1493     [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
1494     [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
1495     [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
1496     [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
1497     [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
1498     [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
1499     [ETH_MDC] = PAD_INFO(ETH_MDC),
1500     [ETH_MDIO] = PAD_INFO(ETH_MDIO),
1501     [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
1502     [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
1503     [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
1504     [I2S_D0] = PAD_INFO(I2S_D0),
1505     [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
1506     [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
1507     [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
1508     [I2S_D1] = PAD_INFO(I2S_D1),
1509     [I2S_BCLK1] = PAD_INFO(I2S_BCLK1),
1510     [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
1511     [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
1512     [KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0),
1513     [KS_IN1] = PAD_INFO_PULLCTL(KS_IN1),
1514     [KS_IN2] = PAD_INFO_PULLCTL(KS_IN2),
1515     [KS_IN3] = PAD_INFO_PULLCTL(KS_IN3),
1516     [KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0),
1517     [KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1),
1518     [KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2),
1519     [LVDS_OEP] = PAD_INFO(LVDS_OEP),
1520     [LVDS_OEN] = PAD_INFO(LVDS_OEN),
1521     [LVDS_ODP] = PAD_INFO(LVDS_ODP),
1522     [LVDS_ODN] = PAD_INFO(LVDS_ODN),
1523     [LVDS_OCP] = PAD_INFO(LVDS_OCP),
1524     [LVDS_OCN] = PAD_INFO(LVDS_OCN),
1525     [LVDS_OBP] = PAD_INFO(LVDS_OBP),
1526     [LVDS_OBN] = PAD_INFO(LVDS_OBN),
1527     [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
1528     [LVDS_OAN] = PAD_INFO(LVDS_OAN),
1529     [LVDS_EEP] = PAD_INFO(LVDS_EEP),
1530     [LVDS_EEN] = PAD_INFO(LVDS_EEN),
1531     [LVDS_EDP] = PAD_INFO(LVDS_EDP),
1532     [LVDS_EDN] = PAD_INFO(LVDS_EDN),
1533     [LVDS_ECP] = PAD_INFO(LVDS_ECP),
1534     [LVDS_ECN] = PAD_INFO(LVDS_ECN),
1535     [LVDS_EBP] = PAD_INFO(LVDS_EBP),
1536     [LVDS_EBN] = PAD_INFO(LVDS_EBN),
1537     [LVDS_EAP] = PAD_INFO(LVDS_EAP),
1538     [LVDS_EAN] = PAD_INFO(LVDS_EAN),
1539     [LCD0_D18] = PAD_INFO(LCD0_D18),
1540     [LCD0_D17] = PAD_INFO_PULLCTL(LCD0_D17),
1541     [DSI_DP3] = PAD_INFO(DSI_DP3),
1542     [DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3),
1543     [DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1),
1544     [DSI_DN1] = PAD_INFO(DSI_DN1),
1545     [DSI_CP] = PAD_INFO_PULLCTL(DSI_CP),
1546     [DSI_CN] = PAD_INFO_PULLCTL(DSI_CN),
1547     [DSI_DP0] = PAD_INFO_ST(DSI_DP0),
1548     [DSI_DN0] = PAD_INFO_ST(DSI_DN0),
1549     [DSI_DP2] = PAD_INFO_ST(DSI_DP2),
1550     [DSI_DN2] = PAD_INFO_PULLCTL_ST(DSI_DN2),
1551     [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
1552     [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
1553     [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
1554     [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
1555     [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0),
1556     [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1),
1557     [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2),
1558     [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3),
1559     [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
1560     [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
1561     [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD),
1562     [SD1_CLK] = PAD_INFO(SD1_CLK),
1563     [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK),
1564     [SPI0_SS] = PAD_INFO_ST(SPI0_SS),
1565     [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO),
1566     [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI),
1567     [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
1568     [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
1569     [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
1570     [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
1571     [SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK),
1572     [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
1573     [DNAND_ALE] = PAD_INFO(DNAND_ALE),
1574     [DNAND_CLE] = PAD_INFO(DNAND_CLE),
1575     [DNAND_CEB0] = PAD_INFO(DNAND_CEB0),
1576     [DNAND_CEB1] = PAD_INFO(DNAND_CEB1),
1577     [DNAND_CEB2] = PAD_INFO(DNAND_CEB2),
1578     [DNAND_CEB3] = PAD_INFO(DNAND_CEB3),
1579     [UART2_RX] = PAD_INFO_ST(UART2_RX),
1580     [UART2_TX] = PAD_INFO(UART2_TX),
1581     [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
1582     [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
1583     [UART3_RX] = PAD_INFO_ST(UART3_RX),
1584     [UART3_TX] = PAD_INFO(UART3_TX),
1585     [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
1586     [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
1587     [PCM1_IN] = PAD_INFO_ST(PCM1_IN),
1588     [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
1589     [PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC),
1590     [PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT),
1591     [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
1592     [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
1593     [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
1594     [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
1595     [CSI_DN0] = PAD_INFO(CSI_DN0),
1596     [CSI_DP0] = PAD_INFO(CSI_DP0),
1597     [CSI_DN1] = PAD_INFO(CSI_DN1),
1598     [CSI_DP1] = PAD_INFO(CSI_DP1),
1599     [CSI_CN] = PAD_INFO(CSI_CN),
1600     [CSI_CP] = PAD_INFO(CSI_CP),
1601     [CSI_DN2] = PAD_INFO(CSI_DN2),
1602     [CSI_DP2] = PAD_INFO(CSI_DP2),
1603     [CSI_DN3] = PAD_INFO(CSI_DN3),
1604     [CSI_DP3] = PAD_INFO(CSI_DP3),
1605     [DNAND_D0] = PAD_INFO_PULLCTL(DNAND_D0),
1606     [DNAND_D1] = PAD_INFO_PULLCTL(DNAND_D1),
1607     [DNAND_D2] = PAD_INFO_PULLCTL(DNAND_D2),
1608     [DNAND_D3] = PAD_INFO_PULLCTL(DNAND_D3),
1609     [DNAND_D4] = PAD_INFO_PULLCTL(DNAND_D4),
1610     [DNAND_D5] = PAD_INFO_PULLCTL(DNAND_D5),
1611     [DNAND_D6] = PAD_INFO_PULLCTL(DNAND_D6),
1612     [DNAND_D7] = PAD_INFO_PULLCTL(DNAND_D7),
1613     [DNAND_WRB] = PAD_INFO(DNAND_WRB),
1614     [DNAND_RDB] = PAD_INFO(DNAND_RDB),
1615     [DNAND_RDBN] = PAD_INFO_PULLCTL(DNAND_RDBN),
1616     [DNAND_RB] = PAD_INFO(DNAND_RB),
1617     [PORB] = PAD_INFO(PORB),
1618     [CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M),
1619     [BSEL] = PAD_INFO(BSEL),
1620     [PKG0] = PAD_INFO(PKG0),
1621     [PKG1] = PAD_INFO(PKG1),
1622     [PKG2] = PAD_INFO(PKG2),
1623     [PKG3] = PAD_INFO(PKG3),
1624 };
1625 
1626 static const struct owl_gpio_port s500_gpio_ports[] = {
1627     OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0),
1628     OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x1F8, 0x204, 0x208, 0x22C, 1),
1629     OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x1EC, 0x200, 0x204, 0x228, 2),
1630     OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x1E0, 0x1FC, 0x200, 0x224, 3),
1631     OWL_GPIO_PORT(E, 0x0030,  4, 0x0, 0x4, 0x8, 0x1D4, 0x1F8, 0x1FC, 0x220, 4),
1632 };
1633 
1634 enum s500_pinconf_pull {
1635     OWL_PINCONF_PULL_DOWN,
1636     OWL_PINCONF_PULL_UP,
1637 };
1638 
1639 static int s500_pad_pinconf_arg2val(const struct owl_padinfo *info,
1640                     unsigned int param, u32 *arg)
1641 {
1642     switch (param) {
1643     case PIN_CONFIG_BIAS_PULL_DOWN:
1644         *arg = OWL_PINCONF_PULL_DOWN;
1645         break;
1646     case PIN_CONFIG_BIAS_PULL_UP:
1647         *arg = OWL_PINCONF_PULL_UP;
1648         break;
1649     case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1650         *arg = (*arg >= 1 ? 1 : 0);
1651         break;
1652     default:
1653         return -EOPNOTSUPP;
1654     }
1655 
1656     return 0;
1657 }
1658 
1659 static int s500_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
1660                     unsigned int param, u32 *arg)
1661 {
1662     switch (param) {
1663     case PIN_CONFIG_BIAS_PULL_DOWN:
1664         *arg = *arg == OWL_PINCONF_PULL_DOWN;
1665         break;
1666     case PIN_CONFIG_BIAS_PULL_UP:
1667         *arg = *arg == OWL_PINCONF_PULL_UP;
1668         break;
1669     case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1670         *arg = *arg == 1;
1671         break;
1672     default:
1673         return -EOPNOTSUPP;
1674     }
1675 
1676     return 0;
1677 }
1678 
1679 static struct owl_pinctrl_soc_data s500_pinctrl_data = {
1680     .padinfo = s500_padinfo,
1681     .pins = (const struct pinctrl_pin_desc *)s500_pads,
1682     .npins = ARRAY_SIZE(s500_pads),
1683     .functions = s500_functions,
1684     .nfunctions = ARRAY_SIZE(s500_functions),
1685     .groups = s500_groups,
1686     .ngroups = ARRAY_SIZE(s500_groups),
1687     .ngpios = NUM_GPIOS,
1688     .ports = s500_gpio_ports,
1689     .nports = ARRAY_SIZE(s500_gpio_ports),
1690     .padctl_arg2val = s500_pad_pinconf_arg2val,
1691     .padctl_val2arg = s500_pad_pinconf_val2arg,
1692 };
1693 
1694 static int s500_pinctrl_probe(struct platform_device *pdev)
1695 {
1696     return owl_pinctrl_probe(pdev, &s500_pinctrl_data);
1697 }
1698 
1699 static const struct of_device_id s500_pinctrl_of_match[] = {
1700     { .compatible = "actions,s500-pinctrl", },
1701     { }
1702 };
1703 
1704 static struct platform_driver s500_pinctrl_driver = {
1705     .driver = {
1706         .name = "pinctrl-s500",
1707         .of_match_table = of_match_ptr(s500_pinctrl_of_match),
1708     },
1709     .probe = s500_pinctrl_probe,
1710 };
1711 
1712 static int __init s500_pinctrl_init(void)
1713 {
1714     return platform_driver_register(&s500_pinctrl_driver);
1715 }
1716 arch_initcall(s500_pinctrl_init);
1717 
1718 static void __exit s500_pinctrl_exit(void)
1719 {
1720     platform_driver_unregister(&s500_pinctrl_driver);
1721 }
1722 module_exit(s500_pinctrl_exit);
1723 
1724 MODULE_AUTHOR("Actions Semi Inc.");
1725 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@gmail.com>");
1726 MODULE_DESCRIPTION("Actions Semi S500 SoC Pinctrl Driver");
1727 MODULE_LICENSE("GPL");
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