pinctrl/actions/pinctrl-owl.h

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * OWL SoC's Pinctrl definitions
0004  *
0005  * Copyright (c) 2014 Actions Semi Inc.
0006  * Author: David Liu <liuwei@actions-semi.com>
0007  *
0008  * Copyright (c) 2018 Linaro Ltd.
0009  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0010  */
0011
0012 #ifndef __PINCTRL_OWL_H__
0013 #define __PINCTRL_OWL_H__
0014
0015 #define OWL_PINCONF_SLEW_SLOW 0
0016 #define OWL_PINCONF_SLEW_FAST 1
0017
0018 #define MUX_PG(group_name, reg, shift, width)               \
0019     {                               \
0020         .name = #group_name,                    \
0021         .pads = group_name##_pads,              \
0022         .npads = ARRAY_SIZE(group_name##_pads),         \
0023         .funcs = group_name##_funcs,                \
0024         .nfuncs = ARRAY_SIZE(group_name##_funcs),       \
0025         .mfpctl_reg  = MFCTL##reg,              \
0026         .mfpctl_shift = shift,                  \
0027         .mfpctl_width = width,                  \
0028         .drv_reg = -1,                      \
0029         .drv_shift = -1,                    \
0030         .drv_width = -1,                    \
0031         .sr_reg = -1,                       \
0032         .sr_shift = -1,                     \
0033         .sr_width = -1,                     \
0034     }
0035
0036 #define DRV_PG(group_name, reg, shift, width)               \
0037     {                               \
0038         .name = #group_name,                    \
0039         .pads = group_name##_pads,              \
0040         .npads = ARRAY_SIZE(group_name##_pads),         \
0041         .mfpctl_reg  = -1,                  \
0042         .mfpctl_shift = -1,                 \
0043         .mfpctl_width = -1,                 \
0044         .drv_reg = PAD_DRV##reg,                \
0045         .drv_shift = shift,                 \
0046         .drv_width = width,                 \
0047         .sr_reg = -1,                       \
0048         .sr_shift = -1,                     \
0049         .sr_width = -1,                     \
0050     }
0051
0052 #define SR_PG(group_name, reg, shift, width)                \
0053     {                               \
0054         .name = #group_name,                    \
0055         .pads = group_name##_pads,              \
0056         .npads = ARRAY_SIZE(group_name##_pads),         \
0057         .mfpctl_reg  = -1,                  \
0058         .mfpctl_shift = -1,                 \
0059         .mfpctl_width = -1,                 \
0060         .drv_reg = -1,                      \
0061         .drv_shift = -1,                    \
0062         .drv_width = -1,                    \
0063         .sr_reg = PAD_SR##reg,                  \
0064         .sr_shift = shift,                  \
0065         .sr_width = width,                  \
0066     }
0067
0068 #define FUNCTION(fname)                 \
0069     {                       \
0070         .name = #fname,             \
0071         .groups = fname##_groups,       \
0072         .ngroups = ARRAY_SIZE(fname##_groups),  \
0073     }
0074
0075 /* PAD PULL UP/DOWN CONFIGURES */
0076 #define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)  \
0077     {                       \
0078         .reg = PAD_PULLCTL##pull_reg,       \
0079         .shift = pull_sft,          \
0080         .width = pull_wdt,          \
0081     }
0082
0083 #define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt)    \
0084     struct owl_pullctl pad_name##_pullctl_conf          \
0085         = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
0086
0087 #define ST_CONF(st_reg, st_sft, st_wdt)         \
0088     {                       \
0089         .reg = PAD_ST##st_reg,          \
0090         .shift = st_sft,            \
0091         .width = st_wdt,            \
0092     }
0093
0094 #define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt)   \
0095     struct owl_st pad_name##_st_conf        \
0096         = ST_CONF(st_reg, st_sft, st_wdt)
0097
0098 #define PAD_INFO(name)                  \
0099     {                       \
0100         .pad = name,                \
0101         .pullctl = NULL,            \
0102         .st = NULL,             \
0103     }
0104
0105 #define PAD_INFO_ST(name)               \
0106     {                       \
0107         .pad = name,                \
0108         .pullctl = NULL,            \
0109         .st = &name##_st_conf,          \
0110     }
0111
0112 #define PAD_INFO_PULLCTL(name)              \
0113     {                       \
0114         .pad = name,                \
0115         .pullctl = &name##_pullctl_conf,    \
0116         .st = NULL,             \
0117     }
0118
0119 #define PAD_INFO_PULLCTL_ST(name)           \
0120     {                       \
0121         .pad = name,                \
0122         .pullctl = &name##_pullctl_conf,    \
0123         .st = &name##_st_conf,          \
0124     }
0125
0126 #define OWL_GPIO_PORT_A     0
0127 #define OWL_GPIO_PORT_B     1
0128 #define OWL_GPIO_PORT_C     2
0129 #define OWL_GPIO_PORT_D     3
0130 #define OWL_GPIO_PORT_E     4
0131 #define OWL_GPIO_PORT_F     5
0132
0133 #define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\
0134             _intc_pd, _intc_msk, _intc_type, _share)    \
0135     [OWL_GPIO_PORT_##port] = {              \
0136         .offset = base,                 \
0137         .pins = count,                  \
0138         .outen = _outen,                \
0139         .inen = _inen,                  \
0140         .dat = _dat,                    \
0141         .intc_ctl = _intc_ctl,              \
0142         .intc_pd = _intc_pd,                \
0143         .intc_msk = _intc_msk,              \
0144         .intc_type = _intc_type,            \
0145         .shared_ctl_offset = _share,            \
0146     }
0147
0148 enum owl_pinconf_drv {
0149     OWL_PINCONF_DRV_2MA,
0150     OWL_PINCONF_DRV_4MA,
0151     OWL_PINCONF_DRV_8MA,
0152     OWL_PINCONF_DRV_12MA,
0153 };
0154
0155 /* GPIO CTRL Bit Definition */
0156 #define OWL_GPIO_CTLR_PENDING       0
0157 #define OWL_GPIO_CTLR_ENABLE        1
0158 #define OWL_GPIO_CTLR_SAMPLE_CLK_24M    2
0159
0160 /* GPIO TYPE Bit Definition */
0161 #define OWL_GPIO_INT_LEVEL_HIGH     0
0162 #define OWL_GPIO_INT_LEVEL_LOW      1
0163 #define OWL_GPIO_INT_EDGE_RISING    2
0164 #define OWL_GPIO_INT_EDGE_FALLING   3
0165 #define OWL_GPIO_INT_MASK       3
0166
0167 /**
0168  * struct owl_pullctl - Actions pad pull control register
0169  * @reg: offset to the pull control register
0170  * @shift: shift value of the register
0171  * @width: width of the register
0172  */
0173 struct owl_pullctl {
0174     int reg;
0175     unsigned int shift;
0176     unsigned int width;
0177 };
0178
0179 /**
0180  * struct owl_st - Actions pad schmitt trigger enable register
0181  * @reg: offset to the schmitt trigger enable register
0182  * @shift: shift value of the register
0183  * @width: width of the register
0184  */
0185 struct owl_st {
0186     int reg;
0187     unsigned int shift;
0188     unsigned int width;
0189 };
0190
0191 /**
0192  * struct owl_pingroup - Actions pingroup definition
0193  * @name: name of the  pin group
0194  * @pads: list of pins assigned to this pingroup
0195  * @npads: size of @pads array
0196  * @funcs: list of pinmux functions for this pingroup
0197  * @nfuncs: size of @funcs array
0198  * @mfpctl_reg: multiplexing control register offset
0199  * @mfpctl_shift: multiplexing control register bit mask
0200  * @mfpctl_width: multiplexing control register width
0201  * @drv_reg: drive control register offset
0202  * @drv_shift: drive control register bit mask
0203  * @drv_width: driver control register width
0204  * @sr_reg: slew rate control register offset
0205  * @sr_shift: slew rate control register bit mask
0206  * @sr_width: slew rate control register width
0207  */
0208 struct owl_pingroup {
0209     const char *name;
0210     unsigned int *pads;
0211     unsigned int npads;
0212     unsigned int *funcs;
0213     unsigned int nfuncs;
0214
0215     int mfpctl_reg;
0216     unsigned int mfpctl_shift;
0217     unsigned int mfpctl_width;
0218
0219     int drv_reg;
0220     unsigned int drv_shift;
0221     unsigned int drv_width;
0222
0223     int sr_reg;
0224     unsigned int sr_shift;
0225     unsigned int sr_width;
0226 };
0227
0228 /**
0229  * struct owl_padinfo - Actions pinctrl pad info
0230  * @pad: pad name of the SoC
0231  * @pullctl: pull control register info
0232  * @st: schmitt trigger register info
0233  */
0234 struct owl_padinfo {
0235     int pad;
0236     struct owl_pullctl *pullctl;
0237     struct owl_st *st;
0238 };
0239
0240 /**
0241  * struct owl_pinmux_func - Actions pinctrl mux functions
0242  * @name: name of the pinmux function.
0243  * @groups: array of pin groups that may select this function.
0244  * @ngroups: number of entries in @groups.
0245  */
0246 struct owl_pinmux_func {
0247     const char *name;
0248     const char * const *groups;
0249     unsigned int ngroups;
0250 };
0251
0252 /**
0253  * struct owl_gpio_port - Actions GPIO port info
0254  * @offset: offset of the GPIO port.
0255  * @pins: number of pins belongs to the GPIO port.
0256  * @outen: offset of the output enable register.
0257  * @inen: offset of the input enable register.
0258  * @dat: offset of the data register.
0259  * @intc_ctl: offset of the interrupt control register.
0260  * @intc_pd: offset of the interrupt pending register.
0261  * @intc_msk: offset of the interrupt mask register.
0262  * @intc_type: offset of the interrupt type register.
0263  */
0264 struct owl_gpio_port {
0265     unsigned int offset;
0266     unsigned int pins;
0267     unsigned int outen;
0268     unsigned int inen;
0269     unsigned int dat;
0270     unsigned int intc_ctl;
0271     unsigned int intc_pd;
0272     unsigned int intc_msk;
0273     unsigned int intc_type;
0274     u8 shared_ctl_offset;
0275 };
0276
0277 /**
0278  * struct owl_pinctrl_soc_data - Actions pin controller driver configuration
0279  * @pins: array describing all pins of the pin controller.
0280  * @npins: number of entries in @pins.
0281  * @functions: array describing all mux functions of this SoC.
0282  * @nfunction: number of entries in @functions.
0283  * @groups: array describing all pin groups of this SoC.
0284  * @ngroups: number of entries in @groups.
0285  * @padinfo: array describing the pad info of this SoC.
0286  * @ngpios: number of pingroups the driver should expose as GPIOs.
0287  * @ports: array describing all GPIO ports of this SoC.
0288  * @nports: number of GPIO ports in this SoC.
0289  */
0290 struct owl_pinctrl_soc_data {
0291     const struct pinctrl_pin_desc *pins;
0292     unsigned int npins;
0293     const struct owl_pinmux_func *functions;
0294     unsigned int nfunctions;
0295     const struct owl_pingroup *groups;
0296     unsigned int ngroups;
0297     const struct owl_padinfo *padinfo;
0298     unsigned int ngpios;
0299     const struct owl_gpio_port *ports;
0300     unsigned int nports;
0301     int (*padctl_val2arg)(const struct owl_padinfo *padinfo,
0302                 unsigned int param,
0303                 u32 *arg);
0304     int (*padctl_arg2val)(const struct owl_padinfo *info,
0305                 unsigned int param,
0306                 u32 *arg);
0307 };
0308
0309 int owl_pinctrl_probe(struct platform_device *pdev,
0310         struct owl_pinctrl_soc_data *soc_data);
0311
0312 #endif /* __PINCTRL_OWL_H__ */