Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * OWL SoC's Pinctrl driver
0004  *
0005  * Copyright (c) 2014 Actions Semi Inc.
0006  * Author: David Liu <liuwei@actions-semi.com>
0007  *
0008  * Copyright (c) 2018 Linaro Ltd.
0009  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/err.h>
0014 #include <linux/gpio/driver.h>
0015 #include <linux/io.h>
0016 #include <linux/irq.h>
0017 #include <linux/module.h>
0018 #include <linux/of.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/pinctrl/machine.h>
0021 #include <linux/pinctrl/pinctrl.h>
0022 #include <linux/pinctrl/pinmux.h>
0023 #include <linux/pinctrl/pinconf.h>
0024 #include <linux/pinctrl/pinconf-generic.h>
0025 #include <linux/slab.h>
0026 #include <linux/spinlock.h>
0027 
0028 #include "../core.h"
0029 #include "../pinctrl-utils.h"
0030 #include "pinctrl-owl.h"
0031 
0032 /**
0033  * struct owl_pinctrl - pinctrl state of the device
0034  * @dev: device handle
0035  * @pctrldev: pinctrl handle
0036  * @chip: gpio chip
0037  * @lock: spinlock to protect registers
0038  * @clk: clock control
0039  * @soc: reference to soc_data
0040  * @base: pinctrl register base address
0041  * @irq_chip: IRQ chip information
0042  * @num_irq: number of possible interrupts
0043  * @irq: interrupt numbers
0044  */
0045 struct owl_pinctrl {
0046     struct device *dev;
0047     struct pinctrl_dev *pctrldev;
0048     struct gpio_chip chip;
0049     raw_spinlock_t lock;
0050     struct clk *clk;
0051     const struct owl_pinctrl_soc_data *soc;
0052     void __iomem *base;
0053     struct irq_chip irq_chip;
0054     unsigned int num_irq;
0055     unsigned int *irq;
0056 };
0057 
0058 static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
0059 {
0060     u32 reg_val;
0061 
0062     reg_val = readl_relaxed(base);
0063 
0064     reg_val = (reg_val & ~mask) | (val & mask);
0065 
0066     writel_relaxed(reg_val, base);
0067 }
0068 
0069 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
0070                 u32 bit, u32 width)
0071 {
0072     u32 tmp, mask;
0073 
0074     tmp = readl_relaxed(pctrl->base + reg);
0075     mask = (1 << width) - 1;
0076 
0077     return (tmp >> bit) & mask;
0078 }
0079 
0080 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
0081                 u32 bit, u32 width)
0082 {
0083     u32 mask;
0084 
0085     mask = (1 << width) - 1;
0086     mask = mask << bit;
0087 
0088     owl_update_bits(pctrl->base + reg, mask, (arg << bit));
0089 }
0090 
0091 static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
0092 {
0093     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0094 
0095     return pctrl->soc->ngroups;
0096 }
0097 
0098 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
0099                 unsigned int group)
0100 {
0101     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0102 
0103     return pctrl->soc->groups[group].name;
0104 }
0105 
0106 static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
0107                 unsigned int group,
0108                 const unsigned int **pins,
0109                 unsigned int *num_pins)
0110 {
0111     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0112 
0113     *pins = pctrl->soc->groups[group].pads;
0114     *num_pins = pctrl->soc->groups[group].npads;
0115 
0116     return 0;
0117 }
0118 
0119 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
0120                 struct seq_file *s,
0121                 unsigned int offset)
0122 {
0123     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0124 
0125     seq_printf(s, "%s", dev_name(pctrl->dev));
0126 }
0127 
0128 static const struct pinctrl_ops owl_pinctrl_ops = {
0129     .get_groups_count = owl_get_groups_count,
0130     .get_group_name = owl_get_group_name,
0131     .get_group_pins = owl_get_group_pins,
0132     .pin_dbg_show = owl_pin_dbg_show,
0133     .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
0134     .dt_free_map = pinctrl_utils_free_map,
0135 };
0136 
0137 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
0138 {
0139     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0140 
0141     return pctrl->soc->nfunctions;
0142 }
0143 
0144 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
0145                 unsigned int function)
0146 {
0147     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0148 
0149     return pctrl->soc->functions[function].name;
0150 }
0151 
0152 static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
0153                 unsigned int function,
0154                 const char * const **groups,
0155                 unsigned int * const num_groups)
0156 {
0157     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0158 
0159     *groups = pctrl->soc->functions[function].groups;
0160     *num_groups = pctrl->soc->functions[function].ngroups;
0161 
0162     return 0;
0163 }
0164 
0165 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
0166                 int function,
0167                 u32 *mask,
0168                 u32 *val)
0169 {
0170     int id;
0171     u32 option_num;
0172     u32 option_mask;
0173 
0174     for (id = 0; id < g->nfuncs; id++) {
0175         if (g->funcs[id] == function)
0176             break;
0177     }
0178     if (WARN_ON(id == g->nfuncs))
0179         return -EINVAL;
0180 
0181     option_num = (1 << g->mfpctl_width);
0182     if (id > option_num)
0183         id -= option_num;
0184 
0185     option_mask = option_num - 1;
0186     *mask = (option_mask  << g->mfpctl_shift);
0187     *val = (id << g->mfpctl_shift);
0188 
0189     return 0;
0190 }
0191 
0192 static int owl_set_mux(struct pinctrl_dev *pctrldev,
0193                 unsigned int function,
0194                 unsigned int group)
0195 {
0196     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0197     const struct owl_pingroup *g;
0198     unsigned long flags;
0199     u32 val, mask;
0200 
0201     g = &pctrl->soc->groups[group];
0202 
0203     if (get_group_mfp_mask_val(g, function, &mask, &val))
0204         return -EINVAL;
0205 
0206     raw_spin_lock_irqsave(&pctrl->lock, flags);
0207 
0208     owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
0209 
0210     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0211 
0212     return 0;
0213 }
0214 
0215 static const struct pinmux_ops owl_pinmux_ops = {
0216     .get_functions_count = owl_get_funcs_count,
0217     .get_function_name = owl_get_func_name,
0218     .get_function_groups = owl_get_func_groups,
0219     .set_mux = owl_set_mux,
0220 };
0221 
0222 static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
0223                 unsigned int param,
0224                 u32 *reg,
0225                 u32 *bit,
0226                 u32 *width)
0227 {
0228     switch (param) {
0229     case PIN_CONFIG_BIAS_BUS_HOLD:
0230     case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0231     case PIN_CONFIG_BIAS_PULL_DOWN:
0232     case PIN_CONFIG_BIAS_PULL_UP:
0233         if (!info->pullctl)
0234             return -EINVAL;
0235         *reg = info->pullctl->reg;
0236         *bit = info->pullctl->shift;
0237         *width = info->pullctl->width;
0238         break;
0239     case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
0240         if (!info->st)
0241             return -EINVAL;
0242         *reg = info->st->reg;
0243         *bit = info->st->shift;
0244         *width = info->st->width;
0245         break;
0246     default:
0247         return -ENOTSUPP;
0248     }
0249 
0250     return 0;
0251 }
0252 
0253 static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
0254                 unsigned int pin,
0255                 unsigned long *config)
0256 {
0257     int ret = 0;
0258     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0259     const struct owl_padinfo *info;
0260     unsigned int param = pinconf_to_config_param(*config);
0261     u32 reg, bit, width, arg;
0262 
0263     info = &pctrl->soc->padinfo[pin];
0264 
0265     ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
0266     if (ret)
0267         return ret;
0268 
0269     arg = owl_read_field(pctrl, reg, bit, width);
0270 
0271     if (!pctrl->soc->padctl_val2arg)
0272         return -ENOTSUPP;
0273 
0274     ret = pctrl->soc->padctl_val2arg(info, param, &arg);
0275     if (ret)
0276         return ret;
0277 
0278     *config = pinconf_to_config_packed(param, arg);
0279 
0280     return ret;
0281 }
0282 
0283 static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
0284                 unsigned int pin,
0285                 unsigned long *configs,
0286                 unsigned int num_configs)
0287 {
0288     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0289     const struct owl_padinfo *info;
0290     unsigned long flags;
0291     unsigned int param;
0292     u32 reg, bit, width, arg;
0293     int ret = 0, i;
0294 
0295     info = &pctrl->soc->padinfo[pin];
0296 
0297     for (i = 0; i < num_configs; i++) {
0298         param = pinconf_to_config_param(configs[i]);
0299         arg = pinconf_to_config_argument(configs[i]);
0300 
0301         ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
0302         if (ret)
0303             return ret;
0304 
0305         if (!pctrl->soc->padctl_arg2val)
0306             return -ENOTSUPP;
0307 
0308         ret = pctrl->soc->padctl_arg2val(info, param, &arg);
0309         if (ret)
0310             return ret;
0311 
0312         raw_spin_lock_irqsave(&pctrl->lock, flags);
0313 
0314         owl_write_field(pctrl, reg, arg, bit, width);
0315 
0316         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0317     }
0318 
0319     return ret;
0320 }
0321 
0322 static int owl_group_pinconf_reg(const struct owl_pingroup *g,
0323                 unsigned int param,
0324                 u32 *reg,
0325                 u32 *bit,
0326                 u32 *width)
0327 {
0328     switch (param) {
0329     case PIN_CONFIG_DRIVE_STRENGTH:
0330         if (g->drv_reg < 0)
0331             return -EINVAL;
0332         *reg = g->drv_reg;
0333         *bit = g->drv_shift;
0334         *width = g->drv_width;
0335         break;
0336     case PIN_CONFIG_SLEW_RATE:
0337         if (g->sr_reg < 0)
0338             return -EINVAL;
0339         *reg = g->sr_reg;
0340         *bit = g->sr_shift;
0341         *width = g->sr_width;
0342         break;
0343     default:
0344         return -ENOTSUPP;
0345     }
0346 
0347     return 0;
0348 }
0349 
0350 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
0351                 unsigned int param,
0352                 u32 *arg)
0353 {
0354     switch (param) {
0355     case PIN_CONFIG_DRIVE_STRENGTH:
0356         switch (*arg) {
0357         case 2:
0358             *arg = OWL_PINCONF_DRV_2MA;
0359             break;
0360         case 4:
0361             *arg = OWL_PINCONF_DRV_4MA;
0362             break;
0363         case 8:
0364             *arg = OWL_PINCONF_DRV_8MA;
0365             break;
0366         case 12:
0367             *arg = OWL_PINCONF_DRV_12MA;
0368             break;
0369         default:
0370             return -EINVAL;
0371         }
0372         break;
0373     case PIN_CONFIG_SLEW_RATE:
0374         if (*arg)
0375             *arg = OWL_PINCONF_SLEW_FAST;
0376         else
0377             *arg = OWL_PINCONF_SLEW_SLOW;
0378         break;
0379     default:
0380         return -ENOTSUPP;
0381     }
0382 
0383     return 0;
0384 }
0385 
0386 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
0387                 unsigned int param,
0388                 u32 *arg)
0389 {
0390     switch (param) {
0391     case PIN_CONFIG_DRIVE_STRENGTH:
0392         switch (*arg) {
0393         case OWL_PINCONF_DRV_2MA:
0394             *arg = 2;
0395             break;
0396         case OWL_PINCONF_DRV_4MA:
0397             *arg = 4;
0398             break;
0399         case OWL_PINCONF_DRV_8MA:
0400             *arg = 8;
0401             break;
0402         case OWL_PINCONF_DRV_12MA:
0403             *arg = 12;
0404             break;
0405         default:
0406             return -EINVAL;
0407         }
0408         break;
0409     case PIN_CONFIG_SLEW_RATE:
0410         if (*arg)
0411             *arg = 1;
0412         else
0413             *arg = 0;
0414         break;
0415     default:
0416         return -ENOTSUPP;
0417     }
0418 
0419     return 0;
0420 }
0421 
0422 static int owl_group_config_get(struct pinctrl_dev *pctrldev,
0423                 unsigned int group,
0424                 unsigned long *config)
0425 {
0426     const struct owl_pingroup *g;
0427     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0428     unsigned int param = pinconf_to_config_param(*config);
0429     u32 reg, bit, width, arg;
0430     int ret;
0431 
0432     g = &pctrl->soc->groups[group];
0433 
0434     ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
0435     if (ret)
0436         return ret;
0437 
0438     arg = owl_read_field(pctrl, reg, bit, width);
0439 
0440     ret = owl_group_pinconf_val2arg(g, param, &arg);
0441     if (ret)
0442         return ret;
0443 
0444     *config = pinconf_to_config_packed(param, arg);
0445 
0446     return ret;
0447 }
0448 
0449 static int owl_group_config_set(struct pinctrl_dev *pctrldev,
0450                 unsigned int group,
0451                 unsigned long *configs,
0452                 unsigned int num_configs)
0453 {
0454     const struct owl_pingroup *g;
0455     struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
0456     unsigned long flags;
0457     unsigned int param;
0458     u32 reg, bit, width, arg;
0459     int ret, i;
0460 
0461     g = &pctrl->soc->groups[group];
0462 
0463     for (i = 0; i < num_configs; i++) {
0464         param = pinconf_to_config_param(configs[i]);
0465         arg = pinconf_to_config_argument(configs[i]);
0466 
0467         ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
0468         if (ret)
0469             return ret;
0470 
0471         ret = owl_group_pinconf_arg2val(g, param, &arg);
0472         if (ret)
0473             return ret;
0474 
0475         /* Update register */
0476         raw_spin_lock_irqsave(&pctrl->lock, flags);
0477 
0478         owl_write_field(pctrl, reg, arg, bit, width);
0479 
0480         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0481     }
0482 
0483     return 0;
0484 }
0485 
0486 static const struct pinconf_ops owl_pinconf_ops = {
0487     .is_generic = true,
0488     .pin_config_get = owl_pin_config_get,
0489     .pin_config_set = owl_pin_config_set,
0490     .pin_config_group_get = owl_group_config_get,
0491     .pin_config_group_set = owl_group_config_set,
0492 };
0493 
0494 static struct pinctrl_desc owl_pinctrl_desc = {
0495     .pctlops = &owl_pinctrl_ops,
0496     .pmxops = &owl_pinmux_ops,
0497     .confops = &owl_pinconf_ops,
0498     .owner = THIS_MODULE,
0499 };
0500 
0501 static const struct owl_gpio_port *
0502 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
0503 {
0504     unsigned int start = 0, i;
0505 
0506     for (i = 0; i < pctrl->soc->nports; i++) {
0507         const struct owl_gpio_port *port = &pctrl->soc->ports[i];
0508 
0509         if (*pin >= start && *pin < start + port->pins) {
0510             *pin -= start;
0511             return port;
0512         }
0513 
0514         start += port->pins;
0515     }
0516 
0517     return NULL;
0518 }
0519 
0520 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
0521 {
0522     u32 val;
0523 
0524     val = readl_relaxed(base);
0525 
0526     if (flag)
0527         val |= BIT(pin);
0528     else
0529         val &= ~BIT(pin);
0530 
0531     writel_relaxed(val, base);
0532 }
0533 
0534 static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
0535 {
0536     struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
0537     const struct owl_gpio_port *port;
0538     void __iomem *gpio_base;
0539     unsigned long flags;
0540 
0541     port = owl_gpio_get_port(pctrl, &offset);
0542     if (WARN_ON(port == NULL))
0543         return -ENODEV;
0544 
0545     gpio_base = pctrl->base + port->offset;
0546 
0547     /*
0548      * GPIOs have higher priority over other modules, so either setting
0549      * them as OUT or IN is sufficient
0550      */
0551     raw_spin_lock_irqsave(&pctrl->lock, flags);
0552     owl_gpio_update_reg(gpio_base + port->outen, offset, true);
0553     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0554 
0555     return 0;
0556 }
0557 
0558 static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
0559 {
0560     struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
0561     const struct owl_gpio_port *port;
0562     void __iomem *gpio_base;
0563     unsigned long flags;
0564 
0565     port = owl_gpio_get_port(pctrl, &offset);
0566     if (WARN_ON(port == NULL))
0567         return;
0568 
0569     gpio_base = pctrl->base + port->offset;
0570 
0571     raw_spin_lock_irqsave(&pctrl->lock, flags);
0572     /* disable gpio output */
0573     owl_gpio_update_reg(gpio_base + port->outen, offset, false);
0574 
0575     /* disable gpio input */
0576     owl_gpio_update_reg(gpio_base + port->inen, offset, false);
0577     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0578 }
0579 
0580 static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
0581 {
0582     struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
0583     const struct owl_gpio_port *port;
0584     void __iomem *gpio_base;
0585     unsigned long flags;
0586     u32 val;
0587 
0588     port = owl_gpio_get_port(pctrl, &offset);
0589     if (WARN_ON(port == NULL))
0590         return -ENODEV;
0591 
0592     gpio_base = pctrl->base + port->offset;
0593 
0594     raw_spin_lock_irqsave(&pctrl->lock, flags);
0595     val = readl_relaxed(gpio_base + port->dat);
0596     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0597 
0598     return !!(val & BIT(offset));
0599 }
0600 
0601 static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
0602 {
0603     struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
0604     const struct owl_gpio_port *port;
0605     void __iomem *gpio_base;
0606     unsigned long flags;
0607 
0608     port = owl_gpio_get_port(pctrl, &offset);
0609     if (WARN_ON(port == NULL))
0610         return;
0611 
0612     gpio_base = pctrl->base + port->offset;
0613 
0614     raw_spin_lock_irqsave(&pctrl->lock, flags);
0615     owl_gpio_update_reg(gpio_base + port->dat, offset, value);
0616     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0617 }
0618 
0619 static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
0620 {
0621     struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
0622     const struct owl_gpio_port *port;
0623     void __iomem *gpio_base;
0624     unsigned long flags;
0625 
0626     port = owl_gpio_get_port(pctrl, &offset);
0627     if (WARN_ON(port == NULL))
0628         return -ENODEV;
0629 
0630     gpio_base = pctrl->base + port->offset;
0631 
0632     raw_spin_lock_irqsave(&pctrl->lock, flags);
0633     owl_gpio_update_reg(gpio_base + port->outen, offset, false);
0634     owl_gpio_update_reg(gpio_base + port->inen, offset, true);
0635     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0636 
0637     return 0;
0638 }
0639 
0640 static int owl_gpio_direction_output(struct gpio_chip *chip,
0641                 unsigned int offset, int value)
0642 {
0643     struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
0644     const struct owl_gpio_port *port;
0645     void __iomem *gpio_base;
0646     unsigned long flags;
0647 
0648     port = owl_gpio_get_port(pctrl, &offset);
0649     if (WARN_ON(port == NULL))
0650         return -ENODEV;
0651 
0652     gpio_base = pctrl->base + port->offset;
0653 
0654     raw_spin_lock_irqsave(&pctrl->lock, flags);
0655     owl_gpio_update_reg(gpio_base + port->inen, offset, false);
0656     owl_gpio_update_reg(gpio_base + port->outen, offset, true);
0657     owl_gpio_update_reg(gpio_base + port->dat, offset, value);
0658     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0659 
0660     return 0;
0661 }
0662 
0663 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
0664 {
0665     const struct owl_gpio_port *port;
0666     void __iomem *gpio_base;
0667     unsigned long flags;
0668     unsigned int offset, value, irq_type = 0;
0669 
0670     switch (type) {
0671     case IRQ_TYPE_EDGE_BOTH:
0672         /*
0673          * Since the hardware doesn't support interrupts on both edges,
0674          * emulate it in the software by setting the single edge
0675          * interrupt and switching to the opposite edge while ACKing
0676          * the interrupt
0677          */
0678         if (owl_gpio_get(&pctrl->chip, gpio))
0679             irq_type = OWL_GPIO_INT_EDGE_FALLING;
0680         else
0681             irq_type = OWL_GPIO_INT_EDGE_RISING;
0682         break;
0683 
0684     case IRQ_TYPE_EDGE_RISING:
0685         irq_type = OWL_GPIO_INT_EDGE_RISING;
0686         break;
0687 
0688     case IRQ_TYPE_EDGE_FALLING:
0689         irq_type = OWL_GPIO_INT_EDGE_FALLING;
0690         break;
0691 
0692     case IRQ_TYPE_LEVEL_HIGH:
0693         irq_type = OWL_GPIO_INT_LEVEL_HIGH;
0694         break;
0695 
0696     case IRQ_TYPE_LEVEL_LOW:
0697         irq_type = OWL_GPIO_INT_LEVEL_LOW;
0698         break;
0699 
0700     default:
0701         break;
0702     }
0703 
0704     port = owl_gpio_get_port(pctrl, &gpio);
0705     if (WARN_ON(port == NULL))
0706         return;
0707 
0708     gpio_base = pctrl->base + port->offset;
0709 
0710     raw_spin_lock_irqsave(&pctrl->lock, flags);
0711 
0712     offset = (gpio < 16) ? 4 : 0;
0713     value = readl_relaxed(gpio_base + port->intc_type + offset);
0714     value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
0715     value |= irq_type << ((gpio % 16) * 2);
0716     writel_relaxed(value, gpio_base + port->intc_type + offset);
0717 
0718     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0719 }
0720 
0721 static void owl_gpio_irq_mask(struct irq_data *data)
0722 {
0723     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0724     struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
0725     const struct owl_gpio_port *port;
0726     void __iomem *gpio_base;
0727     unsigned long flags;
0728     unsigned int gpio = data->hwirq;
0729     u32 val;
0730 
0731     port = owl_gpio_get_port(pctrl, &gpio);
0732     if (WARN_ON(port == NULL))
0733         return;
0734 
0735     gpio_base = pctrl->base + port->offset;
0736 
0737     raw_spin_lock_irqsave(&pctrl->lock, flags);
0738 
0739     owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
0740 
0741     /* disable port interrupt if no interrupt pending bit is active */
0742     val = readl_relaxed(gpio_base + port->intc_msk);
0743     if (val == 0)
0744         owl_gpio_update_reg(gpio_base + port->intc_ctl,
0745                     OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
0746 
0747     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0748 }
0749 
0750 static void owl_gpio_irq_unmask(struct irq_data *data)
0751 {
0752     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0753     struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
0754     const struct owl_gpio_port *port;
0755     void __iomem *gpio_base;
0756     unsigned long flags;
0757     unsigned int gpio = data->hwirq;
0758     u32 value;
0759 
0760     port = owl_gpio_get_port(pctrl, &gpio);
0761     if (WARN_ON(port == NULL))
0762         return;
0763 
0764     gpio_base = pctrl->base + port->offset;
0765     raw_spin_lock_irqsave(&pctrl->lock, flags);
0766 
0767     /* enable port interrupt */
0768     value = readl_relaxed(gpio_base + port->intc_ctl);
0769     value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
0770             << port->shared_ctl_offset * 5);
0771     writel_relaxed(value, gpio_base + port->intc_ctl);
0772 
0773     /* enable GPIO interrupt */
0774     owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
0775 
0776     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0777 }
0778 
0779 static void owl_gpio_irq_ack(struct irq_data *data)
0780 {
0781     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0782     struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
0783     const struct owl_gpio_port *port;
0784     void __iomem *gpio_base;
0785     unsigned long flags;
0786     unsigned int gpio = data->hwirq;
0787 
0788     /*
0789      * Switch the interrupt edge to the opposite edge of the interrupt
0790      * which got triggered for the case of emulating both edges
0791      */
0792     if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
0793         if (owl_gpio_get(gc, gpio))
0794             irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
0795         else
0796             irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
0797     }
0798 
0799     port = owl_gpio_get_port(pctrl, &gpio);
0800     if (WARN_ON(port == NULL))
0801         return;
0802 
0803     gpio_base = pctrl->base + port->offset;
0804 
0805     raw_spin_lock_irqsave(&pctrl->lock, flags);
0806 
0807     owl_gpio_update_reg(gpio_base + port->intc_ctl,
0808                 OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
0809 
0810     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0811 }
0812 
0813 static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
0814 {
0815     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0816     struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
0817 
0818     if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
0819         irq_set_handler_locked(data, handle_level_irq);
0820     else
0821         irq_set_handler_locked(data, handle_edge_irq);
0822 
0823     irq_set_type(pctrl, data->hwirq, type);
0824 
0825     return 0;
0826 }
0827 
0828 static void owl_gpio_irq_handler(struct irq_desc *desc)
0829 {
0830     struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
0831     struct irq_chip *chip = irq_desc_get_chip(desc);
0832     struct irq_domain *domain = pctrl->chip.irq.domain;
0833     unsigned int parent = irq_desc_get_irq(desc);
0834     const struct owl_gpio_port *port;
0835     void __iomem *base;
0836     unsigned int pin, offset = 0, i;
0837     unsigned long pending_irq;
0838 
0839     chained_irq_enter(chip, desc);
0840 
0841     for (i = 0; i < pctrl->soc->nports; i++) {
0842         port = &pctrl->soc->ports[i];
0843         base = pctrl->base + port->offset;
0844 
0845         /* skip ports that are not associated with this irq */
0846         if (parent != pctrl->irq[i])
0847             goto skip;
0848 
0849         pending_irq = readl_relaxed(base + port->intc_pd);
0850 
0851         for_each_set_bit(pin, &pending_irq, port->pins) {
0852             generic_handle_domain_irq(domain, offset + pin);
0853 
0854             /* clear pending interrupt */
0855             owl_gpio_update_reg(base + port->intc_pd, pin, true);
0856         }
0857 
0858 skip:
0859         offset += port->pins;
0860     }
0861 
0862     chained_irq_exit(chip, desc);
0863 }
0864 
0865 static int owl_gpio_init(struct owl_pinctrl *pctrl)
0866 {
0867     struct gpio_chip *chip;
0868     struct gpio_irq_chip *gpio_irq;
0869     int ret, i, j, offset;
0870 
0871     chip = &pctrl->chip;
0872     chip->base = -1;
0873     chip->ngpio = pctrl->soc->ngpios;
0874     chip->label = dev_name(pctrl->dev);
0875     chip->parent = pctrl->dev;
0876     chip->owner = THIS_MODULE;
0877 
0878     pctrl->irq_chip.name = chip->of_node->name;
0879     pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
0880     pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
0881     pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
0882     pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
0883 
0884     gpio_irq = &chip->irq;
0885     gpio_irq->chip = &pctrl->irq_chip;
0886     gpio_irq->handler = handle_simple_irq;
0887     gpio_irq->default_type = IRQ_TYPE_NONE;
0888     gpio_irq->parent_handler = owl_gpio_irq_handler;
0889     gpio_irq->parent_handler_data = pctrl;
0890     gpio_irq->num_parents = pctrl->num_irq;
0891     gpio_irq->parents = pctrl->irq;
0892 
0893     gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
0894                 sizeof(*gpio_irq->map), GFP_KERNEL);
0895     if (!gpio_irq->map)
0896         return -ENOMEM;
0897 
0898     for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
0899         const struct owl_gpio_port *port = &pctrl->soc->ports[i];
0900 
0901         for (j = 0; j < port->pins; j++)
0902             gpio_irq->map[offset + j] = gpio_irq->parents[i];
0903 
0904         offset += port->pins;
0905     }
0906 
0907     ret = gpiochip_add_data(&pctrl->chip, pctrl);
0908     if (ret) {
0909         dev_err(pctrl->dev, "failed to register gpiochip\n");
0910         return ret;
0911     }
0912 
0913     return 0;
0914 }
0915 
0916 int owl_pinctrl_probe(struct platform_device *pdev,
0917                 struct owl_pinctrl_soc_data *soc_data)
0918 {
0919     struct owl_pinctrl *pctrl;
0920     int ret, i;
0921 
0922     pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
0923     if (!pctrl)
0924         return -ENOMEM;
0925 
0926     pctrl->base = devm_platform_ioremap_resource(pdev, 0);
0927     if (IS_ERR(pctrl->base))
0928         return PTR_ERR(pctrl->base);
0929 
0930     /* enable GPIO/MFP clock */
0931     pctrl->clk = devm_clk_get(&pdev->dev, NULL);
0932     if (IS_ERR(pctrl->clk)) {
0933         dev_err(&pdev->dev, "no clock defined\n");
0934         return PTR_ERR(pctrl->clk);
0935     }
0936 
0937     ret = clk_prepare_enable(pctrl->clk);
0938     if (ret) {
0939         dev_err(&pdev->dev, "clk enable failed\n");
0940         return ret;
0941     }
0942 
0943     raw_spin_lock_init(&pctrl->lock);
0944 
0945     owl_pinctrl_desc.name = dev_name(&pdev->dev);
0946     owl_pinctrl_desc.pins = soc_data->pins;
0947     owl_pinctrl_desc.npins = soc_data->npins;
0948 
0949     pctrl->chip.direction_input  = owl_gpio_direction_input;
0950     pctrl->chip.direction_output = owl_gpio_direction_output;
0951     pctrl->chip.get = owl_gpio_get;
0952     pctrl->chip.set = owl_gpio_set;
0953     pctrl->chip.request = owl_gpio_request;
0954     pctrl->chip.free = owl_gpio_free;
0955 
0956     pctrl->soc = soc_data;
0957     pctrl->dev = &pdev->dev;
0958 
0959     pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
0960                     &owl_pinctrl_desc, pctrl);
0961     if (IS_ERR(pctrl->pctrldev)) {
0962         dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
0963         ret = PTR_ERR(pctrl->pctrldev);
0964         goto err_exit;
0965     }
0966 
0967     ret = platform_irq_count(pdev);
0968     if (ret < 0)
0969         goto err_exit;
0970 
0971     pctrl->num_irq = ret;
0972 
0973     pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
0974                     sizeof(*pctrl->irq), GFP_KERNEL);
0975     if (!pctrl->irq) {
0976         ret = -ENOMEM;
0977         goto err_exit;
0978     }
0979 
0980     for (i = 0; i < pctrl->num_irq ; i++) {
0981         ret = platform_get_irq(pdev, i);
0982         if (ret < 0)
0983             goto err_exit;
0984         pctrl->irq[i] = ret;
0985     }
0986 
0987     ret = owl_gpio_init(pctrl);
0988     if (ret)
0989         goto err_exit;
0990 
0991     platform_set_drvdata(pdev, pctrl);
0992 
0993     return 0;
0994 
0995 err_exit:
0996     clk_disable_unprepare(pctrl->clk);
0997 
0998     return ret;
0999 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!