phy/ti/phy-omap-control.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * omap-control-phy.c - The PHY part of control module.
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
0006  * Author: Kishon Vijay Abraham I <kishon@ti.com>
0007  */
0008
0009 #include <linux/module.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/slab.h>
0012 #include <linux/of.h>
0013 #include <linux/of_device.h>
0014 #include <linux/err.h>
0015 #include <linux/io.h>
0016 #include <linux/clk.h>
0017 #include <linux/phy/omap_control_phy.h>
0018
0019 /**
0020  * omap_control_pcie_pcs - set the PCS delay count
0021  * @dev: the control module device
0022  * @delay: 8 bit delay value
0023  */
0024 void omap_control_pcie_pcs(struct device *dev, u8 delay)
0025 {
0026     u32 val;
0027     struct omap_control_phy *control_phy;
0028
0029     if (IS_ERR_OR_NULL(dev)) {
0030         pr_err("%s: invalid device\n", __func__);
0031         return;
0032     }
0033
0034     control_phy = dev_get_drvdata(dev);
0035     if (!control_phy) {
0036         dev_err(dev, "%s: invalid control phy device\n", __func__);
0037         return;
0038     }
0039
0040     if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
0041         dev_err(dev, "%s: unsupported operation\n", __func__);
0042         return;
0043     }
0044
0045     val = readl(control_phy->pcie_pcs);
0046     val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
0047         OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
0048     val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
0049     writel(val, control_phy->pcie_pcs);
0050 }
0051 EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
0052
0053 /**
0054  * omap_control_phy_power - power on/off the phy using control module reg
0055  * @dev: the control module device
0056  * @on: 0 or 1, based on powering on or off the PHY
0057  */
0058 void omap_control_phy_power(struct device *dev, int on)
0059 {
0060     u32 val;
0061     unsigned long rate;
0062     struct omap_control_phy *control_phy;
0063
0064     if (IS_ERR_OR_NULL(dev)) {
0065         pr_err("%s: invalid device\n", __func__);
0066         return;
0067     }
0068
0069     control_phy = dev_get_drvdata(dev);
0070     if (!control_phy) {
0071         dev_err(dev, "%s: invalid control phy device\n", __func__);
0072         return;
0073     }
0074
0075     if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
0076         return;
0077
0078     val = readl(control_phy->power);
0079
0080     switch (control_phy->type) {
0081     case OMAP_CTRL_TYPE_USB2:
0082         if (on)
0083             val &= ~OMAP_CTRL_DEV_PHY_PD;
0084         else
0085             val |= OMAP_CTRL_DEV_PHY_PD;
0086         break;
0087
0088     case OMAP_CTRL_TYPE_PCIE:
0089     case OMAP_CTRL_TYPE_PIPE3:
0090         rate = clk_get_rate(control_phy->sys_clk);
0091         rate = rate/1000000;
0092
0093         if (on) {
0094             val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
0095                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
0096             val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
0097                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
0098             val |= rate <<
0099                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
0100         } else {
0101             val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
0102             val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
0103                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
0104         }
0105         break;
0106
0107     case OMAP_CTRL_TYPE_DRA7USB2:
0108         if (on)
0109             val &= ~OMAP_CTRL_USB2_PHY_PD;
0110         else
0111             val |= OMAP_CTRL_USB2_PHY_PD;
0112         break;
0113
0114     case OMAP_CTRL_TYPE_AM437USB2:
0115         if (on) {
0116             val &= ~(AM437X_CTRL_USB2_PHY_PD |
0117                     AM437X_CTRL_USB2_OTG_PD);
0118             val |= (AM437X_CTRL_USB2_OTGVDET_EN |
0119                     AM437X_CTRL_USB2_OTGSESSEND_EN);
0120         } else {
0121             val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
0122                     AM437X_CTRL_USB2_OTGSESSEND_EN);
0123             val |= (AM437X_CTRL_USB2_PHY_PD |
0124                      AM437X_CTRL_USB2_OTG_PD);
0125         }
0126         break;
0127     default:
0128         dev_err(dev, "%s: type %d not recognized\n",
0129             __func__, control_phy->type);
0130         break;
0131     }
0132
0133     writel(val, control_phy->power);
0134 }
0135 EXPORT_SYMBOL_GPL(omap_control_phy_power);
0136
0137 /**
0138  * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
0139  * @ctrl_phy: struct omap_control_phy *
0140  *
0141  * Writes to the mailbox register to notify the usb core that a usb
0142  * device has been connected.
0143  */
0144 static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
0145 {
0146     u32 val;
0147
0148     val = readl(ctrl_phy->otghs_control);
0149     val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
0150     val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
0151     writel(val, ctrl_phy->otghs_control);
0152 }
0153
0154 /**
0155  * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
0156  * impedance
0157  * @ctrl_phy: struct omap_control_phy *
0158  *
0159  * Writes to the mailbox register to notify the usb core that it has been
0160  * connected to a usb host.
0161  */
0162 static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
0163 {
0164     u32 val;
0165
0166     val = readl(ctrl_phy->otghs_control);
0167     val &= ~OMAP_CTRL_DEV_SESSEND;
0168     val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
0169         OMAP_CTRL_DEV_VBUSVALID;
0170     writel(val, ctrl_phy->otghs_control);
0171 }
0172
0173 /**
0174  * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
0175  * impedance
0176  * @ctrl_phy: struct omap_control_phy *
0177  *
0178  * Writes to the mailbox register to notify the usb core it's now in
0179  * disconnected state.
0180  */
0181 static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
0182 {
0183     u32 val;
0184
0185     val = readl(ctrl_phy->otghs_control);
0186     val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
0187     val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
0188     writel(val, ctrl_phy->otghs_control);
0189 }
0190
0191 /**
0192  * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
0193  * or device mode or to denote disconnected state
0194  * @dev: the control module device
0195  * @mode: The mode to which usb should be configured
0196  *
0197  * This is an API to write to the mailbox register to notify the usb core that
0198  * a usb device has been connected.
0199  */
0200 void omap_control_usb_set_mode(struct device *dev,
0201     enum omap_control_usb_mode mode)
0202 {
0203     struct omap_control_phy *ctrl_phy;
0204
0205     if (IS_ERR_OR_NULL(dev))
0206         return;
0207
0208     ctrl_phy = dev_get_drvdata(dev);
0209     if (!ctrl_phy) {
0210         dev_err(dev, "Invalid control phy device\n");
0211         return;
0212     }
0213
0214     if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
0215         return;
0216
0217     switch (mode) {
0218     case USB_MODE_HOST:
0219         omap_control_usb_host_mode(ctrl_phy);
0220         break;
0221     case USB_MODE_DEVICE:
0222         omap_control_usb_device_mode(ctrl_phy);
0223         break;
0224     case USB_MODE_DISCONNECT:
0225         omap_control_usb_set_sessionend(ctrl_phy);
0226         break;
0227     default:
0228         dev_vdbg(dev, "invalid omap control usb mode\n");
0229     }
0230 }
0231 EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
0232
0233 static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
0234 static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
0235 static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
0236 static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
0237 static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
0238 static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;
0239
0240 static const struct of_device_id omap_control_phy_id_table[] = {
0241     {
0242         .compatible = "ti,control-phy-otghs",
0243         .data = &otghs_data,
0244     },
0245     {
0246         .compatible = "ti,control-phy-usb2",
0247         .data = &usb2_data,
0248     },
0249     {
0250         .compatible = "ti,control-phy-pipe3",
0251         .data = &pipe3_data,
0252     },
0253     {
0254         .compatible = "ti,control-phy-pcie",
0255         .data = &pcie_data,
0256     },
0257     {
0258         .compatible = "ti,control-phy-usb2-dra7",
0259         .data = &dra7usb2_data,
0260     },
0261     {
0262         .compatible = "ti,control-phy-usb2-am437",
0263         .data = &am437usb2_data,
0264     },
0265     {},
0266 };
0267 MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
0268
0269 static int omap_control_phy_probe(struct platform_device *pdev)
0270 {
0271     const struct of_device_id *of_id;
0272     struct omap_control_phy *control_phy;
0273
0274     of_id = of_match_device(omap_control_phy_id_table, &pdev->dev);
0275     if (!of_id)
0276         return -EINVAL;
0277
0278     control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
0279         GFP_KERNEL);
0280     if (!control_phy)
0281         return -ENOMEM;
0282
0283     control_phy->dev = &pdev->dev;
0284     control_phy->type = *(enum omap_control_phy_type *)of_id->data;
0285
0286     if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
0287         control_phy->otghs_control =
0288             devm_platform_ioremap_resource_byname(pdev, "otghs_control");
0289         if (IS_ERR(control_phy->otghs_control))
0290             return PTR_ERR(control_phy->otghs_control);
0291     } else {
0292         control_phy->power =
0293             devm_platform_ioremap_resource_byname(pdev, "power");
0294         if (IS_ERR(control_phy->power)) {
0295             dev_err(&pdev->dev, "Couldn't get power register\n");
0296             return PTR_ERR(control_phy->power);
0297         }
0298     }
0299
0300     if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 ||
0301         control_phy->type == OMAP_CTRL_TYPE_PCIE) {
0302         control_phy->sys_clk = devm_clk_get(control_phy->dev,
0303             "sys_clkin");
0304         if (IS_ERR(control_phy->sys_clk)) {
0305             pr_err("%s: unable to get sys_clkin\n", __func__);
0306             return -EINVAL;
0307         }
0308     }
0309
0310     if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
0311         control_phy->pcie_pcs =
0312             devm_platform_ioremap_resource_byname(pdev, "pcie_pcs");
0313         if (IS_ERR(control_phy->pcie_pcs))
0314             return PTR_ERR(control_phy->pcie_pcs);
0315     }
0316
0317     dev_set_drvdata(control_phy->dev, control_phy);
0318
0319     return 0;
0320 }
0321
0322 static struct platform_driver omap_control_phy_driver = {
0323     .probe      = omap_control_phy_probe,
0324     .driver     = {
0325         .name   = "omap-control-phy",
0326         .of_match_table = omap_control_phy_id_table,
0327     },
0328 };
0329
0330 static int __init omap_control_phy_init(void)
0331 {
0332     return platform_driver_register(&omap_control_phy_driver);
0333 }
0334 subsys_initcall(omap_control_phy_init);
0335
0336 static void __exit omap_control_phy_exit(void)
0337 {
0338     platform_driver_unregister(&omap_control_phy_driver);
0339 }
0340 module_exit(omap_control_phy_exit);
0341
0342 MODULE_ALIAS("platform:omap_control_phy");
0343 MODULE_AUTHOR("Texas Instruments Inc.");
0344 MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
0345 MODULE_LICENSE("GPL v2");