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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Wrapper driver for SERDES used in J721E
0004  *
0005  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
0006  * Author: Kishon Vijay Abraham I <kishon@ti.com>
0007  */
0008 
0009 #include <dt-bindings/phy/phy.h>
0010 #include <dt-bindings/phy/phy-ti.h>
0011 #include <linux/slab.h>
0012 #include <linux/clk.h>
0013 #include <linux/clk-provider.h>
0014 #include <linux/gpio.h>
0015 #include <linux/gpio/consumer.h>
0016 #include <linux/io.h>
0017 #include <linux/module.h>
0018 #include <linux/mux/consumer.h>
0019 #include <linux/of_address.h>
0020 #include <linux/of_platform.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/regmap.h>
0024 #include <linux/reset-controller.h>
0025 
0026 #define WIZ_SERDES_CTRL     0x404
0027 #define WIZ_SERDES_TOP_CTRL 0x408
0028 #define WIZ_SERDES_RST      0x40c
0029 #define WIZ_SERDES_TYPEC    0x410
0030 #define WIZ_LANECTL(n)      (0x480 + (0x40 * (n)))
0031 #define WIZ_LANEDIV(n)      (0x484 + (0x40 * (n)))
0032 
0033 #define WIZ_MAX_INPUT_CLOCKS    4
0034 /* To include mux clocks, divider clocks and gate clocks */
0035 #define WIZ_MAX_OUTPUT_CLOCKS   32
0036 
0037 #define WIZ_MAX_LANES       4
0038 #define WIZ_MUX_NUM_CLOCKS  3
0039 #define WIZ_DIV_NUM_CLOCKS_16G  2
0040 #define WIZ_DIV_NUM_CLOCKS_10G  1
0041 
0042 #define WIZ_SERDES_TYPEC_LN10_SWAP  BIT(30)
0043 
0044 enum wiz_lane_standard_mode {
0045     LANE_MODE_GEN1,
0046     LANE_MODE_GEN2,
0047     LANE_MODE_GEN3,
0048     LANE_MODE_GEN4,
0049 };
0050 
0051 enum wiz_refclk_mux_sel {
0052     PLL0_REFCLK,
0053     PLL1_REFCLK,
0054     REFCLK_DIG,
0055 };
0056 
0057 enum wiz_refclk_div_sel {
0058     CMN_REFCLK_DIG_DIV,
0059     CMN_REFCLK1_DIG_DIV,
0060 };
0061 
0062 enum wiz_clock_input {
0063     WIZ_CORE_REFCLK,
0064     WIZ_EXT_REFCLK,
0065     WIZ_CORE_REFCLK1,
0066     WIZ_EXT_REFCLK1,
0067 };
0068 
0069 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
0070 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
0071 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30);
0072 static const struct reg_field pll1_refclk_mux_sel =
0073                     REG_FIELD(WIZ_SERDES_RST, 29, 29);
0074 static const struct reg_field pll0_refclk_mux_sel =
0075                     REG_FIELD(WIZ_SERDES_RST, 28, 28);
0076 static const struct reg_field refclk_dig_sel_16g =
0077                     REG_FIELD(WIZ_SERDES_RST, 24, 25);
0078 static const struct reg_field refclk_dig_sel_10g =
0079                     REG_FIELD(WIZ_SERDES_RST, 24, 24);
0080 static const struct reg_field pma_cmn_refclk_int_mode =
0081                     REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
0082 static const struct reg_field pma_cmn_refclk_mode =
0083                     REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
0084 static const struct reg_field pma_cmn_refclk_dig_div =
0085                     REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
0086 static const struct reg_field pma_cmn_refclk1_dig_div =
0087                     REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
0088 static const char * const output_clk_names[] = {
0089     [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
0090     [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
0091     [TI_WIZ_REFCLK_DIG] = "refclk-dig",
0092     [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
0093 };
0094 
0095 static const struct reg_field p_enable[WIZ_MAX_LANES] = {
0096     REG_FIELD(WIZ_LANECTL(0), 30, 31),
0097     REG_FIELD(WIZ_LANECTL(1), 30, 31),
0098     REG_FIELD(WIZ_LANECTL(2), 30, 31),
0099     REG_FIELD(WIZ_LANECTL(3), 30, 31),
0100 };
0101 
0102 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
0103 
0104 static const struct reg_field p_align[WIZ_MAX_LANES] = {
0105     REG_FIELD(WIZ_LANECTL(0), 29, 29),
0106     REG_FIELD(WIZ_LANECTL(1), 29, 29),
0107     REG_FIELD(WIZ_LANECTL(2), 29, 29),
0108     REG_FIELD(WIZ_LANECTL(3), 29, 29),
0109 };
0110 
0111 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
0112     REG_FIELD(WIZ_LANECTL(0), 28, 28),
0113     REG_FIELD(WIZ_LANECTL(1), 28, 28),
0114     REG_FIELD(WIZ_LANECTL(2), 28, 28),
0115     REG_FIELD(WIZ_LANECTL(3), 28, 28),
0116 };
0117 
0118 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
0119     REG_FIELD(WIZ_LANECTL(0), 24, 25),
0120     REG_FIELD(WIZ_LANECTL(1), 24, 25),
0121     REG_FIELD(WIZ_LANECTL(2), 24, 25),
0122     REG_FIELD(WIZ_LANECTL(3), 24, 25),
0123 };
0124 
0125 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
0126     REG_FIELD(WIZ_LANECTL(0), 22, 23),
0127     REG_FIELD(WIZ_LANECTL(1), 22, 23),
0128     REG_FIELD(WIZ_LANECTL(2), 22, 23),
0129     REG_FIELD(WIZ_LANECTL(3), 22, 23),
0130 };
0131 
0132 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
0133     REG_FIELD(WIZ_LANEDIV(0), 16, 22),
0134     REG_FIELD(WIZ_LANEDIV(1), 16, 22),
0135     REG_FIELD(WIZ_LANEDIV(2), 16, 22),
0136     REG_FIELD(WIZ_LANEDIV(3), 16, 22),
0137 };
0138 
0139 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
0140     REG_FIELD(WIZ_LANEDIV(0), 0, 8),
0141     REG_FIELD(WIZ_LANEDIV(1), 0, 8),
0142     REG_FIELD(WIZ_LANEDIV(2), 0, 8),
0143     REG_FIELD(WIZ_LANEDIV(3), 0, 8),
0144 };
0145 
0146 static const struct reg_field typec_ln10_swap =
0147                     REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
0148 
0149 struct wiz_clk_mux {
0150     struct clk_hw       hw;
0151     struct regmap_field *field;
0152     const u32       *table;
0153     struct clk_init_data    clk_data;
0154 };
0155 
0156 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
0157 
0158 struct wiz_clk_divider {
0159     struct clk_hw       hw;
0160     struct regmap_field *field;
0161     const struct clk_div_table  *table;
0162     struct clk_init_data    clk_data;
0163 };
0164 
0165 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
0166 
0167 struct wiz_clk_mux_sel {
0168     u32         table[WIZ_MAX_INPUT_CLOCKS];
0169     const char      *node_name;
0170     u32         num_parents;
0171     u32         parents[WIZ_MAX_INPUT_CLOCKS];
0172 };
0173 
0174 struct wiz_clk_div_sel {
0175     const struct clk_div_table *table;
0176     const char      *node_name;
0177 };
0178 
0179 struct wiz_phy_en_refclk {
0180     struct clk_hw       hw;
0181     struct regmap_field *phy_en_refclk;
0182     struct clk_init_data    clk_data;
0183 };
0184 
0185 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw)
0186 
0187 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
0188     {
0189         /*
0190          * Mux value to be configured for each of the input clocks
0191          * in the order populated in device tree
0192          */
0193         .table = { 1, 0 },
0194         .node_name = "pll0-refclk",
0195     },
0196     {
0197         .table = { 1, 0 },
0198         .node_name = "pll1-refclk",
0199     },
0200     {
0201         .table = { 1, 3, 0, 2 },
0202         .node_name = "refclk-dig",
0203     },
0204 };
0205 
0206 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
0207     {
0208         /*
0209          * Mux value to be configured for each of the input clocks
0210          * in the order populated in device tree
0211          */
0212         .num_parents = 2,
0213         .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
0214         .table = { 1, 0 },
0215         .node_name = "pll0-refclk",
0216     },
0217     {
0218         .num_parents = 2,
0219         .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
0220         .table = { 1, 0 },
0221         .node_name = "pll1-refclk",
0222     },
0223     {
0224         .num_parents = 2,
0225         .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
0226         .table = { 1, 0 },
0227         .node_name = "refclk-dig",
0228     },
0229 };
0230 
0231 static const struct clk_div_table clk_div_table[] = {
0232     { .val = 0, .div = 1, },
0233     { .val = 1, .div = 2, },
0234     { .val = 2, .div = 4, },
0235     { .val = 3, .div = 8, },
0236     { /* sentinel */ },
0237 };
0238 
0239 static const struct wiz_clk_div_sel clk_div_sel[] = {
0240     {
0241         .table = clk_div_table,
0242         .node_name = "cmn-refclk-dig-div",
0243     },
0244     {
0245         .table = clk_div_table,
0246         .node_name = "cmn-refclk1-dig-div",
0247     },
0248 };
0249 
0250 enum wiz_type {
0251     J721E_WIZ_16G,
0252     J721E_WIZ_10G,
0253     AM64_WIZ_10G,
0254 };
0255 
0256 struct wiz_data {
0257     enum wiz_type type;
0258     const struct reg_field *refclk_dig_sel;
0259     const struct reg_field *pma_cmn_refclk1_dig_div;
0260     const struct wiz_clk_mux_sel *clk_mux_sel;
0261     unsigned int clk_div_sel_num;
0262 };
0263 
0264 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN  100 /* ms */
0265 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX  1000
0266 
0267 struct wiz {
0268     struct regmap       *regmap;
0269     enum wiz_type       type;
0270     const struct wiz_clk_mux_sel *clk_mux_sel;
0271     const struct wiz_clk_div_sel *clk_div_sel;
0272     unsigned int        clk_div_sel_num;
0273     struct regmap_field *por_en;
0274     struct regmap_field *phy_reset_n;
0275     struct regmap_field *phy_en_refclk;
0276     struct regmap_field *p_enable[WIZ_MAX_LANES];
0277     struct regmap_field *p_align[WIZ_MAX_LANES];
0278     struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
0279     struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
0280     struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
0281     struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
0282     struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
0283     struct regmap_field *pma_cmn_refclk_int_mode;
0284     struct regmap_field *pma_cmn_refclk_mode;
0285     struct regmap_field *pma_cmn_refclk_dig_div;
0286     struct regmap_field *pma_cmn_refclk1_dig_div;
0287     struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
0288     struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
0289     struct regmap_field *typec_ln10_swap;
0290 
0291     struct device       *dev;
0292     u32         num_lanes;
0293     struct platform_device  *serdes_pdev;
0294     struct reset_controller_dev wiz_phy_reset_dev;
0295     struct gpio_desc    *gpio_typec_dir;
0296     int         typec_dir_delay;
0297     u32 lane_phy_type[WIZ_MAX_LANES];
0298     struct clk      *input_clks[WIZ_MAX_INPUT_CLOCKS];
0299     struct clk      *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
0300     struct clk_onecell_data clk_data;
0301     const struct wiz_data   *data;
0302 };
0303 
0304 static int wiz_reset(struct wiz *wiz)
0305 {
0306     int ret;
0307 
0308     ret = regmap_field_write(wiz->por_en, 0x1);
0309     if (ret)
0310         return ret;
0311 
0312     mdelay(1);
0313 
0314     ret = regmap_field_write(wiz->por_en, 0x0);
0315     if (ret)
0316         return ret;
0317 
0318     return 0;
0319 }
0320 
0321 static int wiz_p_mac_div_sel(struct wiz *wiz)
0322 {
0323     u32 num_lanes = wiz->num_lanes;
0324     int ret;
0325     int i;
0326 
0327     for (i = 0; i < num_lanes; i++) {
0328         if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
0329             ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
0330             if (ret)
0331                 return ret;
0332 
0333             ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
0334             if (ret)
0335                 return ret;
0336         }
0337     }
0338 
0339     return 0;
0340 }
0341 
0342 static int wiz_mode_select(struct wiz *wiz)
0343 {
0344     u32 num_lanes = wiz->num_lanes;
0345     enum wiz_lane_standard_mode mode;
0346     int ret;
0347     int i;
0348 
0349     for (i = 0; i < num_lanes; i++) {
0350         if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
0351             mode = LANE_MODE_GEN1;
0352         else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII)
0353             mode = LANE_MODE_GEN2;
0354         else
0355             continue;
0356 
0357         ret = regmap_field_write(wiz->p_standard_mode[i], mode);
0358         if (ret)
0359             return ret;
0360     }
0361 
0362     return 0;
0363 }
0364 
0365 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
0366 {
0367     u32 num_lanes = wiz->num_lanes;
0368     int i;
0369     int ret;
0370 
0371     for (i = 0; i < num_lanes; i++) {
0372         ret = regmap_field_write(wiz->p_align[i], enable);
0373         if (ret)
0374             return ret;
0375 
0376         ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
0377         if (ret)
0378             return ret;
0379     }
0380 
0381     return 0;
0382 }
0383 
0384 static int wiz_init(struct wiz *wiz)
0385 {
0386     struct device *dev = wiz->dev;
0387     int ret;
0388 
0389     ret = wiz_reset(wiz);
0390     if (ret) {
0391         dev_err(dev, "WIZ reset failed\n");
0392         return ret;
0393     }
0394 
0395     ret = wiz_mode_select(wiz);
0396     if (ret) {
0397         dev_err(dev, "WIZ mode select failed\n");
0398         return ret;
0399     }
0400 
0401     ret = wiz_p_mac_div_sel(wiz);
0402     if (ret) {
0403         dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
0404         return ret;
0405     }
0406 
0407     ret = wiz_init_raw_interface(wiz, true);
0408     if (ret) {
0409         dev_err(dev, "WIZ interface initialization failed\n");
0410         return ret;
0411     }
0412 
0413     return 0;
0414 }
0415 
0416 static int wiz_regfield_init(struct wiz *wiz)
0417 {
0418     struct regmap *regmap = wiz->regmap;
0419     int num_lanes = wiz->num_lanes;
0420     struct device *dev = wiz->dev;
0421     const struct wiz_data *data = wiz->data;
0422     int i;
0423 
0424     wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
0425     if (IS_ERR(wiz->por_en)) {
0426         dev_err(dev, "POR_EN reg field init failed\n");
0427         return PTR_ERR(wiz->por_en);
0428     }
0429 
0430     wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
0431                            phy_reset_n);
0432     if (IS_ERR(wiz->phy_reset_n)) {
0433         dev_err(dev, "PHY_RESET_N reg field init failed\n");
0434         return PTR_ERR(wiz->phy_reset_n);
0435     }
0436 
0437     wiz->pma_cmn_refclk_int_mode =
0438         devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
0439     if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
0440         dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
0441         return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
0442     }
0443 
0444     wiz->pma_cmn_refclk_mode =
0445         devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
0446     if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
0447         dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
0448         return PTR_ERR(wiz->pma_cmn_refclk_mode);
0449     }
0450 
0451     wiz->div_sel_field[CMN_REFCLK_DIG_DIV] =
0452         devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
0453     if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) {
0454         dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
0455         return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);
0456     }
0457 
0458     if (data->pma_cmn_refclk1_dig_div) {
0459         wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =
0460             devm_regmap_field_alloc(dev, regmap,
0461                         *data->pma_cmn_refclk1_dig_div);
0462         if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {
0463             dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
0464             return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);
0465         }
0466     }
0467 
0468     wiz->mux_sel_field[PLL0_REFCLK] =
0469         devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel);
0470     if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
0471         dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
0472         return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
0473     }
0474 
0475     wiz->mux_sel_field[PLL1_REFCLK] =
0476         devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel);
0477     if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
0478         dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
0479         return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
0480     }
0481 
0482     wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap,
0483                                  *data->refclk_dig_sel);
0484     if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
0485         dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
0486         return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
0487     }
0488 
0489     for (i = 0; i < num_lanes; i++) {
0490         wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
0491                                p_enable[i]);
0492         if (IS_ERR(wiz->p_enable[i])) {
0493             dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
0494             return PTR_ERR(wiz->p_enable[i]);
0495         }
0496 
0497         wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
0498                               p_align[i]);
0499         if (IS_ERR(wiz->p_align[i])) {
0500             dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
0501             return PTR_ERR(wiz->p_align[i]);
0502         }
0503 
0504         wiz->p_raw_auto_start[i] =
0505           devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
0506         if (IS_ERR(wiz->p_raw_auto_start[i])) {
0507             dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
0508                 i);
0509             return PTR_ERR(wiz->p_raw_auto_start[i]);
0510         }
0511 
0512         wiz->p_standard_mode[i] =
0513           devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
0514         if (IS_ERR(wiz->p_standard_mode[i])) {
0515             dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
0516                 i);
0517             return PTR_ERR(wiz->p_standard_mode[i]);
0518         }
0519 
0520         wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
0521         if (IS_ERR(wiz->p0_fullrt_div[i])) {
0522             dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
0523             return PTR_ERR(wiz->p0_fullrt_div[i]);
0524         }
0525 
0526         wiz->p_mac_div_sel0[i] =
0527           devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
0528         if (IS_ERR(wiz->p_mac_div_sel0[i])) {
0529             dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
0530                 i);
0531             return PTR_ERR(wiz->p_mac_div_sel0[i]);
0532         }
0533 
0534         wiz->p_mac_div_sel1[i] =
0535           devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
0536         if (IS_ERR(wiz->p_mac_div_sel1[i])) {
0537             dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
0538                 i);
0539             return PTR_ERR(wiz->p_mac_div_sel1[i]);
0540         }
0541     }
0542 
0543     wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
0544                                typec_ln10_swap);
0545     if (IS_ERR(wiz->typec_ln10_swap)) {
0546         dev_err(dev, "LN10_SWAP reg field init failed\n");
0547         return PTR_ERR(wiz->typec_ln10_swap);
0548     }
0549 
0550     wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
0551     if (IS_ERR(wiz->phy_en_refclk)) {
0552         dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
0553         return PTR_ERR(wiz->phy_en_refclk);
0554     }
0555 
0556     return 0;
0557 }
0558 
0559 static int wiz_phy_en_refclk_enable(struct clk_hw *hw)
0560 {
0561     struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
0562     struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
0563 
0564     regmap_field_write(phy_en_refclk, 1);
0565 
0566     return 0;
0567 }
0568 
0569 static void wiz_phy_en_refclk_disable(struct clk_hw *hw)
0570 {
0571     struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
0572     struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
0573 
0574     regmap_field_write(phy_en_refclk, 0);
0575 }
0576 
0577 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw)
0578 {
0579     struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
0580     struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
0581     int val;
0582 
0583     regmap_field_read(phy_en_refclk, &val);
0584 
0585     return !!val;
0586 }
0587 
0588 static const struct clk_ops wiz_phy_en_refclk_ops = {
0589     .enable = wiz_phy_en_refclk_enable,
0590     .disable = wiz_phy_en_refclk_disable,
0591     .is_enabled = wiz_phy_en_refclk_is_enabled,
0592 };
0593 
0594 static int wiz_phy_en_refclk_register(struct wiz *wiz)
0595 {
0596     struct wiz_phy_en_refclk *wiz_phy_en_refclk;
0597     struct device *dev = wiz->dev;
0598     struct clk_init_data *init;
0599     struct clk *clk;
0600 
0601     wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL);
0602     if (!wiz_phy_en_refclk)
0603         return -ENOMEM;
0604 
0605     init = &wiz_phy_en_refclk->clk_data;
0606 
0607     init->ops = &wiz_phy_en_refclk_ops;
0608     init->flags = 0;
0609     init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK];
0610 
0611     wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;
0612     wiz_phy_en_refclk->hw.init = init;
0613 
0614     clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw);
0615     if (IS_ERR(clk))
0616         return PTR_ERR(clk);
0617 
0618     wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;
0619 
0620     return 0;
0621 }
0622 
0623 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
0624 {
0625     struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
0626     struct regmap_field *field = mux->field;
0627     unsigned int val;
0628 
0629     regmap_field_read(field, &val);
0630     return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val);
0631 }
0632 
0633 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
0634 {
0635     struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
0636     struct regmap_field *field = mux->field;
0637     int val;
0638 
0639     val = mux->table[index];
0640     return regmap_field_write(field, val);
0641 }
0642 
0643 static const struct clk_ops wiz_clk_mux_ops = {
0644     .set_parent = wiz_clk_mux_set_parent,
0645     .get_parent = wiz_clk_mux_get_parent,
0646 };
0647 
0648 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,
0649                 const struct wiz_clk_mux_sel *mux_sel, int clk_index)
0650 {
0651     struct device *dev = wiz->dev;
0652     struct clk_init_data *init;
0653     const char **parent_names;
0654     unsigned int num_parents;
0655     struct wiz_clk_mux *mux;
0656     char clk_name[100];
0657     struct clk *clk;
0658     int ret = 0, i;
0659 
0660     mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
0661     if (!mux)
0662         return -ENOMEM;
0663 
0664     num_parents = mux_sel->num_parents;
0665 
0666     parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
0667     if (!parent_names)
0668         return -ENOMEM;
0669 
0670     for (i = 0; i < num_parents; i++) {
0671         clk = wiz->input_clks[mux_sel->parents[i]];
0672         if (IS_ERR_OR_NULL(clk)) {
0673             dev_err(dev, "Failed to get parent clk for %s\n",
0674                 output_clk_names[clk_index]);
0675             ret = -EINVAL;
0676             goto err;
0677         }
0678         parent_names[i] = __clk_get_name(clk);
0679     }
0680 
0681     snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]);
0682 
0683     init = &mux->clk_data;
0684 
0685     init->ops = &wiz_clk_mux_ops;
0686     init->flags = CLK_SET_RATE_NO_REPARENT;
0687     init->parent_names = parent_names;
0688     init->num_parents = num_parents;
0689     init->name = clk_name;
0690 
0691     mux->field = field;
0692     mux->table = mux_sel->table;
0693     mux->hw.init = init;
0694 
0695     clk = devm_clk_register(dev, &mux->hw);
0696     if (IS_ERR(clk)) {
0697         ret = PTR_ERR(clk);
0698         goto err;
0699     }
0700 
0701     wiz->output_clks[clk_index] = clk;
0702 
0703 err:
0704     kfree(parent_names);
0705 
0706     return ret;
0707 }
0708 
0709 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,
0710                    struct regmap_field *field, const u32 *table)
0711 {
0712     struct device *dev = wiz->dev;
0713     struct clk_init_data *init;
0714     const char **parent_names;
0715     unsigned int num_parents;
0716     struct wiz_clk_mux *mux;
0717     char clk_name[100];
0718     struct clk *clk;
0719     int ret;
0720 
0721     mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
0722     if (!mux)
0723         return -ENOMEM;
0724 
0725     num_parents = of_clk_get_parent_count(node);
0726     if (num_parents < 2) {
0727         dev_err(dev, "SERDES clock must have parents\n");
0728         return -EINVAL;
0729     }
0730 
0731     parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
0732                     GFP_KERNEL);
0733     if (!parent_names)
0734         return -ENOMEM;
0735 
0736     of_clk_parent_fill(node, parent_names, num_parents);
0737 
0738     snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
0739          node->name);
0740 
0741     init = &mux->clk_data;
0742 
0743     init->ops = &wiz_clk_mux_ops;
0744     init->flags = CLK_SET_RATE_NO_REPARENT;
0745     init->parent_names = parent_names;
0746     init->num_parents = num_parents;
0747     init->name = clk_name;
0748 
0749     mux->field = field;
0750     mux->table = table;
0751     mux->hw.init = init;
0752 
0753     clk = devm_clk_register(dev, &mux->hw);
0754     if (IS_ERR(clk))
0755         return PTR_ERR(clk);
0756 
0757     ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
0758     if (ret)
0759         dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
0760 
0761     return ret;
0762 }
0763 
0764 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
0765                          unsigned long parent_rate)
0766 {
0767     struct wiz_clk_divider *div = to_wiz_clk_div(hw);
0768     struct regmap_field *field = div->field;
0769     int val;
0770 
0771     regmap_field_read(field, &val);
0772 
0773     return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
0774 }
0775 
0776 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
0777                    unsigned long *prate)
0778 {
0779     struct wiz_clk_divider *div = to_wiz_clk_div(hw);
0780 
0781     return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
0782 }
0783 
0784 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
0785                 unsigned long parent_rate)
0786 {
0787     struct wiz_clk_divider *div = to_wiz_clk_div(hw);
0788     struct regmap_field *field = div->field;
0789     int val;
0790 
0791     val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
0792     if (val < 0)
0793         return val;
0794 
0795     return regmap_field_write(field, val);
0796 }
0797 
0798 static const struct clk_ops wiz_clk_div_ops = {
0799     .recalc_rate = wiz_clk_div_recalc_rate,
0800     .round_rate = wiz_clk_div_round_rate,
0801     .set_rate = wiz_clk_div_set_rate,
0802 };
0803 
0804 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
0805                 struct regmap_field *field,
0806                 const struct clk_div_table *table)
0807 {
0808     struct device *dev = wiz->dev;
0809     struct wiz_clk_divider *div;
0810     struct clk_init_data *init;
0811     const char **parent_names;
0812     char clk_name[100];
0813     struct clk *clk;
0814     int ret;
0815 
0816     div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
0817     if (!div)
0818         return -ENOMEM;
0819 
0820     snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
0821          node->name);
0822 
0823     parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
0824     if (!parent_names)
0825         return -ENOMEM;
0826 
0827     of_clk_parent_fill(node, parent_names, 1);
0828 
0829     init = &div->clk_data;
0830 
0831     init->ops = &wiz_clk_div_ops;
0832     init->flags = 0;
0833     init->parent_names = parent_names;
0834     init->num_parents = 1;
0835     init->name = clk_name;
0836 
0837     div->field = field;
0838     div->table = table;
0839     div->hw.init = init;
0840 
0841     clk = devm_clk_register(dev, &div->hw);
0842     if (IS_ERR(clk))
0843         return PTR_ERR(clk);
0844 
0845     ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
0846     if (ret)
0847         dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
0848 
0849     return ret;
0850 }
0851 
0852 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
0853 {
0854     const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
0855     struct device *dev = wiz->dev;
0856     struct device_node *clk_node;
0857     int i;
0858 
0859     if (wiz->type == AM64_WIZ_10G) {
0860         of_clk_del_provider(dev->of_node);
0861         return;
0862     }
0863 
0864     for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
0865         clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
0866         of_clk_del_provider(clk_node);
0867         of_node_put(clk_node);
0868     }
0869 
0870     for (i = 0; i < wiz->clk_div_sel_num; i++) {
0871         clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name);
0872         of_clk_del_provider(clk_node);
0873         of_node_put(clk_node);
0874     }
0875 
0876     of_clk_del_provider(wiz->dev->of_node);
0877 }
0878 
0879 static int wiz_clock_register(struct wiz *wiz)
0880 {
0881     const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
0882     struct device *dev = wiz->dev;
0883     struct device_node *node = dev->of_node;
0884     int clk_index;
0885     int ret;
0886     int i;
0887 
0888     if (wiz->type != AM64_WIZ_10G)
0889         return 0;
0890 
0891     clk_index = TI_WIZ_PLL0_REFCLK;
0892     for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
0893         ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
0894         if (ret) {
0895             dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]);
0896             return ret;
0897         }
0898     }
0899 
0900     ret = wiz_phy_en_refclk_register(wiz);
0901     if (ret) {
0902         dev_err(dev, "Failed to add phy-en-refclk\n");
0903         return ret;
0904     }
0905 
0906     wiz->clk_data.clks = wiz->output_clks;
0907     wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;
0908     ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);
0909     if (ret)
0910         dev_err(dev, "Failed to add clock provider: %s\n", node->name);
0911 
0912     return ret;
0913 }
0914 
0915 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
0916 {
0917     const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
0918     struct device *dev = wiz->dev;
0919     struct device_node *clk_node;
0920     const char *node_name;
0921     unsigned long rate;
0922     struct clk *clk;
0923     int ret;
0924     int i;
0925 
0926     clk = devm_clk_get(dev, "core_ref_clk");
0927     if (IS_ERR(clk)) {
0928         dev_err(dev, "core_ref_clk clock not found\n");
0929         ret = PTR_ERR(clk);
0930         return ret;
0931     }
0932     wiz->input_clks[WIZ_CORE_REFCLK] = clk;
0933 
0934     rate = clk_get_rate(clk);
0935     if (rate >= 100000000)
0936         regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
0937     else
0938         regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
0939 
0940     clk = devm_clk_get(dev, "ext_ref_clk");
0941     if (IS_ERR(clk)) {
0942         dev_err(dev, "ext_ref_clk clock not found\n");
0943         ret = PTR_ERR(clk);
0944         return ret;
0945     }
0946     wiz->input_clks[WIZ_EXT_REFCLK] = clk;
0947 
0948     rate = clk_get_rate(clk);
0949     if (rate >= 100000000)
0950         regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
0951     else
0952         regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
0953 
0954     if (wiz->type == AM64_WIZ_10G) {
0955         ret = wiz_clock_register(wiz);
0956         if (ret)
0957             dev_err(dev, "Failed to register wiz clocks\n");
0958         return ret;
0959     }
0960 
0961     for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
0962         node_name = clk_mux_sel[i].node_name;
0963         clk_node = of_get_child_by_name(node, node_name);
0964         if (!clk_node) {
0965             dev_err(dev, "Unable to get %s node\n", node_name);
0966             ret = -EINVAL;
0967             goto err;
0968         }
0969 
0970         ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],
0971                           clk_mux_sel[i].table);
0972         if (ret) {
0973             dev_err(dev, "Failed to register %s clock\n",
0974                 node_name);
0975             of_node_put(clk_node);
0976             goto err;
0977         }
0978 
0979         of_node_put(clk_node);
0980     }
0981 
0982     for (i = 0; i < wiz->clk_div_sel_num; i++) {
0983         node_name = clk_div_sel[i].node_name;
0984         clk_node = of_get_child_by_name(node, node_name);
0985         if (!clk_node) {
0986             dev_err(dev, "Unable to get %s node\n", node_name);
0987             ret = -EINVAL;
0988             goto err;
0989         }
0990 
0991         ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i],
0992                        clk_div_sel[i].table);
0993         if (ret) {
0994             dev_err(dev, "Failed to register %s clock\n",
0995                 node_name);
0996             of_node_put(clk_node);
0997             goto err;
0998         }
0999 
1000         of_node_put(clk_node);
1001     }
1002 
1003     return 0;
1004 err:
1005     wiz_clock_cleanup(wiz, node);
1006 
1007     return ret;
1008 }
1009 
1010 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
1011                 unsigned long id)
1012 {
1013     struct device *dev = rcdev->dev;
1014     struct wiz *wiz = dev_get_drvdata(dev);
1015     int ret = 0;
1016 
1017     if (id == 0) {
1018         ret = regmap_field_write(wiz->phy_reset_n, false);
1019         return ret;
1020     }
1021 
1022     ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
1023     return ret;
1024 }
1025 
1026 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
1027 {
1028     if (wiz->type != AM64_WIZ_10G)
1029         return 0;
1030 
1031     if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
1032         return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
1033 
1034     return 0;
1035 }
1036 
1037 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
1038                   unsigned long id)
1039 {
1040     struct device *dev = rcdev->dev;
1041     struct wiz *wiz = dev_get_drvdata(dev);
1042     int ret;
1043 
1044     /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1045     if (id == 0 && wiz->gpio_typec_dir) {
1046         if (wiz->typec_dir_delay)
1047             msleep_interruptible(wiz->typec_dir_delay);
1048 
1049         if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1050             regmap_field_write(wiz->typec_ln10_swap, 1);
1051         else
1052             regmap_field_write(wiz->typec_ln10_swap, 0);
1053     }
1054 
1055     if (id == 0) {
1056         ret = regmap_field_write(wiz->phy_reset_n, true);
1057         return ret;
1058     }
1059 
1060     ret = wiz_phy_fullrt_div(wiz, id - 1);
1061     if (ret)
1062         return ret;
1063 
1064     if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
1065         ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
1066     else
1067         ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
1068 
1069     return ret;
1070 }
1071 
1072 static const struct reset_control_ops wiz_phy_reset_ops = {
1073     .assert = wiz_phy_reset_assert,
1074     .deassert = wiz_phy_reset_deassert,
1075 };
1076 
1077 static const struct regmap_config wiz_regmap_config = {
1078     .reg_bits = 32,
1079     .val_bits = 32,
1080     .reg_stride = 4,
1081     .fast_io = true,
1082 };
1083 
1084 static struct wiz_data j721e_16g_data = {
1085     .type = J721E_WIZ_16G,
1086     .refclk_dig_sel = &refclk_dig_sel_16g,
1087     .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
1088     .clk_mux_sel = clk_mux_sel_16g,
1089     .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
1090 };
1091 
1092 static struct wiz_data j721e_10g_data = {
1093     .type = J721E_WIZ_10G,
1094     .refclk_dig_sel = &refclk_dig_sel_10g,
1095     .clk_mux_sel = clk_mux_sel_10g,
1096     .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1097 };
1098 
1099 static struct wiz_data am64_10g_data = {
1100     .type = AM64_WIZ_10G,
1101     .refclk_dig_sel = &refclk_dig_sel_10g,
1102     .clk_mux_sel = clk_mux_sel_10g,
1103     .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1104 };
1105 
1106 static const struct of_device_id wiz_id_table[] = {
1107     {
1108         .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
1109     },
1110     {
1111         .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
1112     },
1113     {
1114         .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
1115     },
1116     {}
1117 };
1118 MODULE_DEVICE_TABLE(of, wiz_id_table);
1119 
1120 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
1121 {
1122     struct device_node *serdes, *subnode;
1123 
1124     serdes = of_get_child_by_name(dev->of_node, "serdes");
1125     if (!serdes) {
1126         dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
1127         return -EINVAL;
1128     }
1129 
1130     for_each_child_of_node(serdes, subnode) {
1131         u32 reg, num_lanes = 1, phy_type = PHY_NONE;
1132         int ret, i;
1133 
1134         if (!(of_node_name_eq(subnode, "phy") ||
1135               of_node_name_eq(subnode, "link")))
1136             continue;
1137 
1138         ret = of_property_read_u32(subnode, "reg", &reg);
1139         if (ret) {
1140             of_node_put(subnode);
1141             dev_err(dev,
1142                 "%s: Reading \"reg\" from \"%s\" failed: %d\n",
1143                 __func__, subnode->name, ret);
1144             return ret;
1145         }
1146         of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
1147         of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
1148 
1149         dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1150             reg, reg + num_lanes - 1, phy_type);
1151 
1152         for (i = reg; i < reg + num_lanes; i++)
1153             wiz->lane_phy_type[i] = phy_type;
1154     }
1155 
1156     return 0;
1157 }
1158 
1159 static int wiz_probe(struct platform_device *pdev)
1160 {
1161     struct reset_controller_dev *phy_reset_dev;
1162     struct device *dev = &pdev->dev;
1163     struct device_node *node = dev->of_node;
1164     struct platform_device *serdes_pdev;
1165     bool already_configured = false;
1166     struct device_node *child_node;
1167     struct regmap *regmap;
1168     struct resource res;
1169     void __iomem *base;
1170     struct wiz *wiz;
1171     int ret, val, i;
1172     u32 num_lanes;
1173     const struct wiz_data *data;
1174 
1175     wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
1176     if (!wiz)
1177         return -ENOMEM;
1178 
1179     data = of_device_get_match_data(dev);
1180     if (!data) {
1181         dev_err(dev, "NULL device data\n");
1182         return -EINVAL;
1183     }
1184 
1185     wiz->data = data;
1186     wiz->type = data->type;
1187 
1188     child_node = of_get_child_by_name(node, "serdes");
1189     if (!child_node) {
1190         dev_err(dev, "Failed to get SERDES child DT node\n");
1191         return -ENODEV;
1192     }
1193 
1194     ret = of_address_to_resource(child_node, 0, &res);
1195     if (ret) {
1196         dev_err(dev, "Failed to get memory resource\n");
1197         goto err_addr_to_resource;
1198     }
1199 
1200     base = devm_ioremap(dev, res.start, resource_size(&res));
1201     if (!base) {
1202         ret = -ENOMEM;
1203         goto err_addr_to_resource;
1204     }
1205 
1206     regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
1207     if (IS_ERR(regmap)) {
1208         dev_err(dev, "Failed to initialize regmap\n");
1209         ret = PTR_ERR(regmap);
1210         goto err_addr_to_resource;
1211     }
1212 
1213     ret = of_property_read_u32(node, "num-lanes", &num_lanes);
1214     if (ret) {
1215         dev_err(dev, "Failed to read num-lanes property\n");
1216         goto err_addr_to_resource;
1217     }
1218 
1219     if (num_lanes > WIZ_MAX_LANES) {
1220         dev_err(dev, "Cannot support %d lanes\n", num_lanes);
1221         ret = -ENODEV;
1222         goto err_addr_to_resource;
1223     }
1224 
1225     wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
1226                               GPIOD_IN);
1227     if (IS_ERR(wiz->gpio_typec_dir)) {
1228         ret = PTR_ERR(wiz->gpio_typec_dir);
1229         if (ret != -EPROBE_DEFER)
1230             dev_err(dev, "Failed to request typec-dir gpio: %d\n",
1231                 ret);
1232         goto err_addr_to_resource;
1233     }
1234 
1235     if (wiz->gpio_typec_dir) {
1236         ret = of_property_read_u32(node, "typec-dir-debounce-ms",
1237                        &wiz->typec_dir_delay);
1238         if (ret && ret != -EINVAL) {
1239             dev_err(dev, "Invalid typec-dir-debounce property\n");
1240             goto err_addr_to_resource;
1241         }
1242 
1243         /* use min. debounce from Type-C spec if not provided in DT  */
1244         if (ret == -EINVAL)
1245             wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
1246 
1247         if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
1248             wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
1249             ret = -EINVAL;
1250             dev_err(dev, "Invalid typec-dir-debounce property\n");
1251             goto err_addr_to_resource;
1252         }
1253     }
1254 
1255     ret = wiz_get_lane_phy_types(dev, wiz);
1256     if (ret)
1257         return ret;
1258 
1259     wiz->dev = dev;
1260     wiz->regmap = regmap;
1261     wiz->num_lanes = num_lanes;
1262     wiz->clk_mux_sel = data->clk_mux_sel;
1263     wiz->clk_div_sel = clk_div_sel;
1264     wiz->clk_div_sel_num = data->clk_div_sel_num;
1265 
1266     platform_set_drvdata(pdev, wiz);
1267 
1268     ret = wiz_regfield_init(wiz);
1269     if (ret) {
1270         dev_err(dev, "Failed to initialize regfields\n");
1271         goto err_addr_to_resource;
1272     }
1273 
1274     phy_reset_dev = &wiz->wiz_phy_reset_dev;
1275     phy_reset_dev->dev = dev;
1276     phy_reset_dev->ops = &wiz_phy_reset_ops,
1277     phy_reset_dev->owner = THIS_MODULE,
1278     phy_reset_dev->of_node = node;
1279     /* Reset for each of the lane and one for the entire SERDES */
1280     phy_reset_dev->nr_resets = num_lanes + 1;
1281 
1282     ret = devm_reset_controller_register(dev, phy_reset_dev);
1283     if (ret < 0) {
1284         dev_warn(dev, "Failed to register reset controller\n");
1285         goto err_addr_to_resource;
1286     }
1287 
1288     pm_runtime_enable(dev);
1289     ret = pm_runtime_get_sync(dev);
1290     if (ret < 0) {
1291         dev_err(dev, "pm_runtime_get_sync failed\n");
1292         goto err_get_sync;
1293     }
1294 
1295     ret = wiz_clock_init(wiz, node);
1296     if (ret < 0) {
1297         dev_warn(dev, "Failed to initialize clocks\n");
1298         goto err_get_sync;
1299     }
1300 
1301     for (i = 0; i < wiz->num_lanes; i++) {
1302         regmap_field_read(wiz->p_enable[i], &val);
1303         if (val & (P_ENABLE | P_ENABLE_FORCE)) {
1304             already_configured = true;
1305             break;
1306         }
1307     }
1308 
1309     if (!already_configured) {
1310         ret = wiz_init(wiz);
1311         if (ret) {
1312             dev_err(dev, "WIZ initialization failed\n");
1313             goto err_wiz_init;
1314         }
1315     }
1316 
1317     serdes_pdev = of_platform_device_create(child_node, NULL, dev);
1318     if (!serdes_pdev) {
1319         dev_WARN(dev, "Unable to create SERDES platform device\n");
1320         ret = -ENOMEM;
1321         goto err_wiz_init;
1322     }
1323     wiz->serdes_pdev = serdes_pdev;
1324 
1325     of_node_put(child_node);
1326     return 0;
1327 
1328 err_wiz_init:
1329     wiz_clock_cleanup(wiz, node);
1330 
1331 err_get_sync:
1332     pm_runtime_put(dev);
1333     pm_runtime_disable(dev);
1334 
1335 err_addr_to_resource:
1336     of_node_put(child_node);
1337 
1338     return ret;
1339 }
1340 
1341 static int wiz_remove(struct platform_device *pdev)
1342 {
1343     struct device *dev = &pdev->dev;
1344     struct device_node *node = dev->of_node;
1345     struct platform_device *serdes_pdev;
1346     struct wiz *wiz;
1347 
1348     wiz = dev_get_drvdata(dev);
1349     serdes_pdev = wiz->serdes_pdev;
1350 
1351     of_platform_device_destroy(&serdes_pdev->dev, NULL);
1352     wiz_clock_cleanup(wiz, node);
1353     pm_runtime_put(dev);
1354     pm_runtime_disable(dev);
1355 
1356     return 0;
1357 }
1358 
1359 static struct platform_driver wiz_driver = {
1360     .probe      = wiz_probe,
1361     .remove     = wiz_remove,
1362     .driver     = {
1363         .name   = "wiz",
1364         .of_match_table = wiz_id_table,
1365     },
1366 };
1367 module_platform_driver(wiz_driver);
1368 
1369 MODULE_AUTHOR("Texas Instruments Inc.");
1370 MODULE_DESCRIPTION("TI J721E WIZ driver");
1371 MODULE_LICENSE("GPL v2");
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