phy/ti/phy-am654-serdes.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe SERDES driver for AM654x SoC
0004  *
0005  * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
0006  * Author: Kishon Vijay Abraham I <kishon@ti.com>
0007  */
0008
0009 #include <dt-bindings/phy/phy.h>
0010 #include <linux/clk.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/delay.h>
0013 #include <linux/module.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/mux/consumer.h>
0016 #include <linux/of_address.h>
0017 #include <linux/phy/phy.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/pm_runtime.h>
0020 #include <linux/regmap.h>
0021
0022 #define CMU_R004        0x4
0023 #define CMU_R060        0x60
0024 #define CMU_R07C        0x7c
0025 #define CMU_R088        0x88
0026 #define CMU_R0D0        0xd0
0027 #define CMU_R0E8        0xe8
0028
0029 #define LANE_R048       0x248
0030 #define LANE_R058       0x258
0031 #define LANE_R06c       0x26c
0032 #define LANE_R070       0x270
0033 #define LANE_R070       0x270
0034 #define LANE_R19C       0x39c
0035
0036 #define COMLANE_R004        0xa04
0037 #define COMLANE_R138        0xb38
0038 #define VERSION_VAL     0x70
0039
0040 #define COMLANE_R190        0xb90
0041 #define COMLANE_R194        0xb94
0042
0043 #define COMRXEQ_R004        0x1404
0044 #define COMRXEQ_R008        0x1408
0045 #define COMRXEQ_R00C        0x140c
0046 #define COMRXEQ_R014        0x1414
0047 #define COMRXEQ_R018        0x1418
0048 #define COMRXEQ_R01C        0x141c
0049 #define COMRXEQ_R04C        0x144c
0050 #define COMRXEQ_R088        0x1488
0051 #define COMRXEQ_R094        0x1494
0052 #define COMRXEQ_R098        0x1498
0053
0054 #define SERDES_CTRL     0x1fd0
0055
0056 #define WIZ_LANEXCTL_STS    0x1fe0
0057 #define TX0_DISABLE_STATE   0x4
0058 #define TX0_SLEEP_STATE     0x5
0059 #define TX0_SNOOZE_STATE    0x6
0060 #define TX0_ENABLE_STATE    0x7
0061
0062 #define RX0_DISABLE_STATE   0x4
0063 #define RX0_SLEEP_STATE     0x5
0064 #define RX0_SNOOZE_STATE    0x6
0065 #define RX0_ENABLE_STATE    0x7
0066
0067 #define WIZ_PLL_CTRL        0x1ff4
0068 #define PLL_DISABLE_STATE   0x4
0069 #define PLL_SLEEP_STATE     0x5
0070 #define PLL_SNOOZE_STATE    0x6
0071 #define PLL_ENABLE_STATE    0x7
0072
0073 #define PLL_LOCK_TIME       100000  /* in microseconds */
0074 #define SLEEP_TIME      100 /* in microseconds */
0075
0076 #define LANE_USB3       0x0
0077 #define LANE_PCIE0_LANE0    0x1
0078
0079 #define LANE_PCIE1_LANE0    0x0
0080 #define LANE_PCIE0_LANE1    0x1
0081
0082 #define SERDES_NUM_CLOCKS   3
0083
0084 #define AM654_SERDES_CTRL_CLKSEL_MASK   GENMASK(7, 4)
0085 #define AM654_SERDES_CTRL_CLKSEL_SHIFT  4
0086
0087 struct serdes_am654_clk_mux {
0088     struct clk_hw   hw;
0089     struct regmap   *regmap;
0090     unsigned int    reg;
0091     int     clk_id;
0092     struct clk_init_data clk_data;
0093 };
0094
0095 #define to_serdes_am654_clk_mux(_hw)    \
0096         container_of(_hw, struct serdes_am654_clk_mux, hw)
0097
0098 static const struct regmap_config serdes_am654_regmap_config = {
0099     .reg_bits = 32,
0100     .val_bits = 32,
0101     .reg_stride = 4,
0102     .fast_io = true,
0103     .max_register = 0x1ffc,
0104 };
0105
0106 enum serdes_am654_fields {
0107     /* CMU PLL Control */
0108     CMU_PLL_CTRL,
0109
0110     LANE_PLL_CTRL_RXEQ_RXIDLE,
0111
0112     /* CMU VCO bias current and VREG setting */
0113     AHB_PMA_CM_VCO_VBIAS_VREG,
0114     AHB_PMA_CM_VCO_BIAS_VREG,
0115
0116     AHB_PMA_CM_SR,
0117     AHB_SSC_GEN_Z_O_20_13,
0118
0119     /* AHB PMA Lane Configuration */
0120     AHB_PMA_LN_AGC_THSEL_VREGH,
0121
0122     /* AGC and Signal detect threshold for Gen3 */
0123     AHB_PMA_LN_GEN3_AGC_SD_THSEL,
0124
0125     AHB_PMA_LN_RX_SELR_GEN3,
0126     AHB_PMA_LN_TX_DRV,
0127
0128     /* CMU Master Reset */
0129     CMU_MASTER_CDN,
0130
0131     /* P2S ring buffer initial startup pointer difference */
0132     P2S_RBUF_PTR_DIFF,
0133
0134     CONFIG_VERSION,
0135
0136     /* Lane 1 Master Reset */
0137     L1_MASTER_CDN,
0138
0139     /* CMU OK Status */
0140     CMU_OK_I_0,
0141
0142     /* Mid-speed initial calibration control */
0143     COMRXEQ_MS_INIT_CTRL_7_0,
0144
0145     /* High-speed initial calibration control */
0146     COMRXEQ_HS_INIT_CAL_7_0,
0147
0148     /* Mid-speed recalibration control */
0149     COMRXEQ_MS_RECAL_CTRL_7_0,
0150
0151     /* High-speed recalibration control */
0152     COMRXEQ_HS_RECAL_CTRL_7_0,
0153
0154     /* ATT configuration */
0155     COMRXEQ_CSR_ATT_CONFIG,
0156
0157     /* Edge based boost adaptation window length */
0158     COMRXEQ_CSR_EBSTADAPT_WIN_LEN,
0159
0160     /* COMRXEQ control 3 & 4 */
0161     COMRXEQ_CTRL_3_4,
0162
0163     /* COMRXEQ control 14, 15 and 16*/
0164     COMRXEQ_CTRL_14_15_16,
0165
0166     /* Threshold for errors in pattern data  */
0167     COMRXEQ_CSR_DLEV_ERR_THRESH,
0168
0169     /* COMRXEQ control 25 */
0170     COMRXEQ_CTRL_25,
0171
0172     /* Mid-speed rate change calibration control */
0173     CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O,
0174
0175     /* High-speed rate change calibration control */
0176     COMRXEQ_HS_RCHANGE_CTRL_7_0,
0177
0178     /* Serdes reset */
0179     POR_EN,
0180
0181     /* Tx Enable Value */
0182     TX0_ENABLE,
0183
0184     /* Rx Enable Value */
0185     RX0_ENABLE,
0186
0187     /* PLL Enable Value */
0188     PLL_ENABLE,
0189
0190     /* PLL ready for use */
0191     PLL_OK,
0192
0193     /* sentinel */
0194     MAX_FIELDS
0195
0196 };
0197
0198 static const struct reg_field serdes_am654_reg_fields[] = {
0199     [CMU_PLL_CTRL]          = REG_FIELD(CMU_R004, 8, 15),
0200     [AHB_PMA_CM_VCO_VBIAS_VREG] = REG_FIELD(CMU_R060, 8, 15),
0201     [CMU_MASTER_CDN]        = REG_FIELD(CMU_R07C, 24, 31),
0202     [AHB_PMA_CM_VCO_BIAS_VREG]  = REG_FIELD(CMU_R088, 24, 31),
0203     [AHB_PMA_CM_SR]         = REG_FIELD(CMU_R0D0, 24, 31),
0204     [AHB_SSC_GEN_Z_O_20_13]     = REG_FIELD(CMU_R0E8, 8, 15),
0205     [LANE_PLL_CTRL_RXEQ_RXIDLE] = REG_FIELD(LANE_R048, 8, 15),
0206     [AHB_PMA_LN_AGC_THSEL_VREGH]    = REG_FIELD(LANE_R058, 16, 23),
0207     [AHB_PMA_LN_GEN3_AGC_SD_THSEL]  = REG_FIELD(LANE_R06c, 0, 7),
0208     [AHB_PMA_LN_RX_SELR_GEN3]   = REG_FIELD(LANE_R070, 16, 23),
0209     [AHB_PMA_LN_TX_DRV]     = REG_FIELD(LANE_R19C, 16, 23),
0210     [P2S_RBUF_PTR_DIFF]     = REG_FIELD(COMLANE_R004, 0, 7),
0211     [CONFIG_VERSION]        = REG_FIELD(COMLANE_R138, 16, 23),
0212     [L1_MASTER_CDN]         = REG_FIELD(COMLANE_R190, 8, 15),
0213     [CMU_OK_I_0]            = REG_FIELD(COMLANE_R194, 19, 19),
0214     [COMRXEQ_MS_INIT_CTRL_7_0]  = REG_FIELD(COMRXEQ_R004, 24, 31),
0215     [COMRXEQ_HS_INIT_CAL_7_0]   = REG_FIELD(COMRXEQ_R008, 0, 7),
0216     [COMRXEQ_MS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 8, 15),
0217     [COMRXEQ_HS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 16, 23),
0218     [COMRXEQ_CSR_ATT_CONFIG]    = REG_FIELD(COMRXEQ_R014, 16, 23),
0219     [COMRXEQ_CSR_EBSTADAPT_WIN_LEN] = REG_FIELD(COMRXEQ_R018, 16, 23),
0220     [COMRXEQ_CTRL_3_4]      = REG_FIELD(COMRXEQ_R01C, 8, 15),
0221     [COMRXEQ_CTRL_14_15_16]     = REG_FIELD(COMRXEQ_R04C, 0, 7),
0222     [COMRXEQ_CSR_DLEV_ERR_THRESH]   = REG_FIELD(COMRXEQ_R088, 16, 23),
0223     [COMRXEQ_CTRL_25]       = REG_FIELD(COMRXEQ_R094, 24, 31),
0224     [CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O] = REG_FIELD(COMRXEQ_R098, 8, 15),
0225     [COMRXEQ_HS_RCHANGE_CTRL_7_0]   = REG_FIELD(COMRXEQ_R098, 16, 23),
0226     [POR_EN]            = REG_FIELD(SERDES_CTRL, 29, 29),
0227     [TX0_ENABLE]            = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31),
0228     [RX0_ENABLE]            = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15),
0229     [PLL_ENABLE]            = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
0230     [PLL_OK]            = REG_FIELD(WIZ_PLL_CTRL, 28, 28),
0231 };
0232
0233 struct serdes_am654 {
0234     struct regmap       *regmap;
0235     struct regmap_field *fields[MAX_FIELDS];
0236
0237     struct device       *dev;
0238     struct mux_control  *control;
0239     bool            busy;
0240     u32         type;
0241     struct device_node  *of_node;
0242     struct clk_onecell_data clk_data;
0243     struct clk      *clks[SERDES_NUM_CLOCKS];
0244 };
0245
0246 static int serdes_am654_enable_pll(struct serdes_am654 *phy)
0247 {
0248     int ret;
0249     u32 val;
0250
0251     ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE);
0252     if (ret)
0253         return ret;
0254
0255     return regmap_field_read_poll_timeout(phy->fields[PLL_OK], val, val,
0256                           1000, PLL_LOCK_TIME);
0257 }
0258
0259 static void serdes_am654_disable_pll(struct serdes_am654 *phy)
0260 {
0261     struct device *dev = phy->dev;
0262     int ret;
0263
0264     ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE);
0265     if (ret)
0266         dev_err(dev, "Failed to disable PLL\n");
0267 }
0268
0269 static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
0270 {
0271     int ret = 0;
0272
0273     /* Enable TX */
0274     ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_ENABLE_STATE);
0275
0276     /* Enable RX */
0277     ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_ENABLE_STATE);
0278
0279     if (ret)
0280         return -EIO;
0281
0282     return 0;
0283 }
0284
0285 static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
0286 {
0287     int ret = 0;
0288
0289     /* Disable TX */
0290     ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_DISABLE_STATE);
0291
0292     /* Disable RX */
0293     ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_DISABLE_STATE);
0294
0295     if (ret)
0296         return -EIO;
0297
0298     return 0;
0299 }
0300
0301 static int serdes_am654_power_on(struct phy *x)
0302 {
0303     struct serdes_am654 *phy = phy_get_drvdata(x);
0304     struct device *dev = phy->dev;
0305     int ret;
0306     u32 val;
0307
0308     ret = serdes_am654_enable_pll(phy);
0309     if (ret) {
0310         dev_err(dev, "Failed to enable PLL\n");
0311         return ret;
0312     }
0313
0314     ret = serdes_am654_enable_txrx(phy);
0315     if (ret) {
0316         dev_err(dev, "Failed to enable TX RX\n");
0317         return ret;
0318     }
0319
0320     return regmap_field_read_poll_timeout(phy->fields[CMU_OK_I_0], val,
0321                           val, SLEEP_TIME, PLL_LOCK_TIME);
0322 }
0323
0324 static int serdes_am654_power_off(struct phy *x)
0325 {
0326     struct serdes_am654 *phy = phy_get_drvdata(x);
0327
0328     serdes_am654_disable_txrx(phy);
0329     serdes_am654_disable_pll(phy);
0330
0331     return 0;
0332 }
0333
0334 #define SERDES_AM654_CFG(offset, a, b, val) \
0335     regmap_update_bits(phy->regmap, (offset),\
0336                GENMASK((a), (b)), (val) << (b))
0337
0338 static int serdes_am654_usb3_init(struct serdes_am654 *phy)
0339 {
0340     SERDES_AM654_CFG(0x0000, 31, 24, 0x17);
0341     SERDES_AM654_CFG(0x0004, 15, 8, 0x02);
0342     SERDES_AM654_CFG(0x0004, 7, 0, 0x0e);
0343     SERDES_AM654_CFG(0x0008, 23, 16, 0x2e);
0344     SERDES_AM654_CFG(0x0008, 31, 24, 0x2e);
0345     SERDES_AM654_CFG(0x0060, 7, 0, 0x4b);
0346     SERDES_AM654_CFG(0x0060, 15, 8, 0x98);
0347     SERDES_AM654_CFG(0x0060, 23, 16, 0x60);
0348     SERDES_AM654_CFG(0x00d0, 31, 24, 0x45);
0349     SERDES_AM654_CFG(0x00e8, 15, 8, 0x0e);
0350     SERDES_AM654_CFG(0x0220, 7, 0, 0x34);
0351     SERDES_AM654_CFG(0x0220, 15, 8, 0x34);
0352     SERDES_AM654_CFG(0x0220, 31, 24, 0x37);
0353     SERDES_AM654_CFG(0x0224, 7, 0, 0x37);
0354     SERDES_AM654_CFG(0x0224, 15, 8, 0x37);
0355     SERDES_AM654_CFG(0x0228, 23, 16, 0x37);
0356     SERDES_AM654_CFG(0x0228, 31, 24, 0x37);
0357     SERDES_AM654_CFG(0x022c, 7, 0, 0x37);
0358     SERDES_AM654_CFG(0x022c, 15, 8, 0x37);
0359     SERDES_AM654_CFG(0x0230, 15, 8, 0x2a);
0360     SERDES_AM654_CFG(0x0230, 23, 16, 0x2a);
0361     SERDES_AM654_CFG(0x0240, 23, 16, 0x10);
0362     SERDES_AM654_CFG(0x0240, 31, 24, 0x34);
0363     SERDES_AM654_CFG(0x0244, 7, 0, 0x40);
0364     SERDES_AM654_CFG(0x0244, 23, 16, 0x34);
0365     SERDES_AM654_CFG(0x0248, 15, 8, 0x0d);
0366     SERDES_AM654_CFG(0x0258, 15, 8, 0x16);
0367     SERDES_AM654_CFG(0x0258, 23, 16, 0x84);
0368     SERDES_AM654_CFG(0x0258, 31, 24, 0xf2);
0369     SERDES_AM654_CFG(0x025c, 7, 0, 0x21);
0370     SERDES_AM654_CFG(0x0260, 7, 0, 0x27);
0371     SERDES_AM654_CFG(0x0260, 15, 8, 0x04);
0372     SERDES_AM654_CFG(0x0268, 15, 8, 0x04);
0373     SERDES_AM654_CFG(0x0288, 15, 8, 0x2c);
0374     SERDES_AM654_CFG(0x0330, 31, 24, 0xa0);
0375     SERDES_AM654_CFG(0x0338, 23, 16, 0x03);
0376     SERDES_AM654_CFG(0x0338, 31, 24, 0x00);
0377     SERDES_AM654_CFG(0x033c, 7, 0, 0x00);
0378     SERDES_AM654_CFG(0x0344, 31, 24, 0x18);
0379     SERDES_AM654_CFG(0x034c, 7, 0, 0x18);
0380     SERDES_AM654_CFG(0x039c, 23, 16, 0x3b);
0381     SERDES_AM654_CFG(0x0a04, 7, 0, 0x03);
0382     SERDES_AM654_CFG(0x0a14, 31, 24, 0x3c);
0383     SERDES_AM654_CFG(0x0a18, 15, 8, 0x3c);
0384     SERDES_AM654_CFG(0x0a38, 7, 0, 0x3e);
0385     SERDES_AM654_CFG(0x0a38, 15, 8, 0x3e);
0386     SERDES_AM654_CFG(0x0ae0, 7, 0, 0x07);
0387     SERDES_AM654_CFG(0x0b6c, 23, 16, 0xcd);
0388     SERDES_AM654_CFG(0x0b6c, 31, 24, 0x04);
0389     SERDES_AM654_CFG(0x0b98, 23, 16, 0x03);
0390     SERDES_AM654_CFG(0x1400, 7, 0, 0x3f);
0391     SERDES_AM654_CFG(0x1404, 23, 16, 0x6f);
0392     SERDES_AM654_CFG(0x1404, 31, 24, 0x6f);
0393     SERDES_AM654_CFG(0x140c, 7, 0, 0x6f);
0394     SERDES_AM654_CFG(0x140c, 15, 8, 0x6f);
0395     SERDES_AM654_CFG(0x1410, 15, 8, 0x27);
0396     SERDES_AM654_CFG(0x1414, 7, 0, 0x0c);
0397     SERDES_AM654_CFG(0x1414, 23, 16, 0x07);
0398     SERDES_AM654_CFG(0x1418, 23, 16, 0x40);
0399     SERDES_AM654_CFG(0x141c, 7, 0, 0x00);
0400     SERDES_AM654_CFG(0x141c, 15, 8, 0x1f);
0401     SERDES_AM654_CFG(0x1428, 31, 24, 0x08);
0402     SERDES_AM654_CFG(0x1434, 31, 24, 0x00);
0403     SERDES_AM654_CFG(0x1444, 7, 0, 0x94);
0404     SERDES_AM654_CFG(0x1460, 31, 24, 0x7f);
0405     SERDES_AM654_CFG(0x1464, 7, 0, 0x43);
0406     SERDES_AM654_CFG(0x1464, 23, 16, 0x6f);
0407     SERDES_AM654_CFG(0x1464, 31, 24, 0x43);
0408     SERDES_AM654_CFG(0x1484, 23, 16, 0x8f);
0409     SERDES_AM654_CFG(0x1498, 7, 0, 0x4f);
0410     SERDES_AM654_CFG(0x1498, 23, 16, 0x4f);
0411     SERDES_AM654_CFG(0x007c, 31, 24, 0x0d);
0412     SERDES_AM654_CFG(0x0b90, 15, 8, 0x0f);
0413
0414     return 0;
0415 }
0416
0417 static int serdes_am654_pcie_init(struct serdes_am654 *phy)
0418 {
0419     int ret = 0;
0420
0421     ret |= regmap_field_write(phy->fields[CMU_PLL_CTRL], 0x2);
0422     ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_VBIAS_VREG], 0x98);
0423     ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_BIAS_VREG], 0x98);
0424     ret |= regmap_field_write(phy->fields[AHB_PMA_CM_SR], 0x45);
0425     ret |= regmap_field_write(phy->fields[AHB_SSC_GEN_Z_O_20_13], 0xe);
0426     ret |= regmap_field_write(phy->fields[LANE_PLL_CTRL_RXEQ_RXIDLE], 0x5);
0427     ret |= regmap_field_write(phy->fields[AHB_PMA_LN_AGC_THSEL_VREGH], 0x83);
0428     ret |= regmap_field_write(phy->fields[AHB_PMA_LN_GEN3_AGC_SD_THSEL], 0x83);
0429     ret |= regmap_field_write(phy->fields[AHB_PMA_LN_RX_SELR_GEN3], 0x81);
0430     ret |= regmap_field_write(phy->fields[AHB_PMA_LN_TX_DRV], 0x3b);
0431     ret |= regmap_field_write(phy->fields[P2S_RBUF_PTR_DIFF], 0x3);
0432     ret |= regmap_field_write(phy->fields[CONFIG_VERSION], VERSION_VAL);
0433     ret |= regmap_field_write(phy->fields[COMRXEQ_MS_INIT_CTRL_7_0], 0xf);
0434     ret |= regmap_field_write(phy->fields[COMRXEQ_HS_INIT_CAL_7_0], 0x4f);
0435     ret |= regmap_field_write(phy->fields[COMRXEQ_MS_RECAL_CTRL_7_0], 0xf);
0436     ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RECAL_CTRL_7_0], 0x4f);
0437     ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_ATT_CONFIG], 0x7);
0438     ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_EBSTADAPT_WIN_LEN], 0x7f);
0439     ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_3_4], 0xf);
0440     ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_14_15_16], 0x9a);
0441     ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_DLEV_ERR_THRESH], 0x32);
0442     ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_25], 0x80);
0443     ret |= regmap_field_write(phy->fields[CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O], 0xf);
0444     ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RCHANGE_CTRL_7_0], 0x4f);
0445     ret |= regmap_field_write(phy->fields[CMU_MASTER_CDN], 0x1);
0446     ret |= regmap_field_write(phy->fields[L1_MASTER_CDN], 0x2);
0447
0448     if (ret)
0449         return -EIO;
0450
0451     return 0;
0452 }
0453
0454 static int serdes_am654_init(struct phy *x)
0455 {
0456     struct serdes_am654 *phy = phy_get_drvdata(x);
0457
0458     switch (phy->type) {
0459     case PHY_TYPE_PCIE:
0460         return serdes_am654_pcie_init(phy);
0461     case PHY_TYPE_USB3:
0462         return serdes_am654_usb3_init(phy);
0463     default:
0464         return -EINVAL;
0465     }
0466 }
0467
0468 static int serdes_am654_reset(struct phy *x)
0469 {
0470     struct serdes_am654 *phy = phy_get_drvdata(x);
0471     int ret = 0;
0472
0473     serdes_am654_disable_pll(phy);
0474     serdes_am654_disable_txrx(phy);
0475
0476     ret |= regmap_field_write(phy->fields[POR_EN], 0x1);
0477
0478     mdelay(1);
0479
0480     ret |= regmap_field_write(phy->fields[POR_EN], 0x0);
0481
0482     if (ret)
0483         return -EIO;
0484
0485     return 0;
0486 }
0487
0488 static void serdes_am654_release(struct phy *x)
0489 {
0490     struct serdes_am654 *phy = phy_get_drvdata(x);
0491
0492     phy->type = PHY_NONE;
0493     phy->busy = false;
0494     mux_control_deselect(phy->control);
0495 }
0496
0497 static struct phy *serdes_am654_xlate(struct device *dev,
0498                       struct of_phandle_args *args)
0499 {
0500     struct serdes_am654 *am654_phy;
0501     struct phy *phy;
0502     int ret;
0503
0504     phy = of_phy_simple_xlate(dev, args);
0505     if (IS_ERR(phy))
0506         return phy;
0507
0508     am654_phy = phy_get_drvdata(phy);
0509     if (am654_phy->busy)
0510         return ERR_PTR(-EBUSY);
0511
0512     ret = mux_control_select(am654_phy->control, args->args[1]);
0513     if (ret) {
0514         dev_err(dev, "Failed to select SERDES Lane Function\n");
0515         return ERR_PTR(ret);
0516     }
0517
0518     am654_phy->busy = true;
0519     am654_phy->type = args->args[0];
0520
0521     return phy;
0522 }
0523
0524 static const struct phy_ops ops = {
0525     .reset      = serdes_am654_reset,
0526     .init       = serdes_am654_init,
0527     .power_on   = serdes_am654_power_on,
0528     .power_off  = serdes_am654_power_off,
0529     .release    = serdes_am654_release,
0530     .owner      = THIS_MODULE,
0531 };
0532
0533 #define SERDES_NUM_MUX_COMBINATIONS 16
0534
0535 #define LICLK 0
0536 #define EXT_REFCLK 1
0537 #define RICLK 2
0538
0539 static const int
0540 serdes_am654_mux_table[SERDES_NUM_MUX_COMBINATIONS][SERDES_NUM_CLOCKS] = {
0541     /*
0542      * Each combination maps to one of
0543      * "Figure 12-1986. SerDes Reference Clock Distribution"
0544      * in TRM.
0545      */
0546      /* Parent of CMU refclk, Left output, Right output
0547       * either of EXT_REFCLK, LICLK, RICLK
0548       */
0549     { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0000 */
0550     { RICLK, EXT_REFCLK, EXT_REFCLK },  /* 0001 */
0551     { EXT_REFCLK, RICLK, LICLK },       /* 0010 */
0552     { RICLK, RICLK, EXT_REFCLK },       /* 0011 */
0553     { LICLK, EXT_REFCLK, EXT_REFCLK },  /* 0100 */
0554     { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0101 */
0555     { LICLK, RICLK, LICLK },        /* 0110 */
0556     { EXT_REFCLK, RICLK, LICLK },       /* 0111 */
0557     { EXT_REFCLK, EXT_REFCLK, LICLK },  /* 1000 */
0558     { RICLK, EXT_REFCLK, LICLK },       /* 1001 */
0559     { EXT_REFCLK, RICLK, EXT_REFCLK },  /* 1010 */
0560     { RICLK, RICLK, EXT_REFCLK },       /* 1011 */
0561     { LICLK, EXT_REFCLK, LICLK },       /* 1100 */
0562     { EXT_REFCLK, EXT_REFCLK, LICLK },  /* 1101 */
0563     { LICLK, RICLK, EXT_REFCLK },       /* 1110 */
0564     { EXT_REFCLK, RICLK, EXT_REFCLK },  /* 1111 */
0565 };
0566
0567 static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw)
0568 {
0569     struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
0570     struct regmap *regmap = mux->regmap;
0571     unsigned int reg = mux->reg;
0572     unsigned int val;
0573
0574     regmap_read(regmap, reg, &val);
0575     val &= AM654_SERDES_CTRL_CLKSEL_MASK;
0576     val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
0577
0578     return serdes_am654_mux_table[val][mux->clk_id];
0579 }
0580
0581 static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
0582 {
0583     struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
0584     struct regmap *regmap = mux->regmap;
0585     const char *name = clk_hw_get_name(hw);
0586     unsigned int reg = mux->reg;
0587     int clk_id = mux->clk_id;
0588     int parents[SERDES_NUM_CLOCKS];
0589     const int *p;
0590     u32 val;
0591     int found, i;
0592     int ret;
0593
0594     /* get existing setting */
0595     regmap_read(regmap, reg, &val);
0596     val &= AM654_SERDES_CTRL_CLKSEL_MASK;
0597     val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
0598
0599     for (i = 0; i < SERDES_NUM_CLOCKS; i++)
0600         parents[i] = serdes_am654_mux_table[val][i];
0601
0602     /* change parent of this clock. others left intact */
0603     parents[clk_id] = index;
0604
0605     /* Find the match */
0606     for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) {
0607         p = serdes_am654_mux_table[val];
0608         found = 1;
0609         for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
0610             if (parents[i] != p[i]) {
0611                 found = 0;
0612                 break;
0613             }
0614         }
0615
0616         if (found)
0617             break;
0618     }
0619
0620     if (!found) {
0621         /*
0622          * This can never happen, unless we missed
0623          * a valid combination in serdes_am654_mux_table.
0624          */
0625         WARN(1, "Failed to find the parent of %s clock\n", name);
0626         return -EINVAL;
0627     }
0628
0629     val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT;
0630     ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK,
0631                  val);
0632
0633     return ret;
0634 }
0635
0636 static const struct clk_ops serdes_am654_clk_mux_ops = {
0637     .set_parent = serdes_am654_clk_mux_set_parent,
0638     .get_parent = serdes_am654_clk_mux_get_parent,
0639 };
0640
0641 static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
0642                      const char *clock_name, int clock_num)
0643 {
0644     struct device_node *node = am654_phy->of_node;
0645     struct device *dev = am654_phy->dev;
0646     struct serdes_am654_clk_mux *mux;
0647     struct device_node *regmap_node;
0648     const char **parent_names;
0649     struct clk_init_data *init;
0650     unsigned int num_parents;
0651     struct regmap *regmap;
0652     const __be32 *addr;
0653     unsigned int reg;
0654     struct clk *clk;
0655     int ret = 0;
0656
0657     mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
0658     if (!mux)
0659         return -ENOMEM;
0660
0661     init = &mux->clk_data;
0662
0663     regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0);
0664     if (!regmap_node) {
0665         dev_err(dev, "Fail to get serdes-clk node\n");
0666         ret = -ENODEV;
0667         goto out_put_node;
0668     }
0669
0670     regmap = syscon_node_to_regmap(regmap_node->parent);
0671     if (IS_ERR(regmap)) {
0672         dev_err(dev, "Fail to get Syscon regmap\n");
0673         ret = PTR_ERR(regmap);
0674         goto out_put_node;
0675     }
0676
0677     num_parents = of_clk_get_parent_count(node);
0678     if (num_parents < 2) {
0679         dev_err(dev, "SERDES clock must have parents\n");
0680         ret = -EINVAL;
0681         goto out_put_node;
0682     }
0683
0684     parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
0685                     GFP_KERNEL);
0686     if (!parent_names) {
0687         ret = -ENOMEM;
0688         goto out_put_node;
0689     }
0690
0691     of_clk_parent_fill(node, parent_names, num_parents);
0692
0693     addr = of_get_address(regmap_node, 0, NULL, NULL);
0694     if (!addr) {
0695         ret = -EINVAL;
0696         goto out_put_node;
0697     }
0698
0699     reg = be32_to_cpu(*addr);
0700
0701     init->ops = &serdes_am654_clk_mux_ops;
0702     init->flags = CLK_SET_RATE_NO_REPARENT;
0703     init->parent_names = parent_names;
0704     init->num_parents = num_parents;
0705     init->name = clock_name;
0706
0707     mux->regmap = regmap;
0708     mux->reg = reg;
0709     mux->clk_id = clock_num;
0710     mux->hw.init = init;
0711
0712     clk = devm_clk_register(dev, &mux->hw);
0713     if (IS_ERR(clk)) {
0714         ret = PTR_ERR(clk);
0715         goto out_put_node;
0716     }
0717
0718     am654_phy->clks[clock_num] = clk;
0719
0720 out_put_node:
0721     of_node_put(regmap_node);
0722     return ret;
0723 }
0724
0725 static const struct of_device_id serdes_am654_id_table[] = {
0726     {
0727         .compatible = "ti,phy-am654-serdes",
0728     },
0729     {}
0730 };
0731 MODULE_DEVICE_TABLE(of, serdes_am654_id_table);
0732
0733 static int serdes_am654_regfield_init(struct serdes_am654 *am654_phy)
0734 {
0735     struct regmap *regmap = am654_phy->regmap;
0736     struct device *dev = am654_phy->dev;
0737     int i;
0738
0739     for (i = 0; i < MAX_FIELDS; i++) {
0740         am654_phy->fields[i] = devm_regmap_field_alloc(dev,
0741                                    regmap,
0742                                    serdes_am654_reg_fields[i]);
0743         if (IS_ERR(am654_phy->fields[i])) {
0744             dev_err(dev, "Unable to allocate regmap field %d\n", i);
0745             return PTR_ERR(am654_phy->fields[i]);
0746         }
0747     }
0748
0749     return 0;
0750 }
0751
0752 static int serdes_am654_probe(struct platform_device *pdev)
0753 {
0754     struct phy_provider *phy_provider;
0755     struct device *dev = &pdev->dev;
0756     struct device_node *node = dev->of_node;
0757     struct clk_onecell_data *clk_data;
0758     struct serdes_am654 *am654_phy;
0759     struct mux_control *control;
0760     const char *clock_name;
0761     struct regmap *regmap;
0762     void __iomem *base;
0763     struct phy *phy;
0764     int ret;
0765     int i;
0766
0767     am654_phy = devm_kzalloc(dev, sizeof(*am654_phy), GFP_KERNEL);
0768     if (!am654_phy)
0769         return -ENOMEM;
0770
0771     base = devm_platform_ioremap_resource(pdev, 0);
0772     if (IS_ERR(base))
0773         return PTR_ERR(base);
0774
0775     regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config);
0776     if (IS_ERR(regmap)) {
0777         dev_err(dev, "Failed to initialize regmap\n");
0778         return PTR_ERR(regmap);
0779     }
0780
0781     control = devm_mux_control_get(dev, NULL);
0782     if (IS_ERR(control))
0783         return PTR_ERR(control);
0784
0785     am654_phy->dev = dev;
0786     am654_phy->of_node = node;
0787     am654_phy->regmap = regmap;
0788     am654_phy->control = control;
0789     am654_phy->type = PHY_NONE;
0790
0791     ret = serdes_am654_regfield_init(am654_phy);
0792     if (ret) {
0793         dev_err(dev, "Failed to initialize regfields\n");
0794         return ret;
0795     }
0796
0797     platform_set_drvdata(pdev, am654_phy);
0798
0799     for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
0800         ret = of_property_read_string_index(node, "clock-output-names",
0801                             i, &clock_name);
0802         if (ret) {
0803             dev_err(dev, "Failed to get clock name\n");
0804             return ret;
0805         }
0806
0807         ret = serdes_am654_clk_register(am654_phy, clock_name, i);
0808         if (ret) {
0809             dev_err(dev, "Failed to initialize clock %s\n",
0810                 clock_name);
0811             return ret;
0812         }
0813     }
0814
0815     clk_data = &am654_phy->clk_data;
0816     clk_data->clks = am654_phy->clks;
0817     clk_data->clk_num = SERDES_NUM_CLOCKS;
0818     ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
0819     if (ret)
0820         return ret;
0821
0822     pm_runtime_enable(dev);
0823
0824     phy = devm_phy_create(dev, NULL, &ops);
0825     if (IS_ERR(phy)) {
0826         ret = PTR_ERR(phy);
0827         goto clk_err;
0828     }
0829
0830     phy_set_drvdata(phy, am654_phy);
0831     phy_provider = devm_of_phy_provider_register(dev, serdes_am654_xlate);
0832     if (IS_ERR(phy_provider)) {
0833         ret = PTR_ERR(phy_provider);
0834         goto clk_err;
0835     }
0836
0837     return 0;
0838
0839 clk_err:
0840     of_clk_del_provider(node);
0841     pm_runtime_disable(dev);
0842     return ret;
0843 }
0844
0845 static int serdes_am654_remove(struct platform_device *pdev)
0846 {
0847     struct serdes_am654 *am654_phy = platform_get_drvdata(pdev);
0848     struct device_node *node = am654_phy->of_node;
0849
0850     pm_runtime_disable(&pdev->dev);
0851     of_clk_del_provider(node);
0852
0853     return 0;
0854 }
0855
0856 static struct platform_driver serdes_am654_driver = {
0857     .probe      = serdes_am654_probe,
0858     .remove     = serdes_am654_remove,
0859     .driver     = {
0860         .name   = "phy-am654",
0861         .of_match_table = serdes_am654_id_table,
0862     },
0863 };
0864 module_platform_driver(serdes_am654_driver);
0865
0866 MODULE_AUTHOR("Texas Instruments Inc.");
0867 MODULE_DESCRIPTION("TI AM654x SERDES driver");
0868 MODULE_LICENSE("GPL v2");