phy/tegra/phy-tegra194-p2u.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * P2U (PIPE to UPHY) driver for Tegra T194 SoC
0004  *
0005  * Copyright (C) 2019-2022 NVIDIA Corporation.
0006  *
0007  * Author: Vidya Sagar <vidyas@nvidia.com>
0008  */
0009
0010 #include <linux/err.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/phy/phy.h>
0016
0017 #define P2U_CONTROL_CMN         0x74
0018 #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN          BIT(20)
0019
0020 #define P2U_PERIODIC_EQ_CTRL_GEN3   0xc0
0021 #define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN        BIT(0)
0022 #define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN   BIT(1)
0023 #define P2U_PERIODIC_EQ_CTRL_GEN4   0xc4
0024 #define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN   BIT(1)
0025
0026 #define P2U_RX_DEBOUNCE_TIME                0xa4
0027 #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK    0xffff
0028 #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL     160
0029
0030 #define P2U_DIR_SEARCH_CTRL             0xd4
0031 #define P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE    BIT(18)
0032
0033 struct tegra_p2u_of_data {
0034     bool one_dir_search;
0035 };
0036
0037 struct tegra_p2u {
0038     void __iomem *base;
0039     bool skip_sz_protection_en; /* Needed to support two retimers */
0040     struct tegra_p2u_of_data *of_data;
0041 };
0042
0043 static inline void p2u_writel(struct tegra_p2u *phy, const u32 value,
0044                   const u32 reg)
0045 {
0046     writel_relaxed(value, phy->base + reg);
0047 }
0048
0049 static inline u32 p2u_readl(struct tegra_p2u *phy, const u32 reg)
0050 {
0051     return readl_relaxed(phy->base + reg);
0052 }
0053
0054 static int tegra_p2u_power_on(struct phy *x)
0055 {
0056     struct tegra_p2u *phy = phy_get_drvdata(x);
0057     u32 val;
0058
0059     if (phy->skip_sz_protection_en) {
0060         val = p2u_readl(phy, P2U_CONTROL_CMN);
0061         val |= P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN;
0062         p2u_writel(phy, val, P2U_CONTROL_CMN);
0063     }
0064
0065     val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);
0066     val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
0067     val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
0068     p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN3);
0069
0070     val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN4);
0071     val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN;
0072     p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN4);
0073
0074     val = p2u_readl(phy, P2U_RX_DEBOUNCE_TIME);
0075     val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK;
0076     val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
0077     p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME);
0078
0079     if (phy->of_data->one_dir_search) {
0080         val = p2u_readl(phy, P2U_DIR_SEARCH_CTRL);
0081         val &= ~P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE;
0082         p2u_writel(phy, val, P2U_DIR_SEARCH_CTRL);
0083     }
0084
0085     return 0;
0086 }
0087
0088 static const struct phy_ops ops = {
0089     .power_on = tegra_p2u_power_on,
0090     .owner = THIS_MODULE,
0091 };
0092
0093 static int tegra_p2u_probe(struct platform_device *pdev)
0094 {
0095     struct phy_provider *phy_provider;
0096     struct device *dev = &pdev->dev;
0097     struct phy *generic_phy;
0098     struct tegra_p2u *phy;
0099
0100     phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
0101     if (!phy)
0102         return -ENOMEM;
0103
0104     phy->of_data =
0105         (struct tegra_p2u_of_data *)of_device_get_match_data(dev);
0106     if (!phy->of_data)
0107         return -EINVAL;
0108
0109     phy->base = devm_platform_ioremap_resource_byname(pdev, "ctl");
0110     if (IS_ERR(phy->base))
0111         return PTR_ERR(phy->base);
0112
0113     phy->skip_sz_protection_en =
0114         of_property_read_bool(dev->of_node,
0115                       "nvidia,skip-sz-protect-en");
0116
0117     platform_set_drvdata(pdev, phy);
0118
0119     generic_phy = devm_phy_create(dev, NULL, &ops);
0120     if (IS_ERR(generic_phy))
0121         return PTR_ERR(generic_phy);
0122
0123     phy_set_drvdata(generic_phy, phy);
0124
0125     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0126     if (IS_ERR(phy_provider))
0127         return PTR_ERR(phy_provider);
0128
0129     return 0;
0130 }
0131
0132 static const struct tegra_p2u_of_data tegra194_p2u_of_data = {
0133     .one_dir_search = false,
0134 };
0135
0136 static const struct tegra_p2u_of_data tegra234_p2u_of_data = {
0137     .one_dir_search = true,
0138 };
0139
0140 static const struct of_device_id tegra_p2u_id_table[] = {
0141     {
0142         .compatible = "nvidia,tegra194-p2u",
0143         .data = &tegra194_p2u_of_data,
0144     },
0145     {
0146         .compatible = "nvidia,tegra234-p2u",
0147         .data = &tegra234_p2u_of_data,
0148     },
0149     {}
0150 };
0151 MODULE_DEVICE_TABLE(of, tegra_p2u_id_table);
0152
0153 static struct platform_driver tegra_p2u_driver = {
0154     .probe = tegra_p2u_probe,
0155     .driver = {
0156         .name = "tegra194-p2u",
0157         .of_match_table = tegra_p2u_id_table,
0158     },
0159 };
0160 module_platform_driver(tegra_p2u_driver);
0161
0162 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
0163 MODULE_DESCRIPTION("NVIDIA Tegra194 PIPE2UPHY PHY driver");
0164 MODULE_LICENSE("GPL v2");