phy/st/phy-stm32-usbphyc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * STMicroelectronics STM32 USB PHY Controller driver
0004  *
0005  * Copyright (C) 2018 STMicroelectronics
0006  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
0007  */
0008 #include <linux/bitfield.h>
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/delay.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/phy/phy.h>
0017 #include <linux/reset.h>
0018 #include <linux/units.h>
0019
0020 #define STM32_USBPHYC_PLL   0x0
0021 #define STM32_USBPHYC_MISC  0x8
0022 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
0023 #define STM32_USBPHYC_TUNE(X)   (0x10C + ((X) * 0x100))
0024 #define STM32_USBPHYC_VERSION   0x3F4
0025
0026 /* STM32_USBPHYC_PLL bit fields */
0027 #define PLLNDIV         GENMASK(6, 0)
0028 #define PLLFRACIN       GENMASK(25, 10)
0029 #define PLLEN           BIT(26)
0030 #define PLLSTRB         BIT(27)
0031 #define PLLSTRBYP       BIT(28)
0032 #define PLLFRACCTL      BIT(29)
0033 #define PLLDITHEN0      BIT(30)
0034 #define PLLDITHEN1      BIT(31)
0035
0036 /* STM32_USBPHYC_MISC bit fields */
0037 #define SWITHOST        BIT(0)
0038
0039 /* STM32_USBPHYC_MONITOR bit fields */
0040 #define STM32_USBPHYC_MON_OUT   GENMASK(3, 0)
0041 #define STM32_USBPHYC_MON_SEL   GENMASK(8, 4)
0042 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
0043 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
0044
0045 /* STM32_USBPHYC_TUNE bit fields */
0046 #define INCURREN        BIT(0)
0047 #define INCURRINT       BIT(1)
0048 #define LFSCAPEN        BIT(2)
0049 #define HSDRVSLEW       BIT(3)
0050 #define HSDRVDCCUR      BIT(4)
0051 #define HSDRVDCLEV      BIT(5)
0052 #define HSDRVCURINCR        BIT(6)
0053 #define FSDRVRFADJ      BIT(7)
0054 #define HSDRVRFRED      BIT(8)
0055 #define HSDRVCHKITRM        GENMASK(12, 9)
0056 #define HSDRVCHKZTRM        GENMASK(14, 13)
0057 #define OTPCOMP         GENMASK(19, 15)
0058 #define SQLCHCTL        GENMASK(21, 20)
0059 #define HDRXGNEQEN      BIT(22)
0060 #define HSRXOFF         GENMASK(24, 23)
0061 #define HSFALLPREEM     BIT(25)
0062 #define SHTCCTCTLPROT       BIT(26)
0063 #define STAGSEL         BIT(27)
0064
0065 enum boosting_vals {
0066     BOOST_1000_UA = 1000,
0067     BOOST_2000_UA = 2000,
0068 };
0069
0070 enum dc_level_vals {
0071     DC_NOMINAL,
0072     DC_PLUS_5_TO_7_MV,
0073     DC_PLUS_10_TO_14_MV,
0074     DC_MINUS_5_TO_7_MV,
0075     DC_MAX,
0076 };
0077
0078 enum current_trim {
0079     CUR_NOMINAL,
0080     CUR_PLUS_1_56_PCT,
0081     CUR_PLUS_3_12_PCT,
0082     CUR_PLUS_4_68_PCT,
0083     CUR_PLUS_6_24_PCT,
0084     CUR_PLUS_7_8_PCT,
0085     CUR_PLUS_9_36_PCT,
0086     CUR_PLUS_10_92_PCT,
0087     CUR_PLUS_12_48_PCT,
0088     CUR_PLUS_14_04_PCT,
0089     CUR_PLUS_15_6_PCT,
0090     CUR_PLUS_17_16_PCT,
0091     CUR_PLUS_19_01_PCT,
0092     CUR_PLUS_20_58_PCT,
0093     CUR_PLUS_22_16_PCT,
0094     CUR_PLUS_23_73_PCT,
0095     CUR_MAX,
0096 };
0097
0098 enum impedance_trim {
0099     IMP_NOMINAL,
0100     IMP_MINUS_2_OHMS,
0101     IMP_MINUS_4_OMHS,
0102     IMP_MINUS_6_OHMS,
0103     IMP_MAX,
0104 };
0105
0106 enum squelch_level {
0107     SQLCH_NOMINAL,
0108     SQLCH_PLUS_7_MV,
0109     SQLCH_MINUS_5_MV,
0110     SQLCH_PLUS_14_MV,
0111     SQLCH_MAX,
0112 };
0113
0114 enum rx_offset {
0115     NO_RX_OFFSET,
0116     RX_OFFSET_PLUS_5_MV,
0117     RX_OFFSET_PLUS_10_MV,
0118     RX_OFFSET_MINUS_5_MV,
0119     RX_OFFSET_MAX,
0120 };
0121
0122 /* STM32_USBPHYC_VERSION bit fields */
0123 #define MINREV          GENMASK(3, 0)
0124 #define MAJREV          GENMASK(7, 4)
0125
0126 #define PLL_FVCO_MHZ        2880
0127 #define PLL_INFF_MIN_RATE_HZ    19200000
0128 #define PLL_INFF_MAX_RATE_HZ    38400000
0129
0130 struct pll_params {
0131     u8 ndiv;
0132     u16 frac;
0133 };
0134
0135 struct stm32_usbphyc_phy {
0136     struct phy *phy;
0137     struct stm32_usbphyc *usbphyc;
0138     struct regulator *vbus;
0139     u32 index;
0140     bool active;
0141     u32 tune;
0142 };
0143
0144 struct stm32_usbphyc {
0145     struct device *dev;
0146     void __iomem *base;
0147     struct clk *clk;
0148     struct reset_control *rst;
0149     struct stm32_usbphyc_phy **phys;
0150     int nphys;
0151     struct regulator *vdda1v1;
0152     struct regulator *vdda1v8;
0153     atomic_t n_pll_cons;
0154     struct clk_hw clk48_hw;
0155     int switch_setup;
0156 };
0157
0158 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
0159 {
0160     writel_relaxed(readl_relaxed(reg) | bits, reg);
0161 }
0162
0163 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
0164 {
0165     writel_relaxed(readl_relaxed(reg) & ~bits, reg);
0166 }
0167
0168 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
0169 {
0170     int ret;
0171
0172     ret = regulator_enable(usbphyc->vdda1v1);
0173     if (ret)
0174         return ret;
0175
0176     ret = regulator_enable(usbphyc->vdda1v8);
0177     if (ret)
0178         goto vdda1v1_disable;
0179
0180     return 0;
0181
0182 vdda1v1_disable:
0183     regulator_disable(usbphyc->vdda1v1);
0184
0185     return ret;
0186 }
0187
0188 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
0189 {
0190     int ret;
0191
0192     ret = regulator_disable(usbphyc->vdda1v8);
0193     if (ret)
0194         return ret;
0195
0196     ret = regulator_disable(usbphyc->vdda1v1);
0197     if (ret)
0198         return ret;
0199
0200     return 0;
0201 }
0202
0203 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
0204                      struct pll_params *pll_params)
0205 {
0206     unsigned long long fvco, ndiv, frac;
0207
0208     /*    _
0209      *   | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
0210      *   | FVCO = 2880MHz
0211      *  <
0212      *   | NDIV = integer part of input bits to set the LDF
0213      *   |_FRACT = fractional part of input bits to set the LDF
0214      *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
0215      *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
0216      * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
0217      */
0218     fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
0219
0220     ndiv = fvco;
0221     do_div(ndiv, (clk_rate * 2));
0222     pll_params->ndiv = (u8)ndiv;
0223
0224     frac = fvco * (1 << 16);
0225     do_div(frac, (clk_rate * 2));
0226     frac = frac - (ndiv * (1 << 16));
0227     pll_params->frac = (u16)frac;
0228 }
0229
0230 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
0231 {
0232     struct pll_params pll_params;
0233     u32 clk_rate = clk_get_rate(usbphyc->clk);
0234     u32 ndiv, frac;
0235     u32 usbphyc_pll;
0236
0237     if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
0238         (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
0239         dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
0240             clk_rate);
0241         return -EINVAL;
0242     }
0243
0244     stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
0245     ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
0246     frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
0247
0248     usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
0249
0250     if (pll_params.frac)
0251         usbphyc_pll |= PLLFRACCTL | frac;
0252
0253     writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
0254
0255     dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
0256         clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
0257         FIELD_GET(PLLFRACIN, usbphyc_pll));
0258
0259     return 0;
0260 }
0261
0262 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
0263 {
0264     void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
0265     u32 pllen;
0266
0267     stm32_usbphyc_clr_bits(pll_reg, PLLEN);
0268
0269     /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
0270     if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
0271         dev_err(usbphyc->dev, "PLL not reset\n");
0272
0273     return stm32_usbphyc_regulators_disable(usbphyc);
0274 }
0275
0276 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
0277 {
0278     /* Check if a phy port is still active or clk48 in use */
0279     if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
0280         return 0;
0281
0282     return __stm32_usbphyc_pll_disable(usbphyc);
0283 }
0284
0285 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
0286 {
0287     void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
0288     bool pllen = readl_relaxed(pll_reg) & PLLEN;
0289     int ret;
0290
0291     /*
0292      * Check if a phy port or clk48 prepare has configured the pll
0293      * and ensure the PLL is enabled
0294      */
0295     if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
0296         return 0;
0297
0298     if (pllen) {
0299         /*
0300          * PLL shouldn't be enabled without known consumer,
0301          * disable it and reinit n_pll_cons
0302          */
0303         dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
0304
0305         ret = __stm32_usbphyc_pll_disable(usbphyc);
0306         if (ret)
0307             goto dec_n_pll_cons;
0308     }
0309
0310     ret = stm32_usbphyc_regulators_enable(usbphyc);
0311     if (ret)
0312         goto dec_n_pll_cons;
0313
0314     ret = stm32_usbphyc_pll_init(usbphyc);
0315     if (ret)
0316         goto reg_disable;
0317
0318     stm32_usbphyc_set_bits(pll_reg, PLLEN);
0319
0320     return 0;
0321
0322 reg_disable:
0323     stm32_usbphyc_regulators_disable(usbphyc);
0324
0325 dec_n_pll_cons:
0326     atomic_dec(&usbphyc->n_pll_cons);
0327
0328     return ret;
0329 }
0330
0331 static int stm32_usbphyc_phy_init(struct phy *phy)
0332 {
0333     struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
0334     struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
0335     u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
0336     u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
0337                 STM32_USBPHYC_MON_SEL_LOCKP);
0338     u32 monout;
0339     int ret;
0340
0341     ret = stm32_usbphyc_pll_enable(usbphyc);
0342     if (ret)
0343         return ret;
0344
0345     /* Check that PLL Lock input to PHY is High */
0346     writel_relaxed(monsel, usbphyc->base + reg_mon);
0347     ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
0348                      (monout & STM32_USBPHYC_MON_OUT_LOCKP),
0349                      100, 1000);
0350     if (ret) {
0351         dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
0352             (u32)(monout & STM32_USBPHYC_MON_OUT));
0353         goto pll_disable;
0354     }
0355
0356     usbphyc_phy->active = true;
0357
0358     return 0;
0359
0360 pll_disable:
0361     stm32_usbphyc_pll_disable(usbphyc);
0362
0363     return ret;
0364 }
0365
0366 static int stm32_usbphyc_phy_exit(struct phy *phy)
0367 {
0368     struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
0369     struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
0370
0371     usbphyc_phy->active = false;
0372
0373     return stm32_usbphyc_pll_disable(usbphyc);
0374 }
0375
0376 static int stm32_usbphyc_phy_power_on(struct phy *phy)
0377 {
0378     struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
0379
0380     if (usbphyc_phy->vbus)
0381         return regulator_enable(usbphyc_phy->vbus);
0382
0383     return 0;
0384 }
0385
0386 static int stm32_usbphyc_phy_power_off(struct phy *phy)
0387 {
0388     struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
0389
0390     if (usbphyc_phy->vbus)
0391         return regulator_disable(usbphyc_phy->vbus);
0392
0393     return 0;
0394 }
0395
0396 static const struct phy_ops stm32_usbphyc_phy_ops = {
0397     .init = stm32_usbphyc_phy_init,
0398     .exit = stm32_usbphyc_phy_exit,
0399     .power_on = stm32_usbphyc_phy_power_on,
0400     .power_off = stm32_usbphyc_phy_power_off,
0401     .owner = THIS_MODULE,
0402 };
0403
0404 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
0405 {
0406     struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
0407
0408     return stm32_usbphyc_pll_enable(usbphyc);
0409 }
0410
0411 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
0412 {
0413     struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
0414
0415     stm32_usbphyc_pll_disable(usbphyc);
0416 }
0417
0418 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
0419 {
0420     return 48000000;
0421 }
0422
0423 static const struct clk_ops usbphyc_clk48_ops = {
0424     .prepare = stm32_usbphyc_clk48_prepare,
0425     .unprepare = stm32_usbphyc_clk48_unprepare,
0426     .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
0427 };
0428
0429 static void stm32_usbphyc_clk48_unregister(void *data)
0430 {
0431     struct stm32_usbphyc *usbphyc = data;
0432
0433     of_clk_del_provider(usbphyc->dev->of_node);
0434     clk_hw_unregister(&usbphyc->clk48_hw);
0435 }
0436
0437 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
0438 {
0439     struct device_node *node = usbphyc->dev->of_node;
0440     struct clk_init_data init = { };
0441     int ret = 0;
0442
0443     init.name = "ck_usbo_48m";
0444     init.ops = &usbphyc_clk48_ops;
0445
0446     usbphyc->clk48_hw.init = &init;
0447
0448     ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
0449     if (ret)
0450         return ret;
0451
0452     ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
0453     if (ret)
0454         clk_hw_unregister(&usbphyc->clk48_hw);
0455
0456     return ret;
0457 }
0458
0459 static void stm32_usbphyc_phy_tuning(struct stm32_usbphyc *usbphyc,
0460                      struct device_node *np, u32 index)
0461 {
0462     struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys[index];
0463     u32 reg = STM32_USBPHYC_TUNE(index);
0464     u32 otpcomp, val;
0465     int ret;
0466
0467     /* Backup OTP compensation code */
0468     otpcomp = FIELD_GET(OTPCOMP, readl_relaxed(usbphyc->base + reg));
0469
0470     ret = of_property_read_u32(np, "st,current-boost-microamp", &val);
0471     if (ret != -EINVAL) {
0472         if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
0473             val = (val == BOOST_2000_UA) ? 1 : 0;
0474             usbphyc_phy->tune |= INCURREN | FIELD_PREP(INCURRINT, val);
0475         } else {
0476             dev_warn(usbphyc->dev, "phy%d: invalid st,current-boost-microamp\n", index);
0477         }
0478     }
0479
0480     if (!of_property_read_bool(np, "st,no-lsfs-fb-cap"))
0481         usbphyc_phy->tune |= LFSCAPEN;
0482
0483     if (of_property_read_bool(np, "st,decrease-hs-slew-rate"))
0484         usbphyc_phy->tune |= HSDRVSLEW;
0485
0486     ret = of_property_read_u32(np, "st,tune-hs-dc-level", &val);
0487     if (ret != -EINVAL) {
0488         if (!ret && val < DC_MAX) {
0489             if (val == DC_MINUS_5_TO_7_MV) {/* Decreases HS driver DC level */
0490                 usbphyc_phy->tune |= HSDRVDCCUR;
0491             } else if (val > 0) {       /* Increases HS driver DC level */
0492                 val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
0493                 usbphyc_phy->tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
0494             }
0495         } else {
0496             dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-dc-level\n", index);
0497         }
0498     }
0499
0500     if (of_property_read_bool(np, "st,enable-fs-rftime-tuning"))
0501         usbphyc_phy->tune |= FSDRVRFADJ;
0502
0503     if (of_property_read_bool(np, "st,enable-hs-rftime-reduction"))
0504         usbphyc_phy->tune |= HSDRVRFRED;
0505
0506     ret = of_property_read_u32(np, "st,trim-hs-current", &val);
0507     if (ret != -EINVAL) {
0508         if (!ret && val < CUR_MAX)
0509             usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKITRM, val);
0510         else
0511             dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-current\n", index);
0512     }
0513
0514     ret = of_property_read_u32(np, "st,trim-hs-impedance", &val);
0515     if (ret != -EINVAL) {
0516         if (!ret && val < IMP_MAX)
0517             usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKZTRM, val);
0518         else
0519             dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-impedance\n", index);
0520     }
0521
0522     ret = of_property_read_u32(np, "st,tune-squelch-level", &val);
0523     if (ret != -EINVAL) {
0524         if (!ret && val < SQLCH_MAX)
0525             usbphyc_phy->tune |= FIELD_PREP(SQLCHCTL, val);
0526         else
0527             dev_warn(usbphyc->dev, "phy%d: invalid st,tune-squelch\n", index);
0528     }
0529
0530     if (of_property_read_bool(np, "st,enable-hs-rx-gain-eq"))
0531         usbphyc_phy->tune |= HDRXGNEQEN;
0532
0533     ret = of_property_read_u32(np, "st,tune-hs-rx-offset", &val);
0534     if (ret != -EINVAL) {
0535         if (!ret && val < RX_OFFSET_MAX)
0536             usbphyc_phy->tune |= FIELD_PREP(HSRXOFF, val);
0537         else
0538             dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-rx-offset\n", index);
0539     }
0540
0541     if (of_property_read_bool(np, "st,no-hs-ftime-ctrl"))
0542         usbphyc_phy->tune |= HSFALLPREEM;
0543
0544     if (!of_property_read_bool(np, "st,no-lsfs-sc"))
0545         usbphyc_phy->tune |= SHTCCTCTLPROT;
0546
0547     if (of_property_read_bool(np, "st,enable-hs-tx-staggering"))
0548         usbphyc_phy->tune |= STAGSEL;
0549
0550     /* Restore OTP compensation code */
0551     usbphyc_phy->tune |= FIELD_PREP(OTPCOMP, otpcomp);
0552
0553     /*
0554      * By default, if no st,xxx tuning property is used, usbphyc_phy->tune is equal to
0555      * STM32_USBPHYC_TUNE reset value (LFSCAPEN | SHTCCTCTLPROT | OTPCOMP).
0556      */
0557     writel_relaxed(usbphyc_phy->tune, usbphyc->base + reg);
0558 }
0559
0560 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
0561                        u32 utmi_switch)
0562 {
0563     if (!utmi_switch)
0564         stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
0565                        SWITHOST);
0566     else
0567         stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
0568                        SWITHOST);
0569     usbphyc->switch_setup = utmi_switch;
0570 }
0571
0572 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
0573                       struct of_phandle_args *args)
0574 {
0575     struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
0576     struct stm32_usbphyc_phy *usbphyc_phy = NULL;
0577     struct device_node *phynode = args->np;
0578     int port = 0;
0579
0580     for (port = 0; port < usbphyc->nphys; port++) {
0581         if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
0582             usbphyc_phy = usbphyc->phys[port];
0583             break;
0584         }
0585     }
0586     if (!usbphyc_phy) {
0587         dev_err(dev, "failed to find phy\n");
0588         return ERR_PTR(-EINVAL);
0589     }
0590
0591     if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
0592         ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
0593         dev_err(dev, "invalid number of cells for phy port%d\n",
0594             usbphyc_phy->index);
0595         return ERR_PTR(-EINVAL);
0596     }
0597
0598     /* Configure the UTMI switch for PHY port#2 */
0599     if (usbphyc_phy->index == 1) {
0600         if (usbphyc->switch_setup < 0) {
0601             stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
0602         } else {
0603             if (args->args[0] != usbphyc->switch_setup) {
0604                 dev_err(dev, "phy port1 already used\n");
0605                 return ERR_PTR(-EBUSY);
0606             }
0607         }
0608     }
0609
0610     return usbphyc_phy->phy;
0611 }
0612
0613 static int stm32_usbphyc_probe(struct platform_device *pdev)
0614 {
0615     struct stm32_usbphyc *usbphyc;
0616     struct device *dev = &pdev->dev;
0617     struct device_node *child, *np = dev->of_node;
0618     struct phy_provider *phy_provider;
0619     u32 pllen, version;
0620     int ret, port = 0;
0621
0622     usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
0623     if (!usbphyc)
0624         return -ENOMEM;
0625     usbphyc->dev = dev;
0626     dev_set_drvdata(dev, usbphyc);
0627
0628     usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
0629     if (IS_ERR(usbphyc->base))
0630         return PTR_ERR(usbphyc->base);
0631
0632     usbphyc->clk = devm_clk_get(dev, NULL);
0633     if (IS_ERR(usbphyc->clk))
0634         return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
0635
0636     ret = clk_prepare_enable(usbphyc->clk);
0637     if (ret) {
0638         dev_err(dev, "clk enable failed: %d\n", ret);
0639         return ret;
0640     }
0641
0642     usbphyc->rst = devm_reset_control_get(dev, NULL);
0643     if (!IS_ERR(usbphyc->rst)) {
0644         reset_control_assert(usbphyc->rst);
0645         udelay(2);
0646         reset_control_deassert(usbphyc->rst);
0647     } else {
0648         ret = PTR_ERR(usbphyc->rst);
0649         if (ret == -EPROBE_DEFER)
0650             goto clk_disable;
0651
0652         stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
0653     }
0654
0655     /*
0656      * Wait for minimum width of powerdown pulse (ENABLE = Low):
0657      * we have to ensure the PLL is disabled before phys initialization.
0658      */
0659     if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
0660                        pllen, !(pllen & PLLEN), 5, 50)) {
0661         dev_warn(usbphyc->dev, "PLL not reset\n");
0662         ret = -EPROBE_DEFER;
0663         goto clk_disable;
0664     }
0665
0666     usbphyc->switch_setup = -EINVAL;
0667     usbphyc->nphys = of_get_child_count(np);
0668     usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
0669                      sizeof(*usbphyc->phys), GFP_KERNEL);
0670     if (!usbphyc->phys) {
0671         ret = -ENOMEM;
0672         goto clk_disable;
0673     }
0674
0675     usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
0676     if (IS_ERR(usbphyc->vdda1v1)) {
0677         ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v1),
0678                     "failed to get vdda1v1 supply\n");
0679         goto clk_disable;
0680     }
0681
0682     usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
0683     if (IS_ERR(usbphyc->vdda1v8)) {
0684         ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v8),
0685                     "failed to get vdda1v8 supply\n");
0686         goto clk_disable;
0687     }
0688
0689     for_each_child_of_node(np, child) {
0690         struct stm32_usbphyc_phy *usbphyc_phy;
0691         struct phy *phy;
0692         u32 index;
0693
0694         phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
0695         if (IS_ERR(phy)) {
0696             ret = PTR_ERR(phy);
0697             if (ret != -EPROBE_DEFER)
0698                 dev_err(dev, "failed to create phy%d: %d\n",
0699                     port, ret);
0700             goto put_child;
0701         }
0702
0703         usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
0704                        GFP_KERNEL);
0705         if (!usbphyc_phy) {
0706             ret = -ENOMEM;
0707             goto put_child;
0708         }
0709
0710         ret = of_property_read_u32(child, "reg", &index);
0711         if (ret || index > usbphyc->nphys) {
0712             dev_err(&phy->dev, "invalid reg property: %d\n", ret);
0713             goto put_child;
0714         }
0715
0716         usbphyc->phys[port] = usbphyc_phy;
0717         phy_set_bus_width(phy, 8);
0718         phy_set_drvdata(phy, usbphyc_phy);
0719
0720         usbphyc->phys[port]->phy = phy;
0721         usbphyc->phys[port]->usbphyc = usbphyc;
0722         usbphyc->phys[port]->index = index;
0723         usbphyc->phys[port]->active = false;
0724
0725         usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
0726         if (IS_ERR(usbphyc->phys[port]->vbus)) {
0727             ret = PTR_ERR(usbphyc->phys[port]->vbus);
0728             if (ret == -EPROBE_DEFER)
0729                 goto put_child;
0730             usbphyc->phys[port]->vbus = NULL;
0731         }
0732
0733         /* Configure phy tuning */
0734         stm32_usbphyc_phy_tuning(usbphyc, child, index);
0735
0736         port++;
0737     }
0738
0739     phy_provider = devm_of_phy_provider_register(dev,
0740                              stm32_usbphyc_of_xlate);
0741     if (IS_ERR(phy_provider)) {
0742         ret = PTR_ERR(phy_provider);
0743         dev_err(dev, "failed to register phy provider: %d\n", ret);
0744         goto clk_disable;
0745     }
0746
0747     ret = stm32_usbphyc_clk48_register(usbphyc);
0748     if (ret) {
0749         dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
0750         goto clk_disable;
0751     }
0752
0753     version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
0754     dev_info(dev, "registered rev:%lu.%lu\n",
0755          FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
0756
0757     return 0;
0758
0759 put_child:
0760     of_node_put(child);
0761 clk_disable:
0762     clk_disable_unprepare(usbphyc->clk);
0763
0764     return ret;
0765 }
0766
0767 static int stm32_usbphyc_remove(struct platform_device *pdev)
0768 {
0769     struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
0770     int port;
0771
0772     /* Ensure PHYs are not active, to allow PLL disabling */
0773     for (port = 0; port < usbphyc->nphys; port++)
0774         if (usbphyc->phys[port]->active)
0775             stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
0776
0777     stm32_usbphyc_clk48_unregister(usbphyc);
0778
0779     clk_disable_unprepare(usbphyc->clk);
0780
0781     return 0;
0782 }
0783
0784 static int __maybe_unused stm32_usbphyc_resume(struct device *dev)
0785 {
0786     struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
0787     struct stm32_usbphyc_phy *usbphyc_phy;
0788     int port;
0789
0790     if (usbphyc->switch_setup >= 0)
0791         stm32_usbphyc_switch_setup(usbphyc, usbphyc->switch_setup);
0792
0793     for (port = 0; port < usbphyc->nphys; port++) {
0794         usbphyc_phy = usbphyc->phys[port];
0795         writel_relaxed(usbphyc_phy->tune, usbphyc->base + STM32_USBPHYC_TUNE(port));
0796     }
0797
0798     return 0;
0799 }
0800
0801 static SIMPLE_DEV_PM_OPS(stm32_usbphyc_pm_ops, NULL, stm32_usbphyc_resume);
0802
0803 static const struct of_device_id stm32_usbphyc_of_match[] = {
0804     { .compatible = "st,stm32mp1-usbphyc", },
0805     { },
0806 };
0807 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
0808
0809 static struct platform_driver stm32_usbphyc_driver = {
0810     .probe = stm32_usbphyc_probe,
0811     .remove = stm32_usbphyc_remove,
0812     .driver = {
0813         .of_match_table = stm32_usbphyc_of_match,
0814         .name = "stm32-usbphyc",
0815         .pm = &stm32_usbphyc_pm_ops,
0816     }
0817 };
0818 module_platform_driver(stm32_usbphyc_driver);
0819
0820 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
0821 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
0822 MODULE_LICENSE("GPL v2");