phy/st/phy-spear1310-miphy.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ST SPEAr1310-miphy driver
0004  *
0005  * Copyright (C) 2014 ST Microelectronics
0006  * Pratyush Anand <pratyush.anand@gmail.com>
0007  * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
0008  */
0009
0010 #include <linux/bitops.h>
0011 #include <linux/delay.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/kernel.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/module.h>
0016 #include <linux/of_device.h>
0017 #include <linux/phy/phy.h>
0018 #include <linux/regmap.h>
0019
0020 /* SPEAr1310 Registers */
0021 #define SPEAR1310_PCIE_SATA_CFG         0x3A4
0022     #define SPEAR1310_PCIE_SATA2_SEL_PCIE       (0 << 31)
0023     #define SPEAR1310_PCIE_SATA1_SEL_PCIE       (0 << 30)
0024     #define SPEAR1310_PCIE_SATA0_SEL_PCIE       (0 << 29)
0025     #define SPEAR1310_PCIE_SATA2_SEL_SATA       BIT(31)
0026     #define SPEAR1310_PCIE_SATA1_SEL_SATA       BIT(30)
0027     #define SPEAR1310_PCIE_SATA0_SEL_SATA       BIT(29)
0028     #define SPEAR1310_SATA2_CFG_TX_CLK_EN       BIT(27)
0029     #define SPEAR1310_SATA2_CFG_RX_CLK_EN       BIT(26)
0030     #define SPEAR1310_SATA2_CFG_POWERUP_RESET   BIT(25)
0031     #define SPEAR1310_SATA2_CFG_PM_CLK_EN       BIT(24)
0032     #define SPEAR1310_SATA1_CFG_TX_CLK_EN       BIT(23)
0033     #define SPEAR1310_SATA1_CFG_RX_CLK_EN       BIT(22)
0034     #define SPEAR1310_SATA1_CFG_POWERUP_RESET   BIT(21)
0035     #define SPEAR1310_SATA1_CFG_PM_CLK_EN       BIT(20)
0036     #define SPEAR1310_SATA0_CFG_TX_CLK_EN       BIT(19)
0037     #define SPEAR1310_SATA0_CFG_RX_CLK_EN       BIT(18)
0038     #define SPEAR1310_SATA0_CFG_POWERUP_RESET   BIT(17)
0039     #define SPEAR1310_SATA0_CFG_PM_CLK_EN       BIT(16)
0040     #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT  BIT(11)
0041     #define SPEAR1310_PCIE2_CFG_POWERUP_RESET   BIT(10)
0042     #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN     BIT(9)
0043     #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN      BIT(8)
0044     #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT  BIT(7)
0045     #define SPEAR1310_PCIE1_CFG_POWERUP_RESET   BIT(6)
0046     #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN     BIT(5)
0047     #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN      BIT(4)
0048     #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT  BIT(3)
0049     #define SPEAR1310_PCIE0_CFG_POWERUP_RESET   BIT(2)
0050     #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN     BIT(1)
0051     #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN      BIT(0)
0052
0053     #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
0054     #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
0055             BIT((x + 29)))
0056     #define SPEAR1310_PCIE_CFG_VAL(x) \
0057             (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
0058             SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
0059             SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
0060             SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
0061             SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
0062     #define SPEAR1310_SATA_CFG_VAL(x) \
0063             (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
0064             SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
0065             SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
0066             SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
0067             SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
0068
0069 #define SPEAR1310_PCIE_MIPHY_CFG_1      0x3A8
0070     #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31)
0071     #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2   BIT(28)
0072     #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x)   (x << 16)
0073     #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT   BIT(15)
0074     #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12)
0075     #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
0076     #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
0077     #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
0078     #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
0079             (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
0080             SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
0081             SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
0082             SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
0083             SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
0084             SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
0085     #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
0086             (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
0087     #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
0088             (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
0089             SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
0090             SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
0091             SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
0092
0093 #define SPEAR1310_PCIE_MIPHY_CFG_2      0x3AC
0094
0095 enum spear1310_miphy_mode {
0096     SATA,
0097     PCIE,
0098 };
0099
0100 struct spear1310_miphy_priv {
0101     /* instance id of this phy */
0102     u32             id;
0103     /* phy mode: 0 for SATA 1 for PCIe */
0104     enum spear1310_miphy_mode   mode;
0105     /* regmap for any soc specific misc registers */
0106     struct regmap           *misc;
0107     /* phy struct pointer */
0108     struct phy          *phy;
0109 };
0110
0111 static int spear1310_miphy_pcie_init(struct spear1310_miphy_priv *priv)
0112 {
0113     u32 val;
0114
0115     regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
0116                SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
0117                SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
0118
0119     switch (priv->id) {
0120     case 0:
0121         val = SPEAR1310_PCIE_CFG_VAL(0);
0122         break;
0123     case 1:
0124         val = SPEAR1310_PCIE_CFG_VAL(1);
0125         break;
0126     case 2:
0127         val = SPEAR1310_PCIE_CFG_VAL(2);
0128         break;
0129     default:
0130         return -EINVAL;
0131     }
0132
0133     regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
0134                SPEAR1310_PCIE_CFG_MASK(priv->id), val);
0135
0136     return 0;
0137 }
0138
0139 static int spear1310_miphy_pcie_exit(struct spear1310_miphy_priv *priv)
0140 {
0141     regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
0142                SPEAR1310_PCIE_CFG_MASK(priv->id), 0);
0143
0144     regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
0145                SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
0146
0147     return 0;
0148 }
0149
0150 static int spear1310_miphy_init(struct phy *phy)
0151 {
0152     struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
0153     int ret = 0;
0154
0155     if (priv->mode == PCIE)
0156         ret = spear1310_miphy_pcie_init(priv);
0157
0158     return ret;
0159 }
0160
0161 static int spear1310_miphy_exit(struct phy *phy)
0162 {
0163     struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
0164     int ret = 0;
0165
0166     if (priv->mode == PCIE)
0167         ret = spear1310_miphy_pcie_exit(priv);
0168
0169     return ret;
0170 }
0171
0172 static const struct of_device_id spear1310_miphy_of_match[] = {
0173     { .compatible = "st,spear1310-miphy" },
0174     { },
0175 };
0176 MODULE_DEVICE_TABLE(of, spear1310_miphy_of_match);
0177
0178 static const struct phy_ops spear1310_miphy_ops = {
0179     .init = spear1310_miphy_init,
0180     .exit = spear1310_miphy_exit,
0181     .owner = THIS_MODULE,
0182 };
0183
0184 static struct phy *spear1310_miphy_xlate(struct device *dev,
0185                      struct of_phandle_args *args)
0186 {
0187     struct spear1310_miphy_priv *priv = dev_get_drvdata(dev);
0188
0189     if (args->args_count < 1) {
0190         dev_err(dev, "DT did not pass correct no of args\n");
0191         return ERR_PTR(-ENODEV);
0192     }
0193
0194     priv->mode = args->args[0];
0195
0196     if (priv->mode != SATA && priv->mode != PCIE) {
0197         dev_err(dev, "DT did not pass correct phy mode\n");
0198         return ERR_PTR(-ENODEV);
0199     }
0200
0201     return priv->phy;
0202 }
0203
0204 static int spear1310_miphy_probe(struct platform_device *pdev)
0205 {
0206     struct device *dev = &pdev->dev;
0207     struct spear1310_miphy_priv *priv;
0208     struct phy_provider *phy_provider;
0209
0210     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0211     if (!priv)
0212         return -ENOMEM;
0213
0214     priv->misc =
0215         syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
0216     if (IS_ERR(priv->misc)) {
0217         dev_err(dev, "failed to find misc regmap\n");
0218         return PTR_ERR(priv->misc);
0219     }
0220
0221     if (of_property_read_u32(dev->of_node, "phy-id", &priv->id)) {
0222         dev_err(dev, "failed to find phy id\n");
0223         return -EINVAL;
0224     }
0225
0226     priv->phy = devm_phy_create(dev, NULL, &spear1310_miphy_ops);
0227     if (IS_ERR(priv->phy)) {
0228         dev_err(dev, "failed to create SATA PCIe PHY\n");
0229         return PTR_ERR(priv->phy);
0230     }
0231
0232     dev_set_drvdata(dev, priv);
0233     phy_set_drvdata(priv->phy, priv);
0234
0235     phy_provider =
0236         devm_of_phy_provider_register(dev, spear1310_miphy_xlate);
0237     if (IS_ERR(phy_provider)) {
0238         dev_err(dev, "failed to register phy provider\n");
0239         return PTR_ERR(phy_provider);
0240     }
0241
0242     return 0;
0243 }
0244
0245 static struct platform_driver spear1310_miphy_driver = {
0246     .probe      = spear1310_miphy_probe,
0247     .driver = {
0248         .name = "spear1310-miphy",
0249         .of_match_table = of_match_ptr(spear1310_miphy_of_match),
0250     },
0251 };
0252
0253 module_platform_driver(spear1310_miphy_driver);
0254
0255 MODULE_DESCRIPTION("ST SPEAR1310-MIPHY driver");
0256 MODULE_AUTHOR("Pratyush Anand <pratyush.anand@gmail.com>");
0257 MODULE_LICENSE("GPL v2");