phy/socionext/phy-uniphier-pcie.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
0004  * Copyright 2018, Socionext Inc.
0005  * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
0006  */
0007
0008 #include <linux/bitops.h>
0009 #include <linux/bitfield.h>
0010 #include <linux/clk.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/phy/phy.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/regmap.h>
0018 #include <linux/reset.h>
0019 #include <linux/resource.h>
0020
0021 /* PHY */
0022 #define PCL_PHY_CLKCTRL     0x0000
0023 #define PORT_SEL_MASK       GENMASK(11, 9)
0024 #define PORT_SEL_1      FIELD_PREP(PORT_SEL_MASK, 1)
0025
0026 #define PCL_PHY_TEST_I      0x2000
0027 #define TESTI_DAT_MASK      GENMASK(13, 6)
0028 #define TESTI_ADR_MASK      GENMASK(5, 1)
0029 #define TESTI_WR_EN     BIT(0)
0030 #define TESTIO_PHY_SHIFT    16
0031
0032 #define PCL_PHY_TEST_O      0x2004
0033 #define TESTO_DAT_MASK      GENMASK(7, 0)
0034
0035 #define PCL_PHY_RESET       0x200c
0036 #define PCL_PHY_RESET_N_MNMODE  BIT(8)  /* =1:manual */
0037 #define PCL_PHY_RESET_N     BIT(0)  /* =1:deasssert */
0038
0039 /* SG */
0040 #define SG_USBPCIESEL       0x590
0041 #define SG_USBPCIESEL_PCIE  BIT(0)
0042
0043 /* SC */
0044 #define SC_US3SRCSEL        0x2244
0045 #define SC_US3SRCSEL_2LANE  GENMASK(9, 8)
0046
0047 #define PCL_PHY_R00     0
0048 #define   RX_EQ_ADJ_EN      BIT(3)      /* enable for EQ adjustment */
0049 #define PCL_PHY_R06     6
0050 #define   RX_EQ_ADJ     GENMASK(5, 0)   /* EQ adjustment value */
0051 #define   RX_EQ_ADJ_VAL     0
0052 #define PCL_PHY_R26     26
0053 #define   VCO_CTRL      GENMASK(7, 4)   /* Tx VCO adjustment value */
0054 #define   VCO_CTRL_INIT_VAL 5
0055 #define PCL_PHY_R28     28
0056 #define   VCOPLL_CLMP       GENMASK(3, 2)   /* Tx VCOPLL clamp mode */
0057 #define   VCOPLL_CLMP_VAL   0
0058
0059 struct uniphier_pciephy_priv {
0060     void __iomem *base;
0061     struct device *dev;
0062     struct clk *clk, *clk_gio;
0063     struct reset_control *rst, *rst_gio;
0064     const struct uniphier_pciephy_soc_data *data;
0065 };
0066
0067 struct uniphier_pciephy_soc_data {
0068     bool is_legacy;
0069     bool is_dual_phy;
0070     void (*set_phymode)(struct regmap *regmap);
0071 };
0072
0073 static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv,
0074                       int id, u32 data)
0075 {
0076     if (id)
0077         data <<= TESTIO_PHY_SHIFT;
0078
0079     /* need to read TESTO twice after accessing TESTI */
0080     writel(data, priv->base + PCL_PHY_TEST_I);
0081     readl(priv->base + PCL_PHY_TEST_O);
0082     readl(priv->base + PCL_PHY_TEST_O);
0083 }
0084
0085 static u32 uniphier_pciephy_testio_read(struct uniphier_pciephy_priv *priv, int id)
0086 {
0087     u32 val = readl(priv->base + PCL_PHY_TEST_O);
0088
0089     if (id)
0090         val >>= TESTIO_PHY_SHIFT;
0091
0092     return val & TESTO_DAT_MASK;
0093 }
0094
0095 static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv,
0096                        int id, u32 reg, u32 mask, u32 param)
0097 {
0098     u32 val;
0099
0100     /* read previous data */
0101     val  = FIELD_PREP(TESTI_DAT_MASK, 1);
0102     val |= FIELD_PREP(TESTI_ADR_MASK, reg);
0103     uniphier_pciephy_testio_write(priv, id, val);
0104     val = uniphier_pciephy_testio_read(priv, id);
0105
0106     /* update value */
0107     val &= ~mask;
0108     val |= mask & param;
0109     val = FIELD_PREP(TESTI_DAT_MASK, val);
0110     val |= FIELD_PREP(TESTI_ADR_MASK, reg);
0111     uniphier_pciephy_testio_write(priv, id, val);
0112     uniphier_pciephy_testio_write(priv, id, val | TESTI_WR_EN);
0113     uniphier_pciephy_testio_write(priv, id, val);
0114
0115     /* read current data as dummy */
0116     val  = FIELD_PREP(TESTI_DAT_MASK, 1);
0117     val |= FIELD_PREP(TESTI_ADR_MASK, reg);
0118     uniphier_pciephy_testio_write(priv, id, val);
0119     uniphier_pciephy_testio_read(priv, id);
0120 }
0121
0122 static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv)
0123 {
0124     u32 val;
0125
0126     val = readl(priv->base + PCL_PHY_RESET);
0127     val &= ~PCL_PHY_RESET_N;
0128     val |= PCL_PHY_RESET_N_MNMODE;
0129     writel(val, priv->base + PCL_PHY_RESET);
0130 }
0131
0132 static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv)
0133 {
0134     u32 val;
0135
0136     val = readl(priv->base + PCL_PHY_RESET);
0137     val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N;
0138     writel(val, priv->base + PCL_PHY_RESET);
0139 }
0140
0141 static int uniphier_pciephy_init(struct phy *phy)
0142 {
0143     struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
0144     u32 val;
0145     int ret, id;
0146
0147     ret = clk_prepare_enable(priv->clk);
0148     if (ret)
0149         return ret;
0150
0151     ret = clk_prepare_enable(priv->clk_gio);
0152     if (ret)
0153         goto out_clk_disable;
0154
0155     ret = reset_control_deassert(priv->rst);
0156     if (ret)
0157         goto out_clk_gio_disable;
0158
0159     ret = reset_control_deassert(priv->rst_gio);
0160     if (ret)
0161         goto out_rst_assert;
0162
0163     /* support only 1 port */
0164     val = readl(priv->base + PCL_PHY_CLKCTRL);
0165     val &= ~PORT_SEL_MASK;
0166     val |= PORT_SEL_1;
0167     writel(val, priv->base + PCL_PHY_CLKCTRL);
0168
0169     /* legacy controller doesn't have phy_reset and parameters */
0170     if (priv->data->is_legacy)
0171         return 0;
0172
0173     for (id = 0; id < (priv->data->is_dual_phy ? 2 : 1); id++) {
0174         uniphier_pciephy_set_param(priv, id, PCL_PHY_R00,
0175                    RX_EQ_ADJ_EN, RX_EQ_ADJ_EN);
0176         uniphier_pciephy_set_param(priv, id, PCL_PHY_R06, RX_EQ_ADJ,
0177                    FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL));
0178         uniphier_pciephy_set_param(priv, id, PCL_PHY_R26, VCO_CTRL,
0179                    FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL));
0180         uniphier_pciephy_set_param(priv, id, PCL_PHY_R28, VCOPLL_CLMP,
0181                    FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL));
0182     }
0183     usleep_range(1, 10);
0184
0185     uniphier_pciephy_deassert(priv);
0186     usleep_range(1, 10);
0187
0188     return 0;
0189
0190 out_rst_assert:
0191     reset_control_assert(priv->rst);
0192 out_clk_gio_disable:
0193     clk_disable_unprepare(priv->clk_gio);
0194 out_clk_disable:
0195     clk_disable_unprepare(priv->clk);
0196
0197     return ret;
0198 }
0199
0200 static int uniphier_pciephy_exit(struct phy *phy)
0201 {
0202     struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
0203
0204     if (!priv->data->is_legacy)
0205         uniphier_pciephy_assert(priv);
0206     reset_control_assert(priv->rst_gio);
0207     reset_control_assert(priv->rst);
0208     clk_disable_unprepare(priv->clk_gio);
0209     clk_disable_unprepare(priv->clk);
0210
0211     return 0;
0212 }
0213
0214 static const struct phy_ops uniphier_pciephy_ops = {
0215     .init  = uniphier_pciephy_init,
0216     .exit  = uniphier_pciephy_exit,
0217     .owner = THIS_MODULE,
0218 };
0219
0220 static int uniphier_pciephy_probe(struct platform_device *pdev)
0221 {
0222     struct uniphier_pciephy_priv *priv;
0223     struct phy_provider *phy_provider;
0224     struct device *dev = &pdev->dev;
0225     struct regmap *regmap;
0226     struct phy *phy;
0227
0228     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0229     if (!priv)
0230         return -ENOMEM;
0231
0232     priv->data = of_device_get_match_data(dev);
0233     if (WARN_ON(!priv->data))
0234         return -EINVAL;
0235
0236     priv->dev = dev;
0237
0238     priv->base = devm_platform_ioremap_resource(pdev, 0);
0239     if (IS_ERR(priv->base))
0240         return PTR_ERR(priv->base);
0241
0242     if (priv->data->is_legacy) {
0243         priv->clk_gio = devm_clk_get(dev, "gio");
0244         if (IS_ERR(priv->clk_gio))
0245             return PTR_ERR(priv->clk_gio);
0246
0247         priv->rst_gio =
0248             devm_reset_control_get_shared(dev, "gio");
0249         if (IS_ERR(priv->rst_gio))
0250             return PTR_ERR(priv->rst_gio);
0251
0252         priv->clk = devm_clk_get(dev, "link");
0253         if (IS_ERR(priv->clk))
0254             return PTR_ERR(priv->clk);
0255
0256         priv->rst = devm_reset_control_get_shared(dev, "link");
0257         if (IS_ERR(priv->rst))
0258             return PTR_ERR(priv->rst);
0259     } else {
0260         priv->clk = devm_clk_get(dev, NULL);
0261         if (IS_ERR(priv->clk))
0262             return PTR_ERR(priv->clk);
0263
0264         priv->rst = devm_reset_control_get_shared(dev, NULL);
0265         if (IS_ERR(priv->rst))
0266             return PTR_ERR(priv->rst);
0267     }
0268
0269     phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops);
0270     if (IS_ERR(phy))
0271         return PTR_ERR(phy);
0272
0273     regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
0274                          "socionext,syscon");
0275     if (!IS_ERR(regmap) && priv->data->set_phymode)
0276         priv->data->set_phymode(regmap);
0277
0278     phy_set_drvdata(phy, priv);
0279     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0280
0281     return PTR_ERR_OR_ZERO(phy_provider);
0282 }
0283
0284 static void uniphier_pciephy_ld20_setmode(struct regmap *regmap)
0285 {
0286     regmap_update_bits(regmap, SG_USBPCIESEL,
0287                SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
0288 }
0289
0290 static void uniphier_pciephy_nx1_setmode(struct regmap *regmap)
0291 {
0292     regmap_update_bits(regmap, SC_US3SRCSEL,
0293                SC_US3SRCSEL_2LANE, SC_US3SRCSEL_2LANE);
0294 }
0295
0296 static const struct uniphier_pciephy_soc_data uniphier_pro5_data = {
0297     .is_legacy = true,
0298 };
0299
0300 static const struct uniphier_pciephy_soc_data uniphier_ld20_data = {
0301     .is_legacy = false,
0302     .is_dual_phy = false,
0303     .set_phymode = uniphier_pciephy_ld20_setmode,
0304 };
0305
0306 static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = {
0307     .is_legacy = false,
0308     .is_dual_phy = false,
0309 };
0310
0311 static const struct uniphier_pciephy_soc_data uniphier_nx1_data = {
0312     .is_legacy = false,
0313     .is_dual_phy = true,
0314     .set_phymode = uniphier_pciephy_nx1_setmode,
0315 };
0316
0317 static const struct of_device_id uniphier_pciephy_match[] = {
0318     {
0319         .compatible = "socionext,uniphier-pro5-pcie-phy",
0320         .data = &uniphier_pro5_data,
0321     },
0322     {
0323         .compatible = "socionext,uniphier-ld20-pcie-phy",
0324         .data = &uniphier_ld20_data,
0325     },
0326     {
0327         .compatible = "socionext,uniphier-pxs3-pcie-phy",
0328         .data = &uniphier_pxs3_data,
0329     },
0330     {
0331         .compatible = "socionext,uniphier-nx1-pcie-phy",
0332         .data = &uniphier_nx1_data,
0333     },
0334     { /* sentinel */ },
0335 };
0336 MODULE_DEVICE_TABLE(of, uniphier_pciephy_match);
0337
0338 static struct platform_driver uniphier_pciephy_driver = {
0339     .probe = uniphier_pciephy_probe,
0340     .driver = {
0341         .name = "uniphier-pcie-phy",
0342         .of_match_table = uniphier_pciephy_match,
0343     },
0344 };
0345 module_platform_driver(uniphier_pciephy_driver);
0346
0347 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
0348 MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller");
0349 MODULE_LICENSE("GPL v2");