phy/samsung/phy-samsung-ufs.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * UFS PHY driver for Samsung SoC
0004  *
0005  * Copyright (C) 2020 Samsung Electronics Co., Ltd.
0006  * Author: Seungwon Jeon <essuuj@gmail.com>
0007  * Author: Alim Akhtar <alim.akhtar@samsung.com>
0008  *
0009  */
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/err.h>
0013 #include <linux/of.h>
0014 #include <linux/io.h>
0015 #include <linux/iopoll.h>
0016 #include <linux/mfd/syscon.h>
0017 #include <linux/module.h>
0018 #include <linux/phy/phy.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/regmap.h>
0021
0022 #include "phy-samsung-ufs.h"
0023
0024 #define for_each_phy_lane(phy, i) \
0025     for (i = 0; i < (phy)->lane_cnt; i++)
0026 #define for_each_phy_cfg(cfg) \
0027     for (; (cfg)->id; (cfg)++)
0028
0029 #define PHY_DEF_LANE_CNT    1
0030
0031 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
0032                    const struct samsung_ufs_phy_cfg *cfg,
0033                    u8 lane)
0034 {
0035     enum {LANE_0, LANE_1}; /* lane index */
0036
0037     switch (lane) {
0038     case LANE_0:
0039         writel(cfg->val, (phy)->reg_pma + cfg->off_0);
0040         break;
0041     case LANE_1:
0042         if (cfg->id == PHY_TRSV_BLK)
0043             writel(cfg->val, (phy)->reg_pma + cfg->off_1);
0044         break;
0045     }
0046 }
0047
0048 static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
0049 {
0050     struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
0051     const unsigned int timeout_us = 100000;
0052     const unsigned int sleep_us = 10;
0053     u32 val;
0054     int err;
0055
0056     err = readl_poll_timeout(
0057             ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
0058             val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
0059     if (err) {
0060         dev_err(ufs_phy->dev,
0061             "failed to get phy pll lock acquisition %d\n", err);
0062         goto out;
0063     }
0064
0065     err = readl_poll_timeout(
0066             ufs_phy->reg_pma +
0067             PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
0068             val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
0069     if (err)
0070         dev_err(ufs_phy->dev,
0071             "failed to get phy cdr lock acquisition %d\n", err);
0072 out:
0073     return err;
0074 }
0075
0076 static int samsung_ufs_phy_calibrate(struct phy *phy)
0077 {
0078     struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
0079     const struct samsung_ufs_phy_cfg * const *cfgs = ufs_phy->cfgs;
0080     const struct samsung_ufs_phy_cfg *cfg;
0081     int err = 0;
0082     int i;
0083
0084     if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
0085              ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
0086         dev_err(ufs_phy->dev, "invalid phy config index %d\n", ufs_phy->ufs_phy_state);
0087         return -EINVAL;
0088     }
0089
0090     cfg = cfgs[ufs_phy->ufs_phy_state];
0091     if (!cfg)
0092         goto out;
0093
0094     for_each_phy_cfg(cfg) {
0095         for_each_phy_lane(ufs_phy, i) {
0096             samsung_ufs_phy_config(ufs_phy, cfg, i);
0097         }
0098     }
0099
0100     if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
0101         err = samsung_ufs_phy_wait_for_lock_acq(phy);
0102
0103     /**
0104      * In Samsung ufshci, PHY need to be calibrated at different
0105      * stages / state mainly before Linkstartup, after Linkstartup,
0106      * before power mode change and after power mode change.
0107      * Below state machine to make sure to calibrate PHY in each
0108      * state. Here after configuring PHY in a given state, will
0109      * change the state to next state so that next state phy
0110      * calibration value can be programed
0111      */
0112 out:
0113     switch (ufs_phy->ufs_phy_state) {
0114     case CFG_PRE_INIT:
0115         ufs_phy->ufs_phy_state = CFG_POST_INIT;
0116         break;
0117     case CFG_POST_INIT:
0118         ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
0119         break;
0120     case CFG_PRE_PWR_HS:
0121         ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
0122         break;
0123     case CFG_POST_PWR_HS:
0124         /* Change back to INIT state */
0125         ufs_phy->ufs_phy_state = CFG_PRE_INIT;
0126         break;
0127     default:
0128         dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
0129     }
0130
0131     return err;
0132 }
0133
0134 static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
0135 {
0136     int i;
0137     const struct samsung_ufs_phy_drvdata *drvdata = phy->drvdata;
0138     int num_clks = drvdata->num_clks;
0139
0140     phy->clks = devm_kcalloc(phy->dev, num_clks, sizeof(*phy->clks),
0141                  GFP_KERNEL);
0142     if (!phy->clks)
0143         return -ENOMEM;
0144
0145     for (i = 0; i < num_clks; i++)
0146         phy->clks[i].id = drvdata->clk_list[i];
0147
0148     return devm_clk_bulk_get(phy->dev, num_clks, phy->clks);
0149 }
0150
0151 static int samsung_ufs_phy_init(struct phy *phy)
0152 {
0153     struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
0154
0155     ss_phy->lane_cnt = phy->attrs.bus_width;
0156     ss_phy->ufs_phy_state = CFG_PRE_INIT;
0157
0158     return 0;
0159 }
0160
0161 static int samsung_ufs_phy_power_on(struct phy *phy)
0162 {
0163     struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
0164     int ret;
0165
0166     samsung_ufs_phy_ctrl_isol(ss_phy, false);
0167
0168     ret = clk_bulk_prepare_enable(ss_phy->drvdata->num_clks, ss_phy->clks);
0169     if (ret) {
0170         dev_err(ss_phy->dev, "failed to enable ufs phy clocks\n");
0171         return ret;
0172     }
0173
0174     if (ss_phy->ufs_phy_state == CFG_PRE_INIT) {
0175         ret = samsung_ufs_phy_calibrate(phy);
0176         if (ret)
0177             dev_err(ss_phy->dev, "ufs phy calibration failed\n");
0178     }
0179
0180     return ret;
0181 }
0182
0183 static int samsung_ufs_phy_power_off(struct phy *phy)
0184 {
0185     struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
0186
0187     clk_bulk_disable_unprepare(ss_phy->drvdata->num_clks, ss_phy->clks);
0188
0189     samsung_ufs_phy_ctrl_isol(ss_phy, true);
0190
0191     return 0;
0192 }
0193
0194 static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
0195                     enum phy_mode mode, int submode)
0196 {
0197     struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(generic_phy);
0198
0199     ss_phy->mode = PHY_MODE_INVALID;
0200
0201     if (mode > 0)
0202         ss_phy->mode = mode;
0203
0204     return 0;
0205 }
0206
0207 static int samsung_ufs_phy_exit(struct phy *phy)
0208 {
0209     struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
0210
0211     ss_phy->ufs_phy_state = CFG_TAG_MAX;
0212
0213     return 0;
0214 }
0215
0216 static const struct phy_ops samsung_ufs_phy_ops = {
0217     .init       = samsung_ufs_phy_init,
0218     .exit       = samsung_ufs_phy_exit,
0219     .power_on   = samsung_ufs_phy_power_on,
0220     .power_off  = samsung_ufs_phy_power_off,
0221     .calibrate  = samsung_ufs_phy_calibrate,
0222     .set_mode   = samsung_ufs_phy_set_mode,
0223     .owner          = THIS_MODULE,
0224 };
0225
0226 static const struct of_device_id samsung_ufs_phy_match[];
0227
0228 static int samsung_ufs_phy_probe(struct platform_device *pdev)
0229 {
0230     struct device *dev = &pdev->dev;
0231     const struct of_device_id *match;
0232     struct samsung_ufs_phy *phy;
0233     struct phy *gen_phy;
0234     struct phy_provider *phy_provider;
0235     const struct samsung_ufs_phy_drvdata *drvdata;
0236     u32 isol_offset;
0237     int err = 0;
0238
0239     match = of_match_node(samsung_ufs_phy_match, dev->of_node);
0240     if (!match) {
0241         err = -EINVAL;
0242         dev_err(dev, "failed to get match_node\n");
0243         goto out;
0244     }
0245
0246     phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
0247     if (!phy) {
0248         err = -ENOMEM;
0249         goto out;
0250     }
0251
0252     phy->reg_pma = devm_platform_ioremap_resource_byname(pdev, "phy-pma");
0253     if (IS_ERR(phy->reg_pma)) {
0254         err = PTR_ERR(phy->reg_pma);
0255         goto out;
0256     }
0257
0258     phy->reg_pmu = syscon_regmap_lookup_by_phandle(
0259                 dev->of_node, "samsung,pmu-syscon");
0260     if (IS_ERR(phy->reg_pmu)) {
0261         err = PTR_ERR(phy->reg_pmu);
0262         dev_err(dev, "failed syscon remap for pmu\n");
0263         goto out;
0264     }
0265
0266     gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
0267     if (IS_ERR(gen_phy)) {
0268         err = PTR_ERR(gen_phy);
0269         dev_err(dev, "failed to create PHY for ufs-phy\n");
0270         goto out;
0271     }
0272
0273     drvdata = match->data;
0274     phy->dev = dev;
0275     phy->drvdata = drvdata;
0276     phy->cfgs = drvdata->cfgs;
0277     memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol));
0278
0279     if (!of_property_read_u32_index(dev->of_node, "samsung,pmu-syscon", 1,
0280                     &isol_offset))
0281         phy->isol.offset = isol_offset;
0282
0283     phy->lane_cnt = PHY_DEF_LANE_CNT;
0284
0285     err = samsung_ufs_phy_clks_init(phy);
0286     if (err) {
0287         dev_err(dev, "failed to get phy clocks\n");
0288         goto out;
0289     }
0290
0291     phy_set_drvdata(gen_phy, phy);
0292
0293     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0294     if (IS_ERR(phy_provider)) {
0295         err = PTR_ERR(phy_provider);
0296         dev_err(dev, "failed to register phy-provider\n");
0297         goto out;
0298     }
0299 out:
0300     return err;
0301 }
0302
0303 static const struct of_device_id samsung_ufs_phy_match[] = {
0304     {
0305         .compatible = "samsung,exynos7-ufs-phy",
0306         .data = &exynos7_ufs_phy,
0307     }, {
0308         .compatible = "samsung,exynosautov9-ufs-phy",
0309         .data = &exynosautov9_ufs_phy,
0310     }, {
0311         .compatible = "tesla,fsd-ufs-phy",
0312         .data = &fsd_ufs_phy,
0313     },
0314     {},
0315 };
0316 MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
0317
0318 static struct platform_driver samsung_ufs_phy_driver = {
0319     .probe  = samsung_ufs_phy_probe,
0320     .driver = {
0321         .name = "samsung-ufs-phy",
0322         .of_match_table = samsung_ufs_phy_match,
0323     },
0324 };
0325 module_platform_driver(samsung_ufs_phy_driver);
0326 MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
0327 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
0328 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
0329 MODULE_LICENSE("GPL v2");