phy/samsung/phy-fsd-ufs.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * UFS PHY driver data for FSD SoC
0004  *
0005  * Copyright (C) 2022 Samsung Electronics Co., Ltd.
0006  *
0007  */
0008 #include "phy-samsung-ufs.h"
0009
0010 #define FSD_EMBEDDED_COMBO_PHY_CTRL 0x724
0011 #define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK    0x1
0012 #define FSD_EMBEDDED_COMBO_PHY_CTRL_EN  BIT(0)
0013 #define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS  0x6e
0014
0015 static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {
0016     PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
0017     PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
0018     PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
0019     PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
0020     PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
0021     PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
0022     PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
0023     PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
0024     PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
0025     PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
0026     PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
0027     PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
0028     PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
0029     PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
0030     END_UFS_PHY_CFG
0031 };
0032
0033 /* Calibration for HS mode series A/B */
0034 static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {
0035     END_UFS_PHY_CFG
0036 };
0037
0038 /* Calibration for HS mode series A/B atfer PMC */
0039 static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {
0040     END_UFS_PHY_CFG
0041 };
0042
0043 static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {
0044     [CFG_PRE_INIT]      = fsd_pre_init_cfg,
0045     [CFG_PRE_PWR_HS]    = fsd_pre_pwr_hs_cfg,
0046     [CFG_POST_PWR_HS]   = fsd_post_pwr_hs_cfg,
0047 };
0048
0049 static const char * const fsd_ufs_phy_clks[] = {
0050     "ref_clk",
0051 };
0052
0053 const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
0054     .cfgs = fsd_ufs_phy_cfgs,
0055     .isol = {
0056         .offset = FSD_EMBEDDED_COMBO_PHY_CTRL,
0057         .mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,
0058         .en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,
0059     },
0060     .clk_list = fsd_ufs_phy_clks,
0061     .num_clks = ARRAY_SIZE(fsd_ufs_phy_clks),
0062     .cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
0063 };