phy/samsung/phy-exynosautov9-ufs.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * UFS PHY driver data for Samsung EXYNOSAUTO v9 SoC
0004  *
0005  * Copyright (C) 2021 Samsung Electronics Co., Ltd.
0006  */
0007
0008 #include "phy-samsung-ufs.h"
0009
0010 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL        0x728
0011 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK   0x1
0012 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN     BIT(0)
0013 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
0014
0015 #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
0016     PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
0017
0018 /* Calibration for phy initialization */
0019 static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = {
0020     PHY_COMN_REG_CFG(0x023, 0x80, PWR_MODE_ANY),
0021     PHY_COMN_REG_CFG(0x01d, 0x10, PWR_MODE_ANY),
0022
0023     PHY_TRSV_REG_CFG_AUTOV9(0x044, 0xb5, PWR_MODE_ANY),
0024     PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x43, PWR_MODE_ANY),
0025     PHY_TRSV_REG_CFG_AUTOV9(0x05b, 0x20, PWR_MODE_ANY),
0026     PHY_TRSV_REG_CFG_AUTOV9(0x05e, 0xc0, PWR_MODE_ANY),
0027     PHY_TRSV_REG_CFG_AUTOV9(0x038, 0x12, PWR_MODE_ANY),
0028     PHY_TRSV_REG_CFG_AUTOV9(0x059, 0x58, PWR_MODE_ANY),
0029     PHY_TRSV_REG_CFG_AUTOV9(0x06c, 0x18, PWR_MODE_ANY),
0030     PHY_TRSV_REG_CFG_AUTOV9(0x06d, 0x02, PWR_MODE_ANY),
0031
0032     PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
0033     PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),
0034
0035     PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
0036     PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),
0037
0038     END_UFS_PHY_CFG,
0039 };
0040
0041 /* Calibration for HS mode series A/B */
0042 static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
0043     PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
0044     PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
0045     PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),
0046
0047     PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
0048     PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
0049                 PWR_MODE_HS_G3_SER_B),
0050     PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
0051
0052     END_UFS_PHY_CFG,
0053 };
0054
0055 static const struct samsung_ufs_phy_cfg *exynosautov9_ufs_phy_cfgs[CFG_TAG_MAX] = {
0056     [CFG_PRE_INIT]      = exynosautov9_pre_init_cfg,
0057     [CFG_PRE_PWR_HS]    = exynosautov9_pre_pwr_hs_cfg,
0058 };
0059
0060 static const char * const exynosautov9_ufs_phy_clks[] = {
0061     "ref_clk",
0062 };
0063
0064 const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
0065     .cfgs = exynosautov9_ufs_phy_cfgs,
0066     .isol = {
0067         .offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL,
0068         .mask = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK,
0069         .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
0070     },
0071     .clk_list = exynosautov9_ufs_phy_clks,
0072     .num_clks = ARRAY_SIZE(exynosautov9_ufs_phy_clks),
0073     .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
0074 };