phy/samsung/phy-exynos7-ufs.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * UFS PHY driver data for Samsung EXYNOS7 SoC
0004  *
0005  * Copyright (C) 2020 Samsung Electronics Co., Ltd.
0006  */
0007
0008 #include "phy-samsung-ufs.h"
0009
0010 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
0011 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK    0x1
0012 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN  BIT(0)
0013
0014 #define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS  0x5e
0015
0016 /* Calibration for phy initialization */
0017 static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
0018     PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
0019     PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
0020     PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
0021     PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
0022     PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
0023     PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
0024     PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
0025     PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
0026     PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
0027     PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
0028     PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
0029     PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
0030     PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
0031     PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
0032     END_UFS_PHY_CFG
0033 };
0034
0035 /* Calibration for HS mode series A/B */
0036 static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
0037     PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
0038     PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
0039     PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
0040     /* Setting order: 1st(0x16, 2nd(0x15) */
0041     PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
0042     PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
0043     PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
0044     PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
0045     PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
0046     PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
0047     PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
0048     PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
0049     PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
0050     PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
0051     PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
0052     PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
0053     PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
0054     PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
0055     END_UFS_PHY_CFG
0056 };
0057
0058 /* Calibration for HS mode series A/B atfer PMC */
0059 static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
0060     PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
0061     PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
0062     END_UFS_PHY_CFG
0063 };
0064
0065 static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
0066     [CFG_PRE_INIT]      = exynos7_pre_init_cfg,
0067     [CFG_PRE_PWR_HS]    = exynos7_pre_pwr_hs_cfg,
0068     [CFG_POST_PWR_HS]   = exynos7_post_pwr_hs_cfg,
0069 };
0070
0071 static const char * const exynos7_ufs_phy_clks[] = {
0072     "tx0_symbol_clk", "rx0_symbol_clk", "rx1_symbol_clk", "ref_clk",
0073 };
0074
0075 const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
0076     .cfgs = exynos7_ufs_phy_cfgs,
0077     .isol = {
0078         .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
0079         .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
0080         .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
0081     },
0082     .clk_list = exynos7_ufs_phy_clks,
0083     .num_clks = ARRAY_SIZE(exynos7_ufs_phy_clks),
0084     .cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
0085 };