phy/samsung/phy-exynos-mipi-video.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
0004  *
0005  * Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
0006  * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
0007  */
0008
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_device.h>
0016 #include <linux/phy/phy.h>
0017 #include <linux/regmap.h>
0018 #include <linux/spinlock.h>
0019 #include <linux/soc/samsung/exynos-regs-pmu.h>
0020 #include <linux/mfd/syscon.h>
0021
0022 enum exynos_mipi_phy_id {
0023     EXYNOS_MIPI_PHY_ID_NONE = -1,
0024     EXYNOS_MIPI_PHY_ID_CSIS0,
0025     EXYNOS_MIPI_PHY_ID_DSIM0,
0026     EXYNOS_MIPI_PHY_ID_CSIS1,
0027     EXYNOS_MIPI_PHY_ID_DSIM1,
0028     EXYNOS_MIPI_PHY_ID_CSIS2,
0029     EXYNOS_MIPI_PHYS_NUM
0030 };
0031
0032 enum exynos_mipi_phy_regmap_id {
0033     EXYNOS_MIPI_REGMAP_PMU,
0034     EXYNOS_MIPI_REGMAP_DISP,
0035     EXYNOS_MIPI_REGMAP_CAM0,
0036     EXYNOS_MIPI_REGMAP_CAM1,
0037     EXYNOS_MIPI_REGMAPS_NUM
0038 };
0039
0040 struct mipi_phy_device_desc {
0041     int num_phys;
0042     int num_regmaps;
0043     const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
0044     struct exynos_mipi_phy_desc {
0045         enum exynos_mipi_phy_id coupled_phy_id;
0046         u32 enable_val;
0047         unsigned int enable_reg;
0048         enum exynos_mipi_phy_regmap_id enable_map;
0049         u32 resetn_val;
0050         unsigned int resetn_reg;
0051         enum exynos_mipi_phy_regmap_id resetn_map;
0052     } phys[EXYNOS_MIPI_PHYS_NUM];
0053 };
0054
0055 static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
0056     .num_regmaps = 1,
0057     .regmap_names = {"syscon"},
0058     .num_phys = 4,
0059     .phys = {
0060         {
0061             /* EXYNOS_MIPI_PHY_ID_CSIS0 */
0062             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
0063             .enable_val = EXYNOS4_PHY_ENABLE,
0064             .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
0065             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0066             .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
0067             .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
0068             .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
0069         }, {
0070             /* EXYNOS_MIPI_PHY_ID_DSIM0 */
0071             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
0072             .enable_val = EXYNOS4_PHY_ENABLE,
0073             .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
0074             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0075             .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
0076             .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
0077             .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
0078         }, {
0079             /* EXYNOS_MIPI_PHY_ID_CSIS1 */
0080             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
0081             .enable_val = EXYNOS4_PHY_ENABLE,
0082             .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
0083             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0084             .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
0085             .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
0086             .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
0087         }, {
0088             /* EXYNOS_MIPI_PHY_ID_DSIM1 */
0089             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
0090             .enable_val = EXYNOS4_PHY_ENABLE,
0091             .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
0092             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0093             .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
0094             .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
0095             .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
0096         },
0097     },
0098 };
0099
0100 static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
0101     .num_regmaps = 1,
0102     .regmap_names = {"syscon"},
0103     .num_phys = 5,
0104     .phys = {
0105         {
0106             /* EXYNOS_MIPI_PHY_ID_CSIS0 */
0107             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
0108             .enable_val = EXYNOS4_PHY_ENABLE,
0109             .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
0110             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0111             .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
0112             .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
0113             .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
0114         }, {
0115             /* EXYNOS_MIPI_PHY_ID_DSIM0 */
0116             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
0117             .enable_val = EXYNOS4_PHY_ENABLE,
0118             .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
0119             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0120             .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
0121             .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
0122             .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
0123         }, {
0124             /* EXYNOS_MIPI_PHY_ID_CSIS1 */
0125             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
0126             .enable_val = EXYNOS4_PHY_ENABLE,
0127             .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
0128             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0129             .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
0130             .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
0131             .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
0132         }, {
0133             /* EXYNOS_MIPI_PHY_ID_DSIM1 */
0134             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
0135             .enable_val = EXYNOS4_PHY_ENABLE,
0136             .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
0137             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0138             .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
0139             .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
0140             .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
0141         }, {
0142             /* EXYNOS_MIPI_PHY_ID_CSIS2 */
0143             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
0144             .enable_val = EXYNOS4_PHY_ENABLE,
0145             .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
0146             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0147             .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
0148             .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
0149             .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
0150         },
0151     },
0152 };
0153
0154 #define EXYNOS5433_SYSREG_DISP_MIPI_PHY     0x100C
0155 #define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON    0x1014
0156 #define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON    0x1020
0157
0158 static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
0159     .num_regmaps = 4,
0160     .regmap_names = {
0161         "samsung,pmu-syscon",
0162         "samsung,disp-sysreg",
0163         "samsung,cam0-sysreg",
0164         "samsung,cam1-sysreg"
0165     },
0166     .num_phys = 5,
0167     .phys = {
0168         {
0169             /* EXYNOS_MIPI_PHY_ID_CSIS0 */
0170             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
0171             .enable_val = EXYNOS4_PHY_ENABLE,
0172             .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
0173             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0174             .resetn_val = BIT(0),
0175             .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
0176             .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
0177         }, {
0178             /* EXYNOS_MIPI_PHY_ID_DSIM0 */
0179             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
0180             .enable_val = EXYNOS4_PHY_ENABLE,
0181             .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
0182             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0183             .resetn_val = BIT(0),
0184             .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
0185             .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
0186         }, {
0187             /* EXYNOS_MIPI_PHY_ID_CSIS1 */
0188             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
0189             .enable_val = EXYNOS4_PHY_ENABLE,
0190             .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
0191             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0192             .resetn_val = BIT(1),
0193             .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
0194             .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
0195         }, {
0196             /* EXYNOS_MIPI_PHY_ID_DSIM1 */
0197             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
0198             .enable_val = EXYNOS4_PHY_ENABLE,
0199             .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
0200             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0201             .resetn_val = BIT(1),
0202             .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
0203             .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
0204         }, {
0205             /* EXYNOS_MIPI_PHY_ID_CSIS2 */
0206             .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
0207             .enable_val = EXYNOS4_PHY_ENABLE,
0208             .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2),
0209             .enable_map = EXYNOS_MIPI_REGMAP_PMU,
0210             .resetn_val = BIT(0),
0211             .resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
0212             .resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
0213         },
0214     },
0215 };
0216
0217 struct exynos_mipi_video_phy {
0218     struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
0219     int num_phys;
0220     struct video_phy_desc {
0221         struct phy *phy;
0222         unsigned int index;
0223         const struct exynos_mipi_phy_desc *data;
0224     } phys[EXYNOS_MIPI_PHYS_NUM];
0225     spinlock_t slock;
0226 };
0227
0228 static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
0229                struct exynos_mipi_video_phy *state, unsigned int on)
0230 {
0231     struct regmap *enable_map = state->regmaps[data->enable_map];
0232     struct regmap *resetn_map = state->regmaps[data->resetn_map];
0233
0234     spin_lock(&state->slock);
0235
0236     /* disable in PMU sysreg */
0237     if (!on && data->coupled_phy_id >= 0 &&
0238         state->phys[data->coupled_phy_id].phy->power_count == 0)
0239         regmap_update_bits(enable_map, data->enable_reg,
0240                    data->enable_val, 0);
0241     /* PHY reset */
0242     if (on)
0243         regmap_update_bits(resetn_map, data->resetn_reg,
0244                    data->resetn_val, data->resetn_val);
0245     else
0246         regmap_update_bits(resetn_map, data->resetn_reg,
0247                    data->resetn_val, 0);
0248     /* enable in PMU sysreg */
0249     if (on)
0250         regmap_update_bits(enable_map, data->enable_reg,
0251                    data->enable_val, data->enable_val);
0252
0253     spin_unlock(&state->slock);
0254
0255     return 0;
0256 }
0257
0258 #define to_mipi_video_phy(desc) \
0259     container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
0260
0261 static int exynos_mipi_video_phy_power_on(struct phy *phy)
0262 {
0263     struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
0264     struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
0265
0266     return __set_phy_state(phy_desc->data, state, 1);
0267 }
0268
0269 static int exynos_mipi_video_phy_power_off(struct phy *phy)
0270 {
0271     struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
0272     struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
0273
0274     return __set_phy_state(phy_desc->data, state, 0);
0275 }
0276
0277 static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
0278                     struct of_phandle_args *args)
0279 {
0280     struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
0281
0282     if (WARN_ON(args->args[0] >= state->num_phys))
0283         return ERR_PTR(-ENODEV);
0284
0285     return state->phys[args->args[0]].phy;
0286 }
0287
0288 static const struct phy_ops exynos_mipi_video_phy_ops = {
0289     .power_on   = exynos_mipi_video_phy_power_on,
0290     .power_off  = exynos_mipi_video_phy_power_off,
0291     .owner      = THIS_MODULE,
0292 };
0293
0294 static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
0295 {
0296     const struct mipi_phy_device_desc *phy_dev;
0297     struct exynos_mipi_video_phy *state;
0298     struct device *dev = &pdev->dev;
0299     struct device_node *np = dev->of_node;
0300     struct phy_provider *phy_provider;
0301     unsigned int i;
0302
0303     phy_dev = of_device_get_match_data(dev);
0304     if (!phy_dev)
0305         return -ENODEV;
0306
0307     state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
0308     if (!state)
0309         return -ENOMEM;
0310
0311     for (i = 0; i < phy_dev->num_regmaps; i++) {
0312         state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
0313                         phy_dev->regmap_names[i]);
0314         if (IS_ERR(state->regmaps[i]))
0315             return PTR_ERR(state->regmaps[i]);
0316     }
0317     state->num_phys = phy_dev->num_phys;
0318     spin_lock_init(&state->slock);
0319
0320     dev_set_drvdata(dev, state);
0321
0322     for (i = 0; i < state->num_phys; i++) {
0323         struct phy *phy = devm_phy_create(dev, NULL,
0324                           &exynos_mipi_video_phy_ops);
0325         if (IS_ERR(phy)) {
0326             dev_err(dev, "failed to create PHY %d\n", i);
0327             return PTR_ERR(phy);
0328         }
0329
0330         state->phys[i].phy = phy;
0331         state->phys[i].index = i;
0332         state->phys[i].data = &phy_dev->phys[i];
0333         phy_set_drvdata(phy, &state->phys[i]);
0334     }
0335
0336     phy_provider = devm_of_phy_provider_register(dev,
0337                     exynos_mipi_video_phy_xlate);
0338
0339     return PTR_ERR_OR_ZERO(phy_provider);
0340 }
0341
0342 static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
0343     {
0344         .compatible = "samsung,s5pv210-mipi-video-phy",
0345         .data = &s5pv210_mipi_phy,
0346     }, {
0347         .compatible = "samsung,exynos5420-mipi-video-phy",
0348         .data = &exynos5420_mipi_phy,
0349     }, {
0350         .compatible = "samsung,exynos5433-mipi-video-phy",
0351         .data = &exynos5433_mipi_phy,
0352     },
0353     { /* sentinel */ },
0354 };
0355 MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
0356
0357 static struct platform_driver exynos_mipi_video_phy_driver = {
0358     .probe  = exynos_mipi_video_phy_probe,
0359     .driver = {
0360         .of_match_table = exynos_mipi_video_phy_of_match,
0361         .name  = "exynos-mipi-video-phy",
0362         .suppress_bind_attrs = true,
0363     }
0364 };
0365 module_platform_driver(exynos_mipi_video_phy_driver);
0366
0367 MODULE_DESCRIPTION("Samsung S5P/Exynos SoC MIPI CSI-2/DSI PHY driver");
0368 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
0369 MODULE_LICENSE("GPL v2");