phy/rockchip/phy-rockchip-pcie.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Rockchip PCIe PHY driver
0004  *
0005  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
0006  * Copyright (C) 2016 ROCKCHIP, Inc.
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/io.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/phy/phy.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regmap.h>
0020 #include <linux/reset.h>
0021
0022 /*
0023  * The higher 16-bit of this register is used for write protection
0024  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
0025  */
0026 #define HIWORD_UPDATE(val, mask, shift) \
0027         ((val) << (shift) | (mask) << ((shift) + 16))
0028
0029 #define PHY_MAX_LANE_NUM      4
0030 #define PHY_CFG_DATA_SHIFT    7
0031 #define PHY_CFG_ADDR_SHIFT    1
0032 #define PHY_CFG_DATA_MASK     0xf
0033 #define PHY_CFG_ADDR_MASK     0x3f
0034 #define PHY_CFG_RD_MASK       0x3ff
0035 #define PHY_CFG_WR_ENABLE     1
0036 #define PHY_CFG_WR_DISABLE    1
0037 #define PHY_CFG_WR_SHIFT      0
0038 #define PHY_CFG_WR_MASK       1
0039 #define PHY_CFG_PLL_LOCK      0x10
0040 #define PHY_CFG_CLK_TEST      0x10
0041 #define PHY_CFG_CLK_SCC       0x12
0042 #define PHY_CFG_SEPE_RATE     BIT(3)
0043 #define PHY_CFG_PLL_100M      BIT(3)
0044 #define PHY_PLL_LOCKED        BIT(9)
0045 #define PHY_PLL_OUTPUT        BIT(10)
0046 #define PHY_LANE_A_STATUS     0x30
0047 #define PHY_LANE_B_STATUS     0x31
0048 #define PHY_LANE_C_STATUS     0x32
0049 #define PHY_LANE_D_STATUS     0x33
0050 #define PHY_LANE_RX_DET_SHIFT 11
0051 #define PHY_LANE_RX_DET_TH    0x1
0052 #define PHY_LANE_IDLE_OFF     0x1
0053 #define PHY_LANE_IDLE_MASK    0x1
0054 #define PHY_LANE_IDLE_A_SHIFT 3
0055 #define PHY_LANE_IDLE_B_SHIFT 4
0056 #define PHY_LANE_IDLE_C_SHIFT 5
0057 #define PHY_LANE_IDLE_D_SHIFT 6
0058
0059 struct rockchip_pcie_data {
0060     unsigned int pcie_conf;
0061     unsigned int pcie_status;
0062     unsigned int pcie_laneoff;
0063 };
0064
0065 struct rockchip_pcie_phy {
0066     struct rockchip_pcie_data *phy_data;
0067     struct regmap *reg_base;
0068     struct phy_pcie_instance {
0069         struct phy *phy;
0070         u32 index;
0071     } phys[PHY_MAX_LANE_NUM];
0072     struct mutex pcie_mutex;
0073     struct reset_control *phy_rst;
0074     struct clk *clk_pciephy_ref;
0075     int pwr_cnt;
0076     int init_cnt;
0077 };
0078
0079 static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
0080 {
0081     return container_of(inst, struct rockchip_pcie_phy,
0082                     phys[inst->index]);
0083 }
0084
0085 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev,
0086                           struct of_phandle_args *args)
0087 {
0088     struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
0089
0090     if (args->args_count == 0)
0091         return rk_phy->phys[0].phy;
0092
0093     if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
0094         return ERR_PTR(-ENODEV);
0095
0096     return rk_phy->phys[args->args[0]].phy;
0097 }
0098
0099
0100 static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
0101                   u32 addr, u32 data)
0102 {
0103     regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
0104              HIWORD_UPDATE(data,
0105                    PHY_CFG_DATA_MASK,
0106                    PHY_CFG_DATA_SHIFT) |
0107              HIWORD_UPDATE(addr,
0108                    PHY_CFG_ADDR_MASK,
0109                    PHY_CFG_ADDR_SHIFT));
0110     udelay(1);
0111     regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
0112              HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
0113                    PHY_CFG_WR_MASK,
0114                    PHY_CFG_WR_SHIFT));
0115     udelay(1);
0116     regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
0117              HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
0118                    PHY_CFG_WR_MASK,
0119                    PHY_CFG_WR_SHIFT));
0120 }
0121
0122 static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
0123                  u32 addr)
0124 {
0125     u32 val;
0126
0127     regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
0128              HIWORD_UPDATE(addr,
0129                    PHY_CFG_RD_MASK,
0130                    PHY_CFG_ADDR_SHIFT));
0131     regmap_read(rk_phy->reg_base,
0132             rk_phy->phy_data->pcie_status,
0133             &val);
0134     return val;
0135 }
0136
0137 static int rockchip_pcie_phy_power_off(struct phy *phy)
0138 {
0139     struct phy_pcie_instance *inst = phy_get_drvdata(phy);
0140     struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
0141     int err = 0;
0142
0143     mutex_lock(&rk_phy->pcie_mutex);
0144
0145     regmap_write(rk_phy->reg_base,
0146              rk_phy->phy_data->pcie_laneoff,
0147              HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
0148                    PHY_LANE_IDLE_MASK,
0149                    PHY_LANE_IDLE_A_SHIFT + inst->index));
0150
0151     if (--rk_phy->pwr_cnt)
0152         goto err_out;
0153
0154     err = reset_control_assert(rk_phy->phy_rst);
0155     if (err) {
0156         dev_err(&phy->dev, "assert phy_rst err %d\n", err);
0157         goto err_restore;
0158     }
0159
0160 err_out:
0161     mutex_unlock(&rk_phy->pcie_mutex);
0162     return 0;
0163
0164 err_restore:
0165     rk_phy->pwr_cnt++;
0166     regmap_write(rk_phy->reg_base,
0167              rk_phy->phy_data->pcie_laneoff,
0168              HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
0169                    PHY_LANE_IDLE_MASK,
0170                    PHY_LANE_IDLE_A_SHIFT + inst->index));
0171     mutex_unlock(&rk_phy->pcie_mutex);
0172     return err;
0173 }
0174
0175 static int rockchip_pcie_phy_power_on(struct phy *phy)
0176 {
0177     struct phy_pcie_instance *inst = phy_get_drvdata(phy);
0178     struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
0179     int err = 0;
0180     u32 status;
0181     unsigned long timeout;
0182
0183     mutex_lock(&rk_phy->pcie_mutex);
0184
0185     if (rk_phy->pwr_cnt++)
0186         goto err_out;
0187
0188     err = reset_control_deassert(rk_phy->phy_rst);
0189     if (err) {
0190         dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
0191         goto err_pwr_cnt;
0192     }
0193
0194     regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
0195              HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
0196                    PHY_CFG_ADDR_MASK,
0197                    PHY_CFG_ADDR_SHIFT));
0198
0199     regmap_write(rk_phy->reg_base,
0200              rk_phy->phy_data->pcie_laneoff,
0201              HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
0202                    PHY_LANE_IDLE_MASK,
0203                    PHY_LANE_IDLE_A_SHIFT + inst->index));
0204
0205     /*
0206      * No documented timeout value for phy operation below,
0207      * so we make it large enough here. And we use loop-break
0208      * method which should not be harmful.
0209      */
0210     timeout = jiffies + msecs_to_jiffies(1000);
0211
0212     err = -EINVAL;
0213     while (time_before(jiffies, timeout)) {
0214         regmap_read(rk_phy->reg_base,
0215                 rk_phy->phy_data->pcie_status,
0216                 &status);
0217         if (status & PHY_PLL_LOCKED) {
0218             dev_dbg(&phy->dev, "pll locked!\n");
0219             err = 0;
0220             break;
0221         }
0222         msleep(20);
0223     }
0224
0225     if (err) {
0226         dev_err(&phy->dev, "pll lock timeout!\n");
0227         goto err_pll_lock;
0228     }
0229
0230     phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
0231     phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
0232
0233     err = -ETIMEDOUT;
0234     while (time_before(jiffies, timeout)) {
0235         regmap_read(rk_phy->reg_base,
0236                 rk_phy->phy_data->pcie_status,
0237                 &status);
0238         if (!(status & PHY_PLL_OUTPUT)) {
0239             dev_dbg(&phy->dev, "pll output enable done!\n");
0240             err = 0;
0241             break;
0242         }
0243         msleep(20);
0244     }
0245
0246     if (err) {
0247         dev_err(&phy->dev, "pll output enable timeout!\n");
0248         goto err_pll_lock;
0249     }
0250
0251     regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
0252              HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
0253                    PHY_CFG_ADDR_MASK,
0254                    PHY_CFG_ADDR_SHIFT));
0255     err = -EINVAL;
0256     while (time_before(jiffies, timeout)) {
0257         regmap_read(rk_phy->reg_base,
0258                 rk_phy->phy_data->pcie_status,
0259                 &status);
0260         if (status & PHY_PLL_LOCKED) {
0261             dev_dbg(&phy->dev, "pll relocked!\n");
0262             err = 0;
0263             break;
0264         }
0265         msleep(20);
0266     }
0267
0268     if (err) {
0269         dev_err(&phy->dev, "pll relock timeout!\n");
0270         goto err_pll_lock;
0271     }
0272
0273 err_out:
0274     mutex_unlock(&rk_phy->pcie_mutex);
0275     return 0;
0276
0277 err_pll_lock:
0278     reset_control_assert(rk_phy->phy_rst);
0279 err_pwr_cnt:
0280     rk_phy->pwr_cnt--;
0281     mutex_unlock(&rk_phy->pcie_mutex);
0282     return err;
0283 }
0284
0285 static int rockchip_pcie_phy_init(struct phy *phy)
0286 {
0287     struct phy_pcie_instance *inst = phy_get_drvdata(phy);
0288     struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
0289     int err = 0;
0290
0291     mutex_lock(&rk_phy->pcie_mutex);
0292
0293     if (rk_phy->init_cnt++)
0294         goto err_out;
0295
0296     err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
0297     if (err) {
0298         dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
0299         goto err_refclk;
0300     }
0301
0302     err = reset_control_assert(rk_phy->phy_rst);
0303     if (err) {
0304         dev_err(&phy->dev, "assert phy_rst err %d\n", err);
0305         goto err_reset;
0306     }
0307
0308 err_out:
0309     mutex_unlock(&rk_phy->pcie_mutex);
0310     return 0;
0311
0312 err_reset:
0313
0314     clk_disable_unprepare(rk_phy->clk_pciephy_ref);
0315 err_refclk:
0316     rk_phy->init_cnt--;
0317     mutex_unlock(&rk_phy->pcie_mutex);
0318     return err;
0319 }
0320
0321 static int rockchip_pcie_phy_exit(struct phy *phy)
0322 {
0323     struct phy_pcie_instance *inst = phy_get_drvdata(phy);
0324     struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
0325
0326     mutex_lock(&rk_phy->pcie_mutex);
0327
0328     if (--rk_phy->init_cnt)
0329         goto err_init_cnt;
0330
0331     clk_disable_unprepare(rk_phy->clk_pciephy_ref);
0332
0333 err_init_cnt:
0334     mutex_unlock(&rk_phy->pcie_mutex);
0335     return 0;
0336 }
0337
0338 static const struct phy_ops ops = {
0339     .init       = rockchip_pcie_phy_init,
0340     .exit       = rockchip_pcie_phy_exit,
0341     .power_on   = rockchip_pcie_phy_power_on,
0342     .power_off  = rockchip_pcie_phy_power_off,
0343     .owner      = THIS_MODULE,
0344 };
0345
0346 static const struct rockchip_pcie_data rk3399_pcie_data = {
0347     .pcie_conf = 0xe220,
0348     .pcie_status = 0xe2a4,
0349     .pcie_laneoff = 0xe214,
0350 };
0351
0352 static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
0353     {
0354         .compatible = "rockchip,rk3399-pcie-phy",
0355         .data = &rk3399_pcie_data,
0356     },
0357     {}
0358 };
0359
0360 MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
0361
0362 static int rockchip_pcie_phy_probe(struct platform_device *pdev)
0363 {
0364     struct device *dev = &pdev->dev;
0365     struct rockchip_pcie_phy *rk_phy;
0366     struct phy_provider *phy_provider;
0367     struct regmap *grf;
0368     const struct of_device_id *of_id;
0369     int i;
0370     u32 phy_num;
0371
0372     grf = syscon_node_to_regmap(dev->parent->of_node);
0373     if (IS_ERR(grf)) {
0374         dev_err(dev, "Cannot find GRF syscon\n");
0375         return PTR_ERR(grf);
0376     }
0377
0378     rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
0379     if (!rk_phy)
0380         return -ENOMEM;
0381
0382     of_id = of_match_device(rockchip_pcie_phy_dt_ids, &pdev->dev);
0383     if (!of_id)
0384         return -EINVAL;
0385
0386     rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data;
0387     rk_phy->reg_base = grf;
0388
0389     mutex_init(&rk_phy->pcie_mutex);
0390
0391     rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
0392     if (IS_ERR(rk_phy->phy_rst)) {
0393         if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
0394             dev_err(dev,
0395                 "missing phy property for reset controller\n");
0396         return PTR_ERR(rk_phy->phy_rst);
0397     }
0398
0399     rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
0400     if (IS_ERR(rk_phy->clk_pciephy_ref)) {
0401         dev_err(dev, "refclk not found.\n");
0402         return PTR_ERR(rk_phy->clk_pciephy_ref);
0403     }
0404
0405     /* parse #phy-cells to see if it's legacy PHY model */
0406     if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
0407         return -ENOENT;
0408
0409     phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
0410     dev_dbg(dev, "phy number is %d\n", phy_num);
0411
0412     for (i = 0; i < phy_num; i++) {
0413         rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
0414         if (IS_ERR(rk_phy->phys[i].phy)) {
0415             dev_err(dev, "failed to create PHY%d\n", i);
0416             return PTR_ERR(rk_phy->phys[i].phy);
0417         }
0418         rk_phy->phys[i].index = i;
0419         phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
0420     }
0421
0422     platform_set_drvdata(pdev, rk_phy);
0423     phy_provider = devm_of_phy_provider_register(dev,
0424                     rockchip_pcie_phy_of_xlate);
0425
0426     return PTR_ERR_OR_ZERO(phy_provider);
0427 }
0428
0429 static struct platform_driver rockchip_pcie_driver = {
0430     .probe      = rockchip_pcie_phy_probe,
0431     .driver     = {
0432         .name   = "rockchip-pcie-phy",
0433         .of_match_table = rockchip_pcie_phy_dt_ids,
0434     },
0435 };
0436
0437 module_platform_driver(rockchip_pcie_driver);
0438
0439 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
0440 MODULE_DESCRIPTION("Rockchip PCIe PHY driver");
0441 MODULE_LICENSE("GPL v2");