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0008 #include <dt-bindings/phy/phy.h>
0009 #include <linux/clk.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/of_device.h>
0012 #include <linux/phy/phy.h>
0013 #include <linux/regmap.h>
0014 #include <linux/reset.h>
0015 #include <linux/units.h>
0016
0017 #define BIT_WRITEABLE_SHIFT 16
0018 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ)
0019 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ)
0020 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
0021
0022
0023 #define PHYREG6 0x14
0024 #define PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
0025 #define PHYREG6_PLL_DIV_SHIFT 6
0026 #define PHYREG6_PLL_DIV_2 1
0027
0028 #define PHYREG7 0x18
0029 #define PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
0030 #define PHYREG7_TX_RTERM_SHIFT 4
0031 #define PHYREG7_TX_RTERM_50OHM 8
0032 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
0033 #define PHYREG7_RX_RTERM_SHIFT 0
0034 #define PHYREG7_RX_RTERM_44OHM 15
0035
0036 #define PHYREG8 0x1C
0037 #define PHYREG8_SSC_EN BIT(4)
0038
0039 #define PHYREG11 0x28
0040 #define PHYREG11_SU_TRIM_0_7 0xF0
0041
0042 #define PHYREG12 0x2C
0043 #define PHYREG12_PLL_LPF_ADJ_VALUE 4
0044
0045 #define PHYREG13 0x30
0046 #define PHYREG13_RESISTER_MASK GENMASK(5, 4)
0047 #define PHYREG13_RESISTER_SHIFT 0x4
0048 #define PHYREG13_RESISTER_HIGH_Z 3
0049 #define PHYREG13_CKRCV_AMP0 BIT(7)
0050
0051 #define PHYREG14 0x34
0052 #define PHYREG14_CKRCV_AMP1 BIT(0)
0053
0054 #define PHYREG15 0x38
0055 #define PHYREG15_CTLE_EN BIT(0)
0056 #define PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
0057 #define PHYREG15_SSC_CNT_SHIFT 6
0058 #define PHYREG15_SSC_CNT_VALUE 1
0059
0060 #define PHYREG16 0x3C
0061 #define PHYREG16_SSC_CNT_VALUE 0x5f
0062
0063 #define PHYREG18 0x44
0064 #define PHYREG18_PLL_LOOP 0x32
0065
0066 #define PHYREG32 0x7C
0067 #define PHYREG32_SSC_MASK GENMASK(7, 4)
0068 #define PHYREG32_SSC_DIR_SHIFT 4
0069 #define PHYREG32_SSC_UPWARD 0
0070 #define PHYREG32_SSC_DOWNWARD 1
0071 #define PHYREG32_SSC_OFFSET_SHIFT 6
0072 #define PHYREG32_SSC_OFFSET_500PPM 1
0073
0074 #define PHYREG33 0x80
0075 #define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
0076 #define PHYREG33_PLL_KVCO_SHIFT 2
0077 #define PHYREG33_PLL_KVCO_VALUE 2
0078
0079 struct rockchip_combphy_priv;
0080
0081 struct combphy_reg {
0082 u16 offset;
0083 u16 bitend;
0084 u16 bitstart;
0085 u16 disable;
0086 u16 enable;
0087 };
0088
0089 struct rockchip_combphy_grfcfg {
0090 struct combphy_reg pcie_mode_set;
0091 struct combphy_reg usb_mode_set;
0092 struct combphy_reg sgmii_mode_set;
0093 struct combphy_reg qsgmii_mode_set;
0094 struct combphy_reg pipe_rxterm_set;
0095 struct combphy_reg pipe_txelec_set;
0096 struct combphy_reg pipe_txcomp_set;
0097 struct combphy_reg pipe_clk_25m;
0098 struct combphy_reg pipe_clk_100m;
0099 struct combphy_reg pipe_phymode_sel;
0100 struct combphy_reg pipe_rate_sel;
0101 struct combphy_reg pipe_rxterm_sel;
0102 struct combphy_reg pipe_txelec_sel;
0103 struct combphy_reg pipe_txcomp_sel;
0104 struct combphy_reg pipe_clk_ext;
0105 struct combphy_reg pipe_sel_usb;
0106 struct combphy_reg pipe_sel_qsgmii;
0107 struct combphy_reg pipe_phy_status;
0108 struct combphy_reg con0_for_pcie;
0109 struct combphy_reg con1_for_pcie;
0110 struct combphy_reg con2_for_pcie;
0111 struct combphy_reg con3_for_pcie;
0112 struct combphy_reg con0_for_sata;
0113 struct combphy_reg con1_for_sata;
0114 struct combphy_reg con2_for_sata;
0115 struct combphy_reg con3_for_sata;
0116 struct combphy_reg pipe_con0_for_sata;
0117 struct combphy_reg pipe_xpcs_phy_ready;
0118 };
0119
0120 struct rockchip_combphy_cfg {
0121 const struct rockchip_combphy_grfcfg *grfcfg;
0122 int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
0123 };
0124
0125 struct rockchip_combphy_priv {
0126 u8 type;
0127 void __iomem *mmio;
0128 int num_clks;
0129 struct clk_bulk_data *clks;
0130 struct device *dev;
0131 struct regmap *pipe_grf;
0132 struct regmap *phy_grf;
0133 struct phy *phy;
0134 struct reset_control *phy_rst;
0135 const struct rockchip_combphy_cfg *cfg;
0136 bool enable_ssc;
0137 bool ext_refclk;
0138 struct clk *refclk;
0139 };
0140
0141 static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
0142 int mask, int val, int reg)
0143 {
0144 unsigned int temp;
0145
0146 temp = readl(priv->mmio + reg);
0147 temp = (temp & ~(mask)) | val;
0148 writel(temp, priv->mmio + reg);
0149 }
0150
0151 static int rockchip_combphy_param_write(struct regmap *base,
0152 const struct combphy_reg *reg, bool en)
0153 {
0154 u32 val, mask, tmp;
0155
0156 tmp = en ? reg->enable : reg->disable;
0157 mask = GENMASK(reg->bitend, reg->bitstart);
0158 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
0159
0160 return regmap_write(base, reg->offset, val);
0161 }
0162
0163 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
0164 {
0165 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
0166 u32 mask, val;
0167
0168 mask = GENMASK(cfg->pipe_phy_status.bitend,
0169 cfg->pipe_phy_status.bitstart);
0170
0171 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
0172 val = (val & mask) >> cfg->pipe_phy_status.bitstart;
0173
0174 return val;
0175 }
0176
0177 static int rockchip_combphy_init(struct phy *phy)
0178 {
0179 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
0180 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
0181 u32 val;
0182 int ret;
0183
0184 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
0185 if (ret) {
0186 dev_err(priv->dev, "failed to enable clks\n");
0187 return ret;
0188 }
0189
0190 switch (priv->type) {
0191 case PHY_TYPE_PCIE:
0192 case PHY_TYPE_USB3:
0193 case PHY_TYPE_SATA:
0194 case PHY_TYPE_SGMII:
0195 case PHY_TYPE_QSGMII:
0196 if (priv->cfg->combphy_cfg)
0197 ret = priv->cfg->combphy_cfg(priv);
0198 break;
0199 default:
0200 dev_err(priv->dev, "incompatible PHY type\n");
0201 ret = -EINVAL;
0202 break;
0203 }
0204
0205 if (ret) {
0206 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
0207 goto err_clk;
0208 }
0209
0210 ret = reset_control_deassert(priv->phy_rst);
0211 if (ret)
0212 goto err_clk;
0213
0214 if (priv->type == PHY_TYPE_USB3) {
0215 ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
0216 priv, val,
0217 val == cfg->pipe_phy_status.enable,
0218 10, 1000);
0219 if (ret)
0220 dev_warn(priv->dev, "wait phy status ready timeout\n");
0221 }
0222
0223 return 0;
0224
0225 err_clk:
0226 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
0227
0228 return ret;
0229 }
0230
0231 static int rockchip_combphy_exit(struct phy *phy)
0232 {
0233 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
0234
0235 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
0236 reset_control_assert(priv->phy_rst);
0237
0238 return 0;
0239 }
0240
0241 static const struct phy_ops rochchip_combphy_ops = {
0242 .init = rockchip_combphy_init,
0243 .exit = rockchip_combphy_exit,
0244 .owner = THIS_MODULE,
0245 };
0246
0247 static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
0248 {
0249 struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
0250
0251 if (args->args_count != 1) {
0252 dev_err(dev, "invalid number of arguments\n");
0253 return ERR_PTR(-EINVAL);
0254 }
0255
0256 if (priv->type != PHY_NONE && priv->type != args->args[0])
0257 dev_warn(dev, "phy type select %d overwriting type %d\n",
0258 args->args[0], priv->type);
0259
0260 priv->type = args->args[0];
0261
0262 return priv->phy;
0263 }
0264
0265 static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
0266 {
0267 int i;
0268
0269 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
0270 if (priv->num_clks < 1)
0271 return -EINVAL;
0272
0273 priv->refclk = NULL;
0274 for (i = 0; i < priv->num_clks; i++) {
0275 if (!strncmp(priv->clks[i].id, "ref", 3)) {
0276 priv->refclk = priv->clks[i].clk;
0277 break;
0278 }
0279 }
0280
0281 if (!priv->refclk) {
0282 dev_err(dev, "no refclk found\n");
0283 return -EINVAL;
0284 }
0285
0286 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
0287 if (IS_ERR(priv->pipe_grf)) {
0288 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
0289 return PTR_ERR(priv->pipe_grf);
0290 }
0291
0292 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
0293 if (IS_ERR(priv->phy_grf)) {
0294 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
0295 return PTR_ERR(priv->phy_grf);
0296 }
0297
0298 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
0299
0300 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
0301
0302 priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
0303 if (IS_ERR(priv->phy_rst))
0304 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
0305
0306 return 0;
0307 }
0308
0309 static int rockchip_combphy_probe(struct platform_device *pdev)
0310 {
0311 struct phy_provider *phy_provider;
0312 struct device *dev = &pdev->dev;
0313 struct rockchip_combphy_priv *priv;
0314 const struct rockchip_combphy_cfg *phy_cfg;
0315 struct resource *res;
0316 int ret;
0317
0318 phy_cfg = of_device_get_match_data(dev);
0319 if (!phy_cfg) {
0320 dev_err(dev, "no OF match data provided\n");
0321 return -EINVAL;
0322 }
0323
0324 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0325 if (!priv)
0326 return -ENOMEM;
0327
0328 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0329 if (IS_ERR(priv->mmio)) {
0330 ret = PTR_ERR(priv->mmio);
0331 return ret;
0332 }
0333
0334 priv->dev = dev;
0335 priv->type = PHY_NONE;
0336 priv->cfg = phy_cfg;
0337
0338 ret = rockchip_combphy_parse_dt(dev, priv);
0339 if (ret)
0340 return ret;
0341
0342 ret = reset_control_assert(priv->phy_rst);
0343 if (ret) {
0344 dev_err(dev, "failed to reset phy\n");
0345 return ret;
0346 }
0347
0348 priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
0349 if (IS_ERR(priv->phy)) {
0350 dev_err(dev, "failed to create combphy\n");
0351 return PTR_ERR(priv->phy);
0352 }
0353
0354 dev_set_drvdata(dev, priv);
0355 phy_set_drvdata(priv->phy, priv);
0356
0357 phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
0358
0359 return PTR_ERR_OR_ZERO(phy_provider);
0360 }
0361
0362 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
0363 {
0364 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
0365 unsigned long rate;
0366 u32 val;
0367
0368 switch (priv->type) {
0369 case PHY_TYPE_PCIE:
0370
0371 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
0372 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
0373 PHYREG32);
0374
0375 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
0376 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
0377 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
0378 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
0379 break;
0380
0381 case PHY_TYPE_USB3:
0382
0383 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
0384 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
0385 PHYREG32);
0386
0387
0388 val = readl(priv->mmio + PHYREG15);
0389 val |= PHYREG15_CTLE_EN;
0390 writel(val, priv->mmio + PHYREG15);
0391
0392
0393 rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
0394 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
0395 PHYREG33);
0396
0397
0398 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
0399
0400
0401 rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
0402 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
0403 PHYREG6);
0404
0405 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
0406 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
0407
0408 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
0409 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
0410 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
0411 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
0412 break;
0413
0414 case PHY_TYPE_SATA:
0415
0416 val = readl(priv->mmio + PHYREG15);
0417 val |= PHYREG15_CTLE_EN;
0418 writel(val, priv->mmio + PHYREG15);
0419
0420
0421
0422
0423 val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
0424 val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
0425 writel(val, priv->mmio + PHYREG7);
0426
0427 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
0428 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
0429 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
0430 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
0431 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
0432 break;
0433
0434 case PHY_TYPE_SGMII:
0435 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
0436 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
0437 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
0438 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
0439 break;
0440
0441 case PHY_TYPE_QSGMII:
0442 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
0443 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
0444 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
0445 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
0446 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
0447 break;
0448
0449 default:
0450 dev_err(priv->dev, "incompatible PHY type\n");
0451 return -EINVAL;
0452 }
0453
0454 rate = clk_get_rate(priv->refclk);
0455
0456 switch (rate) {
0457 case REF_CLOCK_24MHz:
0458 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
0459
0460 val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
0461 rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
0462 val, PHYREG15);
0463
0464 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
0465 }
0466 break;
0467
0468 case REF_CLOCK_25MHz:
0469 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
0470 break;
0471
0472 case REF_CLOCK_100MHz:
0473 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
0474 if (priv->type == PHY_TYPE_PCIE) {
0475
0476 val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
0477 rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
0478 val, PHYREG33);
0479
0480
0481 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
0482
0483 val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
0484 rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
0485 val, PHYREG6);
0486
0487 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
0488 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
0489 } else if (priv->type == PHY_TYPE_SATA) {
0490
0491 val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
0492 val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
0493 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
0494 }
0495 break;
0496
0497 default:
0498 dev_err(priv->dev, "unsupported rate: %lu\n", rate);
0499 return -EINVAL;
0500 }
0501
0502 if (priv->ext_refclk) {
0503 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
0504 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
0505 val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
0506 val |= PHYREG13_CKRCV_AMP0;
0507 rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
0508
0509 val = readl(priv->mmio + PHYREG14);
0510 val |= PHYREG14_CKRCV_AMP1;
0511 writel(val, priv->mmio + PHYREG14);
0512 }
0513 }
0514
0515 if (priv->enable_ssc) {
0516 val = readl(priv->mmio + PHYREG8);
0517 val |= PHYREG8_SSC_EN;
0518 writel(val, priv->mmio + PHYREG8);
0519 }
0520
0521 return 0;
0522 }
0523
0524 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
0525
0526 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
0527 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
0528 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
0529 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
0530 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
0531 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
0532 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
0533 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
0534 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
0535 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
0536 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
0537 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
0538 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
0539 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
0540 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
0541 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
0542 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
0543 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
0544 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
0545 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
0546 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
0547 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
0548 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
0549 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
0550 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
0551 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
0552
0553 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
0554 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
0555 };
0556
0557 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
0558 .grfcfg = &rk3568_combphy_grfcfgs,
0559 .combphy_cfg = rk3568_combphy_cfg,
0560 };
0561
0562 static const struct of_device_id rockchip_combphy_of_match[] = {
0563 {
0564 .compatible = "rockchip,rk3568-naneng-combphy",
0565 .data = &rk3568_combphy_cfgs,
0566 },
0567 { },
0568 };
0569 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
0570
0571 static struct platform_driver rockchip_combphy_driver = {
0572 .probe = rockchip_combphy_probe,
0573 .driver = {
0574 .name = "rockchip-naneng-combphy",
0575 .of_match_table = rockchip_combphy_of_match,
0576 },
0577 };
0578 module_platform_driver(rockchip_combphy_driver);
0579
0580 MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
0581 MODULE_LICENSE("GPL v2");
