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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
0004  *
0005  * Author: Wyon Bi <bivvy.bi@rock-chips.com>
0006  */
0007 
0008 #include <linux/bits.h>
0009 #include <linux/kernel.h>
0010 #include <linux/clk.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/delay.h>
0014 #include <linux/init.h>
0015 #include <linux/mfd/syscon.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/pm_runtime.h>
0020 #include <linux/reset.h>
0021 #include <linux/time64.h>
0022 
0023 #include <linux/phy/phy.h>
0024 #include <linux/phy/phy-mipi-dphy.h>
0025 
0026 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
0027 
0028 /*
0029  * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
0030  * is the first address, the other from the bit4 to bit0 is the second address.
0031  * when you configure the registers, you must set both of them. The Clock Lane
0032  * and Data Lane use the same registers with the same second address, but the
0033  * first address is different.
0034  */
0035 #define FIRST_ADDRESS(x)        (((x) & 0x7) << 5)
0036 #define SECOND_ADDRESS(x)       (((x) & 0x1f) << 0)
0037 #define PHY_REG(first, second)      (FIRST_ADDRESS(first) | \
0038                      SECOND_ADDRESS(second))
0039 
0040 /* Analog Register Part: reg00 */
0041 #define BANDGAP_POWER_MASK          BIT(7)
0042 #define BANDGAP_POWER_DOWN          BIT(7)
0043 #define BANDGAP_POWER_ON            0
0044 #define LANE_EN_MASK                GENMASK(6, 2)
0045 #define LANE_EN_CK              BIT(6)
0046 #define LANE_EN_3               BIT(5)
0047 #define LANE_EN_2               BIT(4)
0048 #define LANE_EN_1               BIT(3)
0049 #define LANE_EN_0               BIT(2)
0050 #define POWER_WORK_MASK             GENMASK(1, 0)
0051 #define POWER_WORK_ENABLE           UPDATE(1, 1, 0)
0052 #define POWER_WORK_DISABLE          UPDATE(2, 1, 0)
0053 /* Analog Register Part: reg01 */
0054 #define REG_SYNCRST_MASK            BIT(2)
0055 #define REG_SYNCRST_RESET           BIT(2)
0056 #define REG_SYNCRST_NORMAL          0
0057 #define REG_LDOPD_MASK              BIT(1)
0058 #define REG_LDOPD_POWER_DOWN            BIT(1)
0059 #define REG_LDOPD_POWER_ON          0
0060 #define REG_PLLPD_MASK              BIT(0)
0061 #define REG_PLLPD_POWER_DOWN            BIT(0)
0062 #define REG_PLLPD_POWER_ON          0
0063 /* Analog Register Part: reg03 */
0064 #define REG_FBDIV_HI_MASK           BIT(5)
0065 #define REG_FBDIV_HI(x)             UPDATE((x >> 8), 5, 5)
0066 #define REG_PREDIV_MASK             GENMASK(4, 0)
0067 #define REG_PREDIV(x)               UPDATE(x, 4, 0)
0068 /* Analog Register Part: reg04 */
0069 #define REG_FBDIV_LO_MASK           GENMASK(7, 0)
0070 #define REG_FBDIV_LO(x)             UPDATE(x, 7, 0)
0071 /* Analog Register Part: reg05 */
0072 #define SAMPLE_CLOCK_PHASE_MASK         GENMASK(6, 4)
0073 #define SAMPLE_CLOCK_PHASE(x)           UPDATE(x, 6, 4)
0074 #define CLOCK_LANE_SKEW_PHASE_MASK      GENMASK(2, 0)
0075 #define CLOCK_LANE_SKEW_PHASE(x)        UPDATE(x, 2, 0)
0076 /* Analog Register Part: reg06 */
0077 #define DATA_LANE_3_SKEW_PHASE_MASK     GENMASK(6, 4)
0078 #define DATA_LANE_3_SKEW_PHASE(x)       UPDATE(x, 6, 4)
0079 #define DATA_LANE_2_SKEW_PHASE_MASK     GENMASK(2, 0)
0080 #define DATA_LANE_2_SKEW_PHASE(x)       UPDATE(x, 2, 0)
0081 /* Analog Register Part: reg07 */
0082 #define DATA_LANE_1_SKEW_PHASE_MASK     GENMASK(6, 4)
0083 #define DATA_LANE_1_SKEW_PHASE(x)       UPDATE(x, 6, 4)
0084 #define DATA_LANE_0_SKEW_PHASE_MASK     GENMASK(2, 0)
0085 #define DATA_LANE_0_SKEW_PHASE(x)       UPDATE(x, 2, 0)
0086 /* Analog Register Part: reg08 */
0087 #define SAMPLE_CLOCK_DIRECTION_MASK     BIT(4)
0088 #define SAMPLE_CLOCK_DIRECTION_REVERSE      BIT(4)
0089 #define SAMPLE_CLOCK_DIRECTION_FORWARD      0
0090 /* Digital Register Part: reg00 */
0091 #define REG_DIG_RSTN_MASK           BIT(0)
0092 #define REG_DIG_RSTN_NORMAL         BIT(0)
0093 #define REG_DIG_RSTN_RESET          0
0094 /* Digital Register Part: reg01 */
0095 #define INVERT_TXCLKESC_MASK            BIT(1)
0096 #define INVERT_TXCLKESC_ENABLE          BIT(1)
0097 #define INVERT_TXCLKESC_DISABLE         0
0098 #define INVERT_TXBYTECLKHS_MASK         BIT(0)
0099 #define INVERT_TXBYTECLKHS_ENABLE       BIT(0)
0100 #define INVERT_TXBYTECLKHS_DISABLE      0
0101 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
0102 #define T_LPX_CNT_MASK              GENMASK(5, 0)
0103 #define T_LPX_CNT(x)                UPDATE(x, 5, 0)
0104 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
0105 #define T_HS_PREPARE_CNT_MASK           GENMASK(6, 0)
0106 #define T_HS_PREPARE_CNT(x)         UPDATE(x, 6, 0)
0107 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
0108 #define T_HS_ZERO_CNT_MASK          GENMASK(5, 0)
0109 #define T_HS_ZERO_CNT(x)            UPDATE(x, 5, 0)
0110 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
0111 #define T_HS_TRAIL_CNT_MASK         GENMASK(6, 0)
0112 #define T_HS_TRAIL_CNT(x)           UPDATE(x, 6, 0)
0113 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
0114 #define T_HS_EXIT_CNT_MASK          GENMASK(4, 0)
0115 #define T_HS_EXIT_CNT(x)            UPDATE(x, 4, 0)
0116 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
0117 #define T_CLK_POST_CNT_MASK         GENMASK(3, 0)
0118 #define T_CLK_POST_CNT(x)           UPDATE(x, 3, 0)
0119 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
0120 #define LPDT_TX_PPI_SYNC_MASK           BIT(2)
0121 #define LPDT_TX_PPI_SYNC_ENABLE         BIT(2)
0122 #define LPDT_TX_PPI_SYNC_DISABLE        0
0123 #define T_WAKEUP_CNT_HI_MASK            GENMASK(1, 0)
0124 #define T_WAKEUP_CNT_HI(x)          UPDATE(x, 1, 0)
0125 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
0126 #define T_WAKEUP_CNT_LO_MASK            GENMASK(7, 0)
0127 #define T_WAKEUP_CNT_LO(x)          UPDATE(x, 7, 0)
0128 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
0129 #define T_CLK_PRE_CNT_MASK          GENMASK(3, 0)
0130 #define T_CLK_PRE_CNT(x)            UPDATE(x, 3, 0)
0131 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
0132 #define T_TA_GO_CNT_MASK            GENMASK(5, 0)
0133 #define T_TA_GO_CNT(x)              UPDATE(x, 5, 0)
0134 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
0135 #define T_TA_SURE_CNT_MASK          GENMASK(5, 0)
0136 #define T_TA_SURE_CNT(x)            UPDATE(x, 5, 0)
0137 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
0138 #define T_TA_WAIT_CNT_MASK          GENMASK(5, 0)
0139 #define T_TA_WAIT_CNT(x)            UPDATE(x, 5, 0)
0140 /* LVDS Register Part: reg00 */
0141 #define LVDS_DIGITAL_INTERNAL_RESET_MASK    BIT(2)
0142 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2)
0143 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE  0
0144 /* LVDS Register Part: reg01 */
0145 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK   BIT(7)
0146 #define LVDS_DIGITAL_INTERNAL_ENABLE        BIT(7)
0147 #define LVDS_DIGITAL_INTERNAL_DISABLE       0
0148 /* LVDS Register Part: reg03 */
0149 #define MODE_ENABLE_MASK            GENMASK(2, 0)
0150 #define TTL_MODE_ENABLE             BIT(2)
0151 #define LVDS_MODE_ENABLE            BIT(1)
0152 #define MIPI_MODE_ENABLE            BIT(0)
0153 /* LVDS Register Part: reg0b */
0154 #define LVDS_LANE_EN_MASK           GENMASK(7, 3)
0155 #define LVDS_DATA_LANE0_EN          BIT(7)
0156 #define LVDS_DATA_LANE1_EN          BIT(6)
0157 #define LVDS_DATA_LANE2_EN          BIT(5)
0158 #define LVDS_DATA_LANE3_EN          BIT(4)
0159 #define LVDS_CLK_LANE_EN            BIT(3)
0160 #define LVDS_PLL_POWER_MASK         BIT(2)
0161 #define LVDS_PLL_POWER_OFF          BIT(2)
0162 #define LVDS_PLL_POWER_ON           0
0163 #define LVDS_BANDGAP_POWER_MASK         BIT(0)
0164 #define LVDS_BANDGAP_POWER_DOWN         BIT(0)
0165 #define LVDS_BANDGAP_POWER_ON           0
0166 
0167 #define DSI_PHY_RSTZ        0xa0
0168 #define PHY_ENABLECLK       BIT(2)
0169 #define DSI_PHY_STATUS      0xb0
0170 #define PHY_LOCK        BIT(0)
0171 
0172 struct inno_dsidphy {
0173     struct device *dev;
0174     struct clk *ref_clk;
0175     struct clk *pclk_phy;
0176     struct clk *pclk_host;
0177     void __iomem *phy_base;
0178     void __iomem *host_base;
0179     struct reset_control *rst;
0180     enum phy_mode mode;
0181     struct phy_configure_opts_mipi_dphy dphy_cfg;
0182 
0183     struct clk *pll_clk;
0184     struct {
0185         struct clk_hw hw;
0186         u8 prediv;
0187         u16 fbdiv;
0188         unsigned long rate;
0189     } pll;
0190 };
0191 
0192 enum {
0193     REGISTER_PART_ANALOG,
0194     REGISTER_PART_DIGITAL,
0195     REGISTER_PART_CLOCK_LANE,
0196     REGISTER_PART_DATA0_LANE,
0197     REGISTER_PART_DATA1_LANE,
0198     REGISTER_PART_DATA2_LANE,
0199     REGISTER_PART_DATA3_LANE,
0200     REGISTER_PART_LVDS,
0201 };
0202 
0203 static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw)
0204 {
0205     return container_of(hw, struct inno_dsidphy, pll.hw);
0206 }
0207 
0208 static void phy_update_bits(struct inno_dsidphy *inno,
0209                 u8 first, u8 second, u8 mask, u8 val)
0210 {
0211     u32 reg = PHY_REG(first, second) << 2;
0212     unsigned int tmp, orig;
0213 
0214     orig = readl(inno->phy_base + reg);
0215     tmp = orig & ~mask;
0216     tmp |= val & mask;
0217     writel(tmp, inno->phy_base + reg);
0218 }
0219 
0220 static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
0221                         unsigned long rate)
0222 {
0223     unsigned long prate = clk_get_rate(inno->ref_clk);
0224     unsigned long best_freq = 0;
0225     unsigned long fref, fout;
0226     u8 min_prediv, max_prediv;
0227     u8 _prediv, best_prediv = 1;
0228     u16 _fbdiv, best_fbdiv = 1;
0229     u32 min_delta = UINT_MAX;
0230 
0231     /*
0232      * The PLL output frequency can be calculated using a simple formula:
0233      * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
0234      * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
0235      */
0236     fref = prate / 2;
0237     if (rate > 1000000000UL)
0238         fout = 1000000000UL;
0239     else
0240         fout = rate;
0241 
0242     /* 5Mhz < Fref / prediv < 40MHz */
0243     min_prediv = DIV_ROUND_UP(fref, 40000000);
0244     max_prediv = fref / 5000000;
0245 
0246     for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
0247         u64 tmp;
0248         u32 delta;
0249 
0250         tmp = (u64)fout * _prediv;
0251         do_div(tmp, fref);
0252         _fbdiv = tmp;
0253 
0254         /*
0255          * The possible settings of feedback divider are
0256          * 12, 13, 14, 16, ~ 511
0257          */
0258         if (_fbdiv == 15)
0259             continue;
0260 
0261         if (_fbdiv < 12 || _fbdiv > 511)
0262             continue;
0263 
0264         tmp = (u64)_fbdiv * fref;
0265         do_div(tmp, _prediv);
0266 
0267         delta = abs(fout - tmp);
0268         if (!delta) {
0269             best_prediv = _prediv;
0270             best_fbdiv = _fbdiv;
0271             best_freq = tmp;
0272             break;
0273         } else if (delta < min_delta) {
0274             best_prediv = _prediv;
0275             best_fbdiv = _fbdiv;
0276             best_freq = tmp;
0277             min_delta = delta;
0278         }
0279     }
0280 
0281     if (best_freq) {
0282         inno->pll.prediv = best_prediv;
0283         inno->pll.fbdiv = best_fbdiv;
0284         inno->pll.rate = best_freq;
0285     }
0286 
0287     return best_freq;
0288 }
0289 
0290 static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
0291 {
0292     struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
0293     const struct {
0294         unsigned long rate;
0295         u8 hs_prepare;
0296         u8 clk_lane_hs_zero;
0297         u8 data_lane_hs_zero;
0298         u8 hs_trail;
0299     } timings[] = {
0300         { 110000000, 0x20, 0x16, 0x02, 0x22},
0301         { 150000000, 0x06, 0x16, 0x03, 0x45},
0302         { 200000000, 0x18, 0x17, 0x04, 0x0b},
0303         { 250000000, 0x05, 0x17, 0x05, 0x16},
0304         { 300000000, 0x51, 0x18, 0x06, 0x2c},
0305         { 400000000, 0x64, 0x19, 0x07, 0x33},
0306         { 500000000, 0x20, 0x1b, 0x07, 0x4e},
0307         { 600000000, 0x6a, 0x1d, 0x08, 0x3a},
0308         { 700000000, 0x3e, 0x1e, 0x08, 0x6a},
0309         { 800000000, 0x21, 0x1f, 0x09, 0x29},
0310         {1000000000, 0x09, 0x20, 0x09, 0x27},
0311     };
0312     u32 t_txbyteclkhs, t_txclkesc;
0313     u32 txbyteclkhs, txclkesc, esc_clk_div;
0314     u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
0315     u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
0316     unsigned int i;
0317 
0318     inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);
0319 
0320     /* Select MIPI mode */
0321     phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
0322             MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
0323     /* Configure PLL */
0324     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
0325             REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
0326     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
0327             REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
0328     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
0329             REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
0330     /* Enable PLL and LDO */
0331     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
0332             REG_LDOPD_MASK | REG_PLLPD_MASK,
0333             REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
0334     /* Reset analog */
0335     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
0336             REG_SYNCRST_MASK, REG_SYNCRST_RESET);
0337     udelay(1);
0338     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
0339             REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
0340     /* Reset digital */
0341     phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
0342             REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
0343     udelay(1);
0344     phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
0345             REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
0346 
0347     txbyteclkhs = inno->pll.rate / 8;
0348     t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
0349 
0350     esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
0351     txclkesc = txbyteclkhs / esc_clk_div;
0352     t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
0353 
0354     /*
0355      * The value of counter for HS Ths-exit
0356      * Ths-exit = Tpin_txbyteclkhs * value
0357      */
0358     hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs);
0359     /*
0360      * The value of counter for HS Tclk-post
0361      * Tclk-post = Tpin_txbyteclkhs * value
0362      */
0363     clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs);
0364     /*
0365      * The value of counter for HS Tclk-pre
0366      * Tclk-pre = Tpin_txbyteclkhs * value
0367      */
0368     clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE);
0369 
0370     /*
0371      * The value of counter for HS Tlpx Time
0372      * Tlpx = Tpin_txbyteclkhs * (2 + value)
0373      */
0374     lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs);
0375     if (lpx >= 2)
0376         lpx -= 2;
0377 
0378     /*
0379      * The value of counter for HS Tta-go
0380      * Tta-go for turnaround
0381      * Tta-go = Ttxclkesc * value
0382      */
0383     ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc);
0384     /*
0385      * The value of counter for HS Tta-sure
0386      * Tta-sure for turnaround
0387      * Tta-sure = Ttxclkesc * value
0388      */
0389     ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc);
0390     /*
0391      * The value of counter for HS Tta-wait
0392      * Tta-wait for turnaround
0393      * Tta-wait = Ttxclkesc * value
0394      */
0395     ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc);
0396 
0397     for (i = 0; i < ARRAY_SIZE(timings); i++)
0398         if (inno->pll.rate <= timings[i].rate)
0399             break;
0400 
0401     if (i == ARRAY_SIZE(timings))
0402         --i;
0403 
0404     hs_prepare = timings[i].hs_prepare;
0405     hs_trail = timings[i].hs_trail;
0406     clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
0407     data_lane_hs_zero = timings[i].data_lane_hs_zero;
0408     wakeup = 0x3ff;
0409 
0410     for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
0411         if (i == REGISTER_PART_CLOCK_LANE)
0412             hs_zero = clk_lane_hs_zero;
0413         else
0414             hs_zero = data_lane_hs_zero;
0415 
0416         phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
0417                 T_LPX_CNT(lpx));
0418         phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
0419                 T_HS_PREPARE_CNT(hs_prepare));
0420         phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
0421                 T_HS_ZERO_CNT(hs_zero));
0422         phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
0423                 T_HS_TRAIL_CNT(hs_trail));
0424         phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
0425                 T_HS_EXIT_CNT(hs_exit));
0426         phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
0427                 T_CLK_POST_CNT(clk_post));
0428         phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
0429                 T_CLK_PRE_CNT(clk_pre));
0430         phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
0431                 T_WAKEUP_CNT_HI(wakeup >> 8));
0432         phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
0433                 T_WAKEUP_CNT_LO(wakeup));
0434         phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
0435                 T_TA_GO_CNT(ta_go));
0436         phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
0437                 T_TA_SURE_CNT(ta_sure));
0438         phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
0439                 T_TA_WAIT_CNT(ta_wait));
0440     }
0441 
0442     /* Enable all lanes on analog part */
0443     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
0444             LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
0445             LANE_EN_1 | LANE_EN_0);
0446 }
0447 
0448 static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
0449 {
0450     u8 prediv = 2;
0451     u16 fbdiv = 28;
0452 
0453     /* Sample clock reverse direction */
0454     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
0455             SAMPLE_CLOCK_DIRECTION_MASK,
0456             SAMPLE_CLOCK_DIRECTION_REVERSE);
0457 
0458     /* Select LVDS mode */
0459     phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
0460             MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
0461     /* Configure PLL */
0462     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
0463             REG_PREDIV_MASK, REG_PREDIV(prediv));
0464     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
0465             REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv));
0466     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
0467             REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
0468     phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
0469     /* Enable PLL and Bandgap */
0470     phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
0471             LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
0472             LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
0473 
0474     msleep(20);
0475 
0476     /* Reset LVDS digital logic */
0477     phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
0478             LVDS_DIGITAL_INTERNAL_RESET_MASK,
0479             LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
0480     udelay(1);
0481     phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
0482             LVDS_DIGITAL_INTERNAL_RESET_MASK,
0483             LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
0484     /* Enable LVDS digital logic */
0485     phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
0486             LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
0487             LVDS_DIGITAL_INTERNAL_ENABLE);
0488     /* Enable LVDS analog driver */
0489     phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
0490             LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
0491             LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
0492             LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
0493 }
0494 
0495 static int inno_dsidphy_power_on(struct phy *phy)
0496 {
0497     struct inno_dsidphy *inno = phy_get_drvdata(phy);
0498 
0499     clk_prepare_enable(inno->pclk_phy);
0500     clk_prepare_enable(inno->ref_clk);
0501     pm_runtime_get_sync(inno->dev);
0502 
0503     /* Bandgap power on */
0504     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
0505             BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
0506     /* Enable power work */
0507     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
0508             POWER_WORK_MASK, POWER_WORK_ENABLE);
0509 
0510     switch (inno->mode) {
0511     case PHY_MODE_MIPI_DPHY:
0512         inno_dsidphy_mipi_mode_enable(inno);
0513         break;
0514     case PHY_MODE_LVDS:
0515         inno_dsidphy_lvds_mode_enable(inno);
0516         break;
0517     default:
0518         return -EINVAL;
0519     }
0520 
0521     return 0;
0522 }
0523 
0524 static int inno_dsidphy_power_off(struct phy *phy)
0525 {
0526     struct inno_dsidphy *inno = phy_get_drvdata(phy);
0527 
0528     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
0529     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
0530             REG_LDOPD_MASK | REG_PLLPD_MASK,
0531             REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
0532     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
0533             POWER_WORK_MASK, POWER_WORK_DISABLE);
0534     phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
0535             BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
0536 
0537     phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
0538     phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
0539             LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
0540             LVDS_DIGITAL_INTERNAL_DISABLE);
0541     phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
0542             LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
0543             LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
0544 
0545     pm_runtime_put(inno->dev);
0546     clk_disable_unprepare(inno->ref_clk);
0547     clk_disable_unprepare(inno->pclk_phy);
0548 
0549     return 0;
0550 }
0551 
0552 static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode,
0553                    int submode)
0554 {
0555     struct inno_dsidphy *inno = phy_get_drvdata(phy);
0556 
0557     switch (mode) {
0558     case PHY_MODE_MIPI_DPHY:
0559     case PHY_MODE_LVDS:
0560         inno->mode = mode;
0561         break;
0562     default:
0563         return -EINVAL;
0564     }
0565 
0566     return 0;
0567 }
0568 
0569 static int inno_dsidphy_configure(struct phy *phy,
0570                   union phy_configure_opts *opts)
0571 {
0572     struct inno_dsidphy *inno = phy_get_drvdata(phy);
0573     int ret;
0574 
0575     if (inno->mode != PHY_MODE_MIPI_DPHY)
0576         return -EINVAL;
0577 
0578     ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
0579     if (ret)
0580         return ret;
0581 
0582     memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg));
0583 
0584     return 0;
0585 }
0586 
0587 static const struct phy_ops inno_dsidphy_ops = {
0588     .configure = inno_dsidphy_configure,
0589     .set_mode = inno_dsidphy_set_mode,
0590     .power_on = inno_dsidphy_power_on,
0591     .power_off = inno_dsidphy_power_off,
0592     .owner = THIS_MODULE,
0593 };
0594 
0595 static int inno_dsidphy_probe(struct platform_device *pdev)
0596 {
0597     struct device *dev = &pdev->dev;
0598     struct inno_dsidphy *inno;
0599     struct phy_provider *phy_provider;
0600     struct phy *phy;
0601     int ret;
0602 
0603     inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
0604     if (!inno)
0605         return -ENOMEM;
0606 
0607     inno->dev = dev;
0608     platform_set_drvdata(pdev, inno);
0609 
0610     inno->phy_base = devm_platform_ioremap_resource(pdev, 0);
0611     if (IS_ERR(inno->phy_base))
0612         return PTR_ERR(inno->phy_base);
0613 
0614     inno->ref_clk = devm_clk_get(dev, "ref");
0615     if (IS_ERR(inno->ref_clk)) {
0616         ret = PTR_ERR(inno->ref_clk);
0617         dev_err(dev, "failed to get ref clock: %d\n", ret);
0618         return ret;
0619     }
0620 
0621     inno->pclk_phy = devm_clk_get(dev, "pclk");
0622     if (IS_ERR(inno->pclk_phy)) {
0623         ret = PTR_ERR(inno->pclk_phy);
0624         dev_err(dev, "failed to get phy pclk: %d\n", ret);
0625         return ret;
0626     }
0627 
0628     inno->rst = devm_reset_control_get(dev, "apb");
0629     if (IS_ERR(inno->rst)) {
0630         ret = PTR_ERR(inno->rst);
0631         dev_err(dev, "failed to get system reset control: %d\n", ret);
0632         return ret;
0633     }
0634 
0635     phy = devm_phy_create(dev, NULL, &inno_dsidphy_ops);
0636     if (IS_ERR(phy)) {
0637         ret = PTR_ERR(phy);
0638         dev_err(dev, "failed to create phy: %d\n", ret);
0639         return ret;
0640     }
0641 
0642     phy_set_drvdata(phy, inno);
0643 
0644     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0645     if (IS_ERR(phy_provider)) {
0646         ret = PTR_ERR(phy_provider);
0647         dev_err(dev, "failed to register phy provider: %d\n", ret);
0648         return ret;
0649     }
0650 
0651     pm_runtime_enable(dev);
0652 
0653     return 0;
0654 }
0655 
0656 static int inno_dsidphy_remove(struct platform_device *pdev)
0657 {
0658     struct inno_dsidphy *inno = platform_get_drvdata(pdev);
0659 
0660     pm_runtime_disable(inno->dev);
0661 
0662     return 0;
0663 }
0664 
0665 static const struct of_device_id inno_dsidphy_of_match[] = {
0666     { .compatible = "rockchip,px30-dsi-dphy", },
0667     { .compatible = "rockchip,rk3128-dsi-dphy", },
0668     { .compatible = "rockchip,rk3368-dsi-dphy", },
0669     {}
0670 };
0671 MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match);
0672 
0673 static struct platform_driver inno_dsidphy_driver = {
0674     .driver = {
0675         .name = "inno-dsidphy",
0676         .of_match_table = of_match_ptr(inno_dsidphy_of_match),
0677     },
0678     .probe = inno_dsidphy_probe,
0679     .remove = inno_dsidphy_remove,
0680 };
0681 module_platform_driver(inno_dsidphy_driver);
0682 
0683 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
0684 MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver");
0685 MODULE_LICENSE("GPL v2");
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