phy/rockchip/phy-rockchip-inno-csidphy.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Rockchip MIPI RX Innosilicon DPHY driver
0004  *
0005  * Copyright (C) 2021 Fuzhou Rockchip Electronics Co., Ltd.
0006  */
0007
0008 #include <linux/bitfield.h>
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/io.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/phy/phy.h>
0017 #include <linux/phy/phy-mipi-dphy.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/pm_runtime.h>
0020 #include <linux/regmap.h>
0021 #include <linux/reset.h>
0022
0023 /* GRF */
0024 #define RK1808_GRF_PD_VI_CON_OFFSET 0x0430
0025
0026 #define RK3326_GRF_PD_VI_CON_OFFSET 0x0430
0027
0028 #define RK3368_GRF_SOC_CON6_OFFSET  0x0418
0029
0030 /* PHY */
0031 #define CSIDPHY_CTRL_LANE_ENABLE        0x00
0032 #define CSIDPHY_CTRL_LANE_ENABLE_CK     BIT(6)
0033 #define CSIDPHY_CTRL_LANE_ENABLE_MASK       GENMASK(5, 2)
0034 #define CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED  BIT(0)
0035
0036 /* not present on all variants */
0037 #define CSIDPHY_CTRL_PWRCTL         0x04
0038 #define CSIDPHY_CTRL_PWRCTL_UNDEFINED       GENMASK(7, 5)
0039 #define CSIDPHY_CTRL_PWRCTL_SYNCRST     BIT(2)
0040 #define CSIDPHY_CTRL_PWRCTL_LDO_PD      BIT(1)
0041 #define CSIDPHY_CTRL_PWRCTL_PLL_PD      BIT(0)
0042
0043 #define CSIDPHY_CTRL_DIG_RST            0x80
0044 #define CSIDPHY_CTRL_DIG_RST_UNDEFINED      0x1e
0045 #define CSIDPHY_CTRL_DIG_RST_RESET      BIT(0)
0046
0047 /* offset after ths_settle_offset */
0048 #define CSIDPHY_CLK_THS_SETTLE          0
0049 #define CSIDPHY_LANE_THS_SETTLE(n)      (((n) + 1) * 0x80)
0050 #define CSIDPHY_THS_SETTLE_MASK         GENMASK(6, 0)
0051
0052 /* offset after calib_offset */
0053 #define CSIDPHY_CLK_CALIB_EN            0
0054 #define CSIDPHY_LANE_CALIB_EN(n)        (((n) + 1) * 0x80)
0055 #define CSIDPHY_CALIB_EN            BIT(7)
0056
0057 /* Configure the count time of the THS-SETTLE by protocol. */
0058 #define RK1808_CSIDPHY_CLK_WR_THS_SETTLE    0x160
0059 #define RK3326_CSIDPHY_CLK_WR_THS_SETTLE    0x100
0060 #define RK3368_CSIDPHY_CLK_WR_THS_SETTLE    0x100
0061
0062 /* Calibration reception enable */
0063 #define RK1808_CSIDPHY_CLK_CALIB_EN     0x168
0064
0065 /*
0066  * The higher 16-bit of this register is used for write protection
0067  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
0068  */
0069 #define HIWORD_UPDATE(val, mask, shift) \
0070         ((val) << (shift) | (mask) << ((shift) + 16))
0071
0072 #define HZ_TO_MHZ(freq)             div_u64(freq, 1000 * 1000)
0073
0074 enum dphy_reg_id {
0075     /* rk1808 & rk3326 */
0076     GRF_DPHY_CSIPHY_FORCERXMODE,
0077     GRF_DPHY_CSIPHY_CLKLANE_EN,
0078     GRF_DPHY_CSIPHY_DATALANE_EN,
0079 };
0080
0081 struct dphy_reg {
0082     u32 offset;
0083     u32 mask;
0084     u32 shift;
0085 };
0086
0087 #define PHY_REG(_offset, _width, _shift) \
0088     { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
0089
0090 static const struct dphy_reg rk1808_grf_dphy_regs[] = {
0091     [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
0092     [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
0093     [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
0094 };
0095
0096 static const struct dphy_reg rk3326_grf_dphy_regs[] = {
0097     [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
0098     [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
0099     [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
0100 };
0101
0102 static const struct dphy_reg rk3368_grf_dphy_regs[] = {
0103     [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
0104 };
0105
0106 struct hsfreq_range {
0107     u32 range_h;
0108     u8 cfg_bit;
0109 };
0110
0111 struct dphy_drv_data {
0112     int pwrctl_offset;
0113     int ths_settle_offset;
0114     int calib_offset;
0115     const struct hsfreq_range *hsfreq_ranges;
0116     int num_hsfreq_ranges;
0117     const struct dphy_reg *grf_regs;
0118 };
0119
0120 struct rockchip_inno_csidphy {
0121     struct device *dev;
0122     void __iomem *phy_base;
0123     struct clk *pclk;
0124     struct regmap *grf;
0125     struct reset_control *rst;
0126     const struct dphy_drv_data *drv_data;
0127     struct phy_configure_opts_mipi_dphy config;
0128     u8 hsfreq;
0129 };
0130
0131 static inline void write_grf_reg(struct rockchip_inno_csidphy *priv,
0132                  int index, u8 value)
0133 {
0134     const struct dphy_drv_data *drv_data = priv->drv_data;
0135     const struct dphy_reg *reg = &drv_data->grf_regs[index];
0136
0137     if (reg->offset)
0138         regmap_write(priv->grf, reg->offset,
0139                  HIWORD_UPDATE(value, reg->mask, reg->shift));
0140 }
0141
0142 /* These tables must be sorted by .range_h ascending. */
0143 static const struct hsfreq_range rk1808_mipidphy_hsfreq_ranges[] = {
0144     { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
0145     { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
0146     { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
0147     {1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
0148     {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
0149 };
0150
0151 static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = {
0152     { 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
0153     { 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
0154     { 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
0155     {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
0156 };
0157
0158 static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = {
0159     { 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
0160     { 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
0161     { 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
0162     {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
0163 };
0164
0165 static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy *priv,
0166                          int hsfreq, int offset)
0167 {
0168     const struct dphy_drv_data *drv_data = priv->drv_data;
0169     u32 val;
0170
0171     val = readl(priv->phy_base + drv_data->ths_settle_offset + offset);
0172     val &= ~CSIDPHY_THS_SETTLE_MASK;
0173     val |= hsfreq;
0174     writel(val, priv->phy_base + drv_data->ths_settle_offset + offset);
0175 }
0176
0177 static int rockchip_inno_csidphy_configure(struct phy *phy,
0178                        union phy_configure_opts *opts)
0179 {
0180     struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
0181     const struct dphy_drv_data *drv_data = priv->drv_data;
0182     struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
0183     unsigned int hsfreq = 0;
0184     unsigned int i;
0185     u64 data_rate_mbps;
0186     int ret;
0187
0188     /* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */
0189     ret = phy_mipi_dphy_config_validate(config);
0190     if (ret)
0191         return ret;
0192
0193     data_rate_mbps = HZ_TO_MHZ(config->hs_clk_rate);
0194
0195     dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",
0196         config->lanes, data_rate_mbps);
0197     for (i = 0; i < drv_data->num_hsfreq_ranges; i++) {
0198         if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) {
0199             hsfreq = drv_data->hsfreq_ranges[i].cfg_bit;
0200             break;
0201         }
0202     }
0203     if (!hsfreq)
0204         return -EINVAL;
0205
0206     priv->hsfreq = hsfreq;
0207     priv->config = *config;
0208     return 0;
0209 }
0210
0211 static int rockchip_inno_csidphy_power_on(struct phy *phy)
0212 {
0213     struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
0214     const struct dphy_drv_data *drv_data = priv->drv_data;
0215     u64 data_rate_mbps = HZ_TO_MHZ(priv->config.hs_clk_rate);
0216     u32 val;
0217     int ret, i;
0218
0219     ret = clk_enable(priv->pclk);
0220     if (ret < 0)
0221         return ret;
0222
0223     ret = pm_runtime_resume_and_get(priv->dev);
0224     if (ret < 0) {
0225         clk_disable(priv->pclk);
0226         return ret;
0227     }
0228
0229     /* phy start */
0230     if (drv_data->pwrctl_offset >= 0)
0231         writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
0232                CSIDPHY_CTRL_PWRCTL_SYNCRST,
0233                priv->phy_base + drv_data->pwrctl_offset);
0234
0235     /* set data lane num and enable clock lane */
0236     val = FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_MASK, GENMASK(priv->config.lanes - 1, 0)) |
0237           FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_CK, 1) |
0238           FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED, 1);
0239     writel(val, priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);
0240
0241     /* Reset dphy analog part */
0242     if (drv_data->pwrctl_offset >= 0)
0243         writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED,
0244                priv->phy_base + drv_data->pwrctl_offset);
0245     usleep_range(500, 1000);
0246
0247     /* Reset dphy digital part */
0248     writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED,
0249            priv->phy_base + CSIDPHY_CTRL_DIG_RST);
0250     writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED + CSIDPHY_CTRL_DIG_RST_RESET,
0251            priv->phy_base + CSIDPHY_CTRL_DIG_RST);
0252
0253     /* not into receive mode/wait stopstate */
0254     write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);
0255
0256     /* enable calibration */
0257     if (data_rate_mbps > 1500 && drv_data->calib_offset >= 0) {
0258         writel(CSIDPHY_CALIB_EN,
0259                priv->phy_base + drv_data->calib_offset +
0260                     CSIDPHY_CLK_CALIB_EN);
0261         for (i = 0; i < priv->config.lanes; i++)
0262             writel(CSIDPHY_CALIB_EN,
0263                    priv->phy_base + drv_data->calib_offset +
0264                         CSIDPHY_LANE_CALIB_EN(i));
0265     }
0266
0267     rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,
0268                      CSIDPHY_CLK_THS_SETTLE);
0269     for (i = 0; i < priv->config.lanes; i++)
0270         rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,
0271                          CSIDPHY_LANE_THS_SETTLE(i));
0272
0273     write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1);
0274     write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN,
0275               GENMASK(priv->config.lanes - 1, 0));
0276
0277     return 0;
0278 }
0279
0280 static int rockchip_inno_csidphy_power_off(struct phy *phy)
0281 {
0282     struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
0283     const struct dphy_drv_data *drv_data = priv->drv_data;
0284
0285     /* disable all lanes */
0286     writel(CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED,
0287            priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);
0288
0289     /* disable pll and ldo */
0290     if (drv_data->pwrctl_offset >= 0)
0291         writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
0292                CSIDPHY_CTRL_PWRCTL_LDO_PD |
0293                CSIDPHY_CTRL_PWRCTL_PLL_PD,
0294                priv->phy_base + drv_data->pwrctl_offset);
0295     usleep_range(500, 1000);
0296
0297     pm_runtime_put(priv->dev);
0298     clk_disable(priv->pclk);
0299
0300     return 0;
0301 }
0302
0303 static int rockchip_inno_csidphy_init(struct phy *phy)
0304 {
0305     struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
0306
0307     return clk_prepare(priv->pclk);
0308 }
0309
0310 static int rockchip_inno_csidphy_exit(struct phy *phy)
0311 {
0312     struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
0313
0314     clk_unprepare(priv->pclk);
0315
0316     return 0;
0317 }
0318
0319 static const struct phy_ops rockchip_inno_csidphy_ops = {
0320     .power_on   = rockchip_inno_csidphy_power_on,
0321     .power_off  = rockchip_inno_csidphy_power_off,
0322     .init       = rockchip_inno_csidphy_init,
0323     .exit       = rockchip_inno_csidphy_exit,
0324     .configure  = rockchip_inno_csidphy_configure,
0325     .owner      = THIS_MODULE,
0326 };
0327
0328 static const struct dphy_drv_data rk1808_mipidphy_drv_data = {
0329     .pwrctl_offset = -1,
0330     .ths_settle_offset = RK1808_CSIDPHY_CLK_WR_THS_SETTLE,
0331     .calib_offset = RK1808_CSIDPHY_CLK_CALIB_EN,
0332     .hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges,
0333     .num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges),
0334     .grf_regs = rk1808_grf_dphy_regs,
0335 };
0336
0337 static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
0338     .pwrctl_offset = CSIDPHY_CTRL_PWRCTL,
0339     .ths_settle_offset = RK3326_CSIDPHY_CLK_WR_THS_SETTLE,
0340     .calib_offset = -1,
0341     .hsfreq_ranges = rk3326_mipidphy_hsfreq_ranges,
0342     .num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges),
0343     .grf_regs = rk3326_grf_dphy_regs,
0344 };
0345
0346 static const struct dphy_drv_data rk3368_mipidphy_drv_data = {
0347     .pwrctl_offset = CSIDPHY_CTRL_PWRCTL,
0348     .ths_settle_offset = RK3368_CSIDPHY_CLK_WR_THS_SETTLE,
0349     .calib_offset = -1,
0350     .hsfreq_ranges = rk3368_mipidphy_hsfreq_ranges,
0351     .num_hsfreq_ranges = ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges),
0352     .grf_regs = rk3368_grf_dphy_regs,
0353 };
0354
0355 static const struct of_device_id rockchip_inno_csidphy_match_id[] = {
0356     {
0357         .compatible = "rockchip,px30-csi-dphy",
0358         .data = &rk3326_mipidphy_drv_data,
0359     },
0360     {
0361         .compatible = "rockchip,rk1808-csi-dphy",
0362         .data = &rk1808_mipidphy_drv_data,
0363     },
0364     {
0365         .compatible = "rockchip,rk3326-csi-dphy",
0366         .data = &rk3326_mipidphy_drv_data,
0367     },
0368     {
0369         .compatible = "rockchip,rk3368-csi-dphy",
0370         .data = &rk3368_mipidphy_drv_data,
0371     },
0372     {}
0373 };
0374 MODULE_DEVICE_TABLE(of, rockchip_inno_csidphy_match_id);
0375
0376 static int rockchip_inno_csidphy_probe(struct platform_device *pdev)
0377 {
0378     struct rockchip_inno_csidphy *priv;
0379     struct device *dev = &pdev->dev;
0380     struct phy_provider *phy_provider;
0381     struct phy *phy;
0382
0383     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0384     if (!priv)
0385         return -ENOMEM;
0386
0387     priv->dev = dev;
0388     platform_set_drvdata(pdev, priv);
0389
0390     priv->drv_data = of_device_get_match_data(dev);
0391     if (!priv->drv_data) {
0392         dev_err(dev, "Can't find device data\n");
0393         return -ENODEV;
0394     }
0395
0396     priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
0397                             "rockchip,grf");
0398     if (IS_ERR(priv->grf)) {
0399         dev_err(dev, "Can't find GRF syscon\n");
0400         return PTR_ERR(priv->grf);
0401     }
0402
0403     priv->phy_base = devm_platform_ioremap_resource(pdev, 0);
0404     if (IS_ERR(priv->phy_base))
0405         return PTR_ERR(priv->phy_base);
0406
0407     priv->pclk = devm_clk_get(dev, "pclk");
0408     if (IS_ERR(priv->pclk)) {
0409         dev_err(dev, "failed to get pclk\n");
0410         return PTR_ERR(priv->pclk);
0411     }
0412
0413     priv->rst = devm_reset_control_get(dev, "apb");
0414     if (IS_ERR(priv->rst)) {
0415         dev_err(dev, "failed to get system reset control\n");
0416         return PTR_ERR(priv->rst);
0417     }
0418
0419     phy = devm_phy_create(dev, NULL, &rockchip_inno_csidphy_ops);
0420     if (IS_ERR(phy)) {
0421         dev_err(dev, "failed to create phy\n");
0422         return PTR_ERR(phy);
0423     }
0424
0425     phy_set_drvdata(phy, priv);
0426
0427     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0428     if (IS_ERR(phy_provider)) {
0429         dev_err(dev, "failed to register phy provider\n");
0430         return PTR_ERR(phy_provider);
0431     }
0432
0433     pm_runtime_enable(dev);
0434
0435     return 0;
0436 }
0437
0438 static int rockchip_inno_csidphy_remove(struct platform_device *pdev)
0439 {
0440     struct rockchip_inno_csidphy *priv = platform_get_drvdata(pdev);
0441
0442     pm_runtime_disable(priv->dev);
0443
0444     return 0;
0445 }
0446
0447 static struct platform_driver rockchip_inno_csidphy_driver = {
0448     .driver = {
0449         .name = "rockchip-inno-csidphy",
0450         .of_match_table = rockchip_inno_csidphy_match_id,
0451     },
0452     .probe = rockchip_inno_csidphy_probe,
0453     .remove = rockchip_inno_csidphy_remove,
0454 };
0455
0456 module_platform_driver(rockchip_inno_csidphy_driver);
0457 MODULE_AUTHOR("Heiko Stuebner <heiko.stuebner@theobroma-systems.com>");
0458 MODULE_DESCRIPTION("Rockchip MIPI Innosilicon CSI-DPHY driver");
0459 MODULE_LICENSE("GPL v2");