phy/rockchip/phy-rockchip-dp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Rockchip DP PHY driver
0004  *
0005  * Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
0006  * Author: Yakir Yang <ykk@@rock-chips.com>
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/phy/phy.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/regmap.h>
0016
0017 #define GRF_SOC_CON12                           0x0274
0018
0019 #define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK   BIT(20)
0020 #define GRF_EDP_REF_CLK_SEL_INTER               BIT(4)
0021
0022 #define GRF_EDP_PHY_SIDDQ_HIWORD_MASK           BIT(21)
0023 #define GRF_EDP_PHY_SIDDQ_ON                    0
0024 #define GRF_EDP_PHY_SIDDQ_OFF                   BIT(5)
0025
0026 struct rockchip_dp_phy {
0027     struct device  *dev;
0028     struct regmap  *grf;
0029     struct clk     *phy_24m;
0030 };
0031
0032 static int rockchip_set_phy_state(struct phy *phy, bool enable)
0033 {
0034     struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
0035     int ret;
0036
0037     if (enable) {
0038         ret = regmap_write(dp->grf, GRF_SOC_CON12,
0039                    GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
0040                    GRF_EDP_PHY_SIDDQ_ON);
0041         if (ret < 0) {
0042             dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
0043             return ret;
0044         }
0045
0046         ret = clk_prepare_enable(dp->phy_24m);
0047     } else {
0048         clk_disable_unprepare(dp->phy_24m);
0049
0050         ret = regmap_write(dp->grf, GRF_SOC_CON12,
0051                    GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
0052                    GRF_EDP_PHY_SIDDQ_OFF);
0053     }
0054
0055     return ret;
0056 }
0057
0058 static int rockchip_dp_phy_power_on(struct phy *phy)
0059 {
0060     return rockchip_set_phy_state(phy, true);
0061 }
0062
0063 static int rockchip_dp_phy_power_off(struct phy *phy)
0064 {
0065     return rockchip_set_phy_state(phy, false);
0066 }
0067
0068 static const struct phy_ops rockchip_dp_phy_ops = {
0069     .power_on   = rockchip_dp_phy_power_on,
0070     .power_off  = rockchip_dp_phy_power_off,
0071     .owner      = THIS_MODULE,
0072 };
0073
0074 static int rockchip_dp_phy_probe(struct platform_device *pdev)
0075 {
0076     struct device *dev = &pdev->dev;
0077     struct device_node *np = dev->of_node;
0078     struct phy_provider *phy_provider;
0079     struct rockchip_dp_phy *dp;
0080     struct phy *phy;
0081     int ret;
0082
0083     if (!np)
0084         return -ENODEV;
0085
0086     if (!dev->parent || !dev->parent->of_node)
0087         return -ENODEV;
0088
0089     dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
0090     if (!dp)
0091         return -ENOMEM;
0092
0093     dp->dev = dev;
0094
0095     dp->phy_24m = devm_clk_get(dev, "24m");
0096     if (IS_ERR(dp->phy_24m)) {
0097         dev_err(dev, "cannot get clock 24m\n");
0098         return PTR_ERR(dp->phy_24m);
0099     }
0100
0101     ret = clk_set_rate(dp->phy_24m, 24000000);
0102     if (ret < 0) {
0103         dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
0104         return ret;
0105     }
0106
0107     dp->grf = syscon_node_to_regmap(dev->parent->of_node);
0108     if (IS_ERR(dp->grf)) {
0109         dev_err(dev, "rk3288-dp needs the General Register Files syscon\n");
0110         return PTR_ERR(dp->grf);
0111     }
0112
0113     ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
0114                GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
0115     if (ret != 0) {
0116         dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
0117         return ret;
0118     }
0119
0120     phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
0121     if (IS_ERR(phy)) {
0122         dev_err(dev, "failed to create phy\n");
0123         return PTR_ERR(phy);
0124     }
0125     phy_set_drvdata(phy, dp);
0126
0127     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0128
0129     return PTR_ERR_OR_ZERO(phy_provider);
0130 }
0131
0132 static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
0133     { .compatible = "rockchip,rk3288-dp-phy" },
0134     {}
0135 };
0136
0137 MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
0138
0139 static struct platform_driver rockchip_dp_phy_driver = {
0140     .probe      = rockchip_dp_phy_probe,
0141     .driver     = {
0142         .name   = "rockchip-dp-phy",
0143         .of_match_table = rockchip_dp_phy_dt_ids,
0144     },
0145 };
0146
0147 module_platform_driver(rockchip_dp_phy_driver);
0148
0149 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
0150 MODULE_DESCRIPTION("Rockchip DP PHY driver");
0151 MODULE_LICENSE("GPL v2");