phy/ralink/phy-ralink-usb.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2017 John Crispin <john@phrozen.org>
0004  *
0005  * Based on code from
0006  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
0007  */
0008
0009 #include <linux/delay.h>
0010 #include <linux/err.h>
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/module.h>
0015 #include <linux/mutex.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/phy/phy.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regmap.h>
0020 #include <linux/reset.h>
0021
0022 #define RT_SYSC_REG_SYSCFG1     0x014
0023 #define RT_SYSC_REG_CLKCFG1     0x030
0024 #define RT_SYSC_REG_USB_PHY_CFG     0x05c
0025
0026 #define OFS_U2_PHY_AC0          0x800
0027 #define OFS_U2_PHY_AC1          0x804
0028 #define OFS_U2_PHY_AC2          0x808
0029 #define OFS_U2_PHY_ACR0         0x810
0030 #define OFS_U2_PHY_ACR1         0x814
0031 #define OFS_U2_PHY_ACR2         0x818
0032 #define OFS_U2_PHY_ACR3         0x81C
0033 #define OFS_U2_PHY_ACR4         0x820
0034 #define OFS_U2_PHY_AMON0        0x824
0035 #define OFS_U2_PHY_DCR0         0x860
0036 #define OFS_U2_PHY_DCR1         0x864
0037 #define OFS_U2_PHY_DTM0         0x868
0038 #define OFS_U2_PHY_DTM1         0x86C
0039
0040 #define RT_RSTCTRL_UDEV         BIT(25)
0041 #define RT_RSTCTRL_UHST         BIT(22)
0042 #define RT_SYSCFG1_USB0_HOST_MODE   BIT(10)
0043
0044 #define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
0045 #define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
0046 #define RT_CLKCFG1_UPHY1_CLK_EN     BIT(20)
0047 #define RT_CLKCFG1_UPHY0_CLK_EN     BIT(18)
0048
0049 #define USB_PHY_UTMI_8B60M      BIT(1)
0050 #define UDEV_WAKEUP         BIT(0)
0051
0052 struct ralink_usb_phy {
0053     struct reset_control    *rstdev;
0054     struct reset_control    *rsthost;
0055     u32         clk;
0056     struct phy      *phy;
0057     void __iomem        *base;
0058     struct regmap       *sysctl;
0059 };
0060
0061 static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
0062 {
0063     writel(val, phy->base + reg);
0064 }
0065
0066 static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
0067 {
0068     return readl(phy->base + reg);
0069 }
0070
0071 static void ralink_usb_phy_init(struct ralink_usb_phy *phy)
0072 {
0073     u2_phy_r32(phy, OFS_U2_PHY_AC2);
0074     u2_phy_r32(phy, OFS_U2_PHY_ACR0);
0075     u2_phy_r32(phy, OFS_U2_PHY_DCR0);
0076
0077     u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
0078     u2_phy_r32(phy, OFS_U2_PHY_DCR0);
0079     u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
0080     u2_phy_r32(phy, OFS_U2_PHY_DCR0);
0081     u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
0082     u2_phy_r32(phy, OFS_U2_PHY_DCR0);
0083     u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
0084     u2_phy_r32(phy, OFS_U2_PHY_DCR0);
0085     u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
0086     u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
0087     u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
0088     u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
0089 }
0090
0091 static int ralink_usb_phy_power_on(struct phy *_phy)
0092 {
0093     struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
0094     u32 t;
0095
0096     /* enable the phy */
0097     regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
0098                phy->clk, phy->clk);
0099
0100     /* setup host mode */
0101     regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1,
0102                RT_SYSCFG1_USB0_HOST_MODE,
0103                RT_SYSCFG1_USB0_HOST_MODE);
0104
0105     /* deassert the reset lines */
0106     reset_control_deassert(phy->rsthost);
0107     reset_control_deassert(phy->rstdev);
0108
0109     /*
0110      * The SDK kernel had a delay of 100ms. however on device
0111      * testing showed that 10ms is enough
0112      */
0113     mdelay(10);
0114
0115     if (phy->base)
0116         ralink_usb_phy_init(phy);
0117
0118     /* print some status info */
0119     regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t);
0120     dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
0121         (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
0122     if (t & USB_PHY_UTMI_8B60M)
0123         dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
0124     else
0125         dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
0126
0127     return 0;
0128 }
0129
0130 static int ralink_usb_phy_power_off(struct phy *_phy)
0131 {
0132     struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
0133
0134     /* disable the phy */
0135     regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
0136                phy->clk, 0);
0137
0138     /* assert the reset lines */
0139     reset_control_assert(phy->rstdev);
0140     reset_control_assert(phy->rsthost);
0141
0142     return 0;
0143 }
0144
0145 static const struct phy_ops ralink_usb_phy_ops = {
0146     .power_on   = ralink_usb_phy_power_on,
0147     .power_off  = ralink_usb_phy_power_off,
0148     .owner      = THIS_MODULE,
0149 };
0150
0151 static const struct of_device_id ralink_usb_phy_of_match[] = {
0152     {
0153         .compatible = "ralink,rt3352-usbphy",
0154         .data = (void *)(uintptr_t)(RT_CLKCFG1_UPHY1_CLK_EN |
0155                         RT_CLKCFG1_UPHY0_CLK_EN)
0156     },
0157     {
0158         .compatible = "mediatek,mt7620-usbphy",
0159         .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
0160                         MT7620_CLKCFG1_UPHY0_CLK_EN)
0161     },
0162     {
0163         .compatible = "mediatek,mt7628-usbphy",
0164         .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
0165                         MT7620_CLKCFG1_UPHY0_CLK_EN) },
0166     { },
0167 };
0168 MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
0169
0170 static int ralink_usb_phy_probe(struct platform_device *pdev)
0171 {
0172     struct device *dev = &pdev->dev;
0173     struct phy_provider *phy_provider;
0174     const struct of_device_id *match;
0175     struct ralink_usb_phy *phy;
0176
0177     match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
0178     if (!match)
0179         return -ENODEV;
0180
0181     phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
0182     if (!phy)
0183         return -ENOMEM;
0184
0185     phy->clk = (uintptr_t)match->data;
0186     phy->base = NULL;
0187
0188     phy->sysctl = syscon_regmap_lookup_by_phandle(dev->of_node, "ralink,sysctl");
0189     if (IS_ERR(phy->sysctl)) {
0190         dev_err(dev, "failed to get sysctl registers\n");
0191         return PTR_ERR(phy->sysctl);
0192     }
0193
0194     /* The MT7628 and MT7688 require extra setup of PHY registers. */
0195     if (of_device_is_compatible(dev->of_node, "mediatek,mt7628-usbphy")) {
0196         phy->base = devm_platform_ioremap_resource(pdev, 0);
0197         if (IS_ERR(phy->base)) {
0198             dev_err(dev, "failed to remap register memory\n");
0199             return PTR_ERR(phy->base);
0200         }
0201     }
0202
0203     phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
0204     if (IS_ERR(phy->rsthost)) {
0205         dev_err(dev, "host reset is missing\n");
0206         return PTR_ERR(phy->rsthost);
0207     }
0208
0209     phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
0210     if (IS_ERR(phy->rstdev)) {
0211         dev_err(dev, "device reset is missing\n");
0212         return PTR_ERR(phy->rstdev);
0213     }
0214
0215     phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
0216     if (IS_ERR(phy->phy)) {
0217         dev_err(dev, "failed to create PHY\n");
0218         return PTR_ERR(phy->phy);
0219     }
0220     phy_set_drvdata(phy->phy, phy);
0221
0222     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0223
0224     return PTR_ERR_OR_ZERO(phy_provider);
0225 }
0226
0227 static struct platform_driver ralink_usb_phy_driver = {
0228     .probe  = ralink_usb_phy_probe,
0229     .driver = {
0230         .of_match_table = ralink_usb_phy_of_match,
0231         .name  = "ralink-usb-phy",
0232     }
0233 };
0234 module_platform_driver(ralink_usb_phy_driver);
0235
0236 MODULE_DESCRIPTION("Ralink USB phy driver");
0237 MODULE_AUTHOR("John Crispin <john@phrozen.org>");
0238 MODULE_LICENSE("GPL v2");