phy/qualcomm/phy-qcom-usb-ss.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved.
0004  * Copyright (c) 2018-2020, Linaro Limited
0005  */
0006
0007 #include <linux/clk.h>
0008 #include <linux/delay.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/phy/phy.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/reset.h>
0018 #include <linux/slab.h>
0019
0020 #define PHY_CTRL0           0x6C
0021 #define PHY_CTRL1           0x70
0022 #define PHY_CTRL2           0x74
0023 #define PHY_CTRL4           0x7C
0024
0025 /* PHY_CTRL bits */
0026 #define REF_PHY_EN          BIT(0)
0027 #define LANE0_PWR_ON            BIT(2)
0028 #define SWI_PCS_CLK_SEL         BIT(4)
0029 #define TST_PWR_DOWN            BIT(4)
0030 #define PHY_RESET           BIT(7)
0031
0032 #define NUM_BULK_CLKS           3
0033 #define NUM_BULK_REGS           2
0034
0035 struct ssphy_priv {
0036     void __iomem *base;
0037     struct device *dev;
0038     struct reset_control *reset_com;
0039     struct reset_control *reset_phy;
0040     struct regulator_bulk_data regs[NUM_BULK_REGS];
0041     struct clk_bulk_data clks[NUM_BULK_CLKS];
0042     enum phy_mode mode;
0043 };
0044
0045 static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val)
0046 {
0047     writel((readl(addr) & ~mask) | val, addr);
0048 }
0049
0050 static int qcom_ssphy_do_reset(struct ssphy_priv *priv)
0051 {
0052     int ret;
0053
0054     if (!priv->reset_com) {
0055         qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET,
0056                    PHY_RESET);
0057         usleep_range(10, 20);
0058         qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0);
0059     } else {
0060         ret = reset_control_assert(priv->reset_com);
0061         if (ret) {
0062             dev_err(priv->dev, "Failed to assert reset com\n");
0063             return ret;
0064         }
0065
0066         ret = reset_control_assert(priv->reset_phy);
0067         if (ret) {
0068             dev_err(priv->dev, "Failed to assert reset phy\n");
0069             return ret;
0070         }
0071
0072         usleep_range(10, 20);
0073
0074         ret = reset_control_deassert(priv->reset_com);
0075         if (ret) {
0076             dev_err(priv->dev, "Failed to deassert reset com\n");
0077             return ret;
0078         }
0079
0080         ret = reset_control_deassert(priv->reset_phy);
0081         if (ret) {
0082             dev_err(priv->dev, "Failed to deassert reset phy\n");
0083             return ret;
0084         }
0085     }
0086
0087     return 0;
0088 }
0089
0090 static int qcom_ssphy_power_on(struct phy *phy)
0091 {
0092     struct ssphy_priv *priv = phy_get_drvdata(phy);
0093     int ret;
0094
0095     ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs);
0096     if (ret)
0097         return ret;
0098
0099     ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks);
0100     if (ret)
0101         goto err_disable_regulator;
0102
0103     ret = qcom_ssphy_do_reset(priv);
0104     if (ret)
0105         goto err_disable_clock;
0106
0107     writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0);
0108     qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON);
0109     qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN);
0110     qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0);
0111
0112     return 0;
0113 err_disable_clock:
0114     clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
0115 err_disable_regulator:
0116     regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
0117
0118     return ret;
0119 }
0120
0121 static int qcom_ssphy_power_off(struct phy *phy)
0122 {
0123     struct ssphy_priv *priv = phy_get_drvdata(phy);
0124
0125     qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0);
0126     qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0);
0127     qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN);
0128
0129     clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
0130     regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
0131
0132     return 0;
0133 }
0134
0135 static int qcom_ssphy_init_clock(struct ssphy_priv *priv)
0136 {
0137     priv->clks[0].id = "ref";
0138     priv->clks[1].id = "ahb";
0139     priv->clks[2].id = "pipe";
0140
0141     return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks);
0142 }
0143
0144 static int qcom_ssphy_init_regulator(struct ssphy_priv *priv)
0145 {
0146     int ret;
0147
0148     priv->regs[0].supply = "vdd";
0149     priv->regs[1].supply = "vdda1p8";
0150     ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs);
0151     if (ret) {
0152         if (ret != -EPROBE_DEFER)
0153             dev_err(priv->dev, "Failed to get regulators\n");
0154         return ret;
0155     }
0156
0157     return ret;
0158 }
0159
0160 static int qcom_ssphy_init_reset(struct ssphy_priv *priv)
0161 {
0162     priv->reset_com = devm_reset_control_get_optional_exclusive(priv->dev, "com");
0163     if (IS_ERR(priv->reset_com)) {
0164         dev_err(priv->dev, "Failed to get reset control com\n");
0165         return PTR_ERR(priv->reset_com);
0166     }
0167
0168     if (priv->reset_com) {
0169         /* if reset_com is present, reset_phy is no longer optional */
0170         priv->reset_phy = devm_reset_control_get_exclusive(priv->dev, "phy");
0171         if (IS_ERR(priv->reset_phy)) {
0172             dev_err(priv->dev, "Failed to get reset control phy\n");
0173             return PTR_ERR(priv->reset_phy);
0174         }
0175     }
0176
0177     return 0;
0178 }
0179
0180 static const struct phy_ops qcom_ssphy_ops = {
0181     .power_off = qcom_ssphy_power_off,
0182     .power_on = qcom_ssphy_power_on,
0183     .owner = THIS_MODULE,
0184 };
0185
0186 static int qcom_ssphy_probe(struct platform_device *pdev)
0187 {
0188     struct device *dev = &pdev->dev;
0189     struct phy_provider *provider;
0190     struct ssphy_priv *priv;
0191     struct phy *phy;
0192     int ret;
0193
0194     priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL);
0195     if (!priv)
0196         return -ENOMEM;
0197
0198     priv->dev = dev;
0199     priv->mode = PHY_MODE_INVALID;
0200
0201     priv->base = devm_platform_ioremap_resource(pdev, 0);
0202     if (IS_ERR(priv->base))
0203         return PTR_ERR(priv->base);
0204
0205     ret = qcom_ssphy_init_clock(priv);
0206     if (ret)
0207         return ret;
0208
0209     ret = qcom_ssphy_init_reset(priv);
0210     if (ret)
0211         return ret;
0212
0213     ret = qcom_ssphy_init_regulator(priv);
0214     if (ret)
0215         return ret;
0216
0217     phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops);
0218     if (IS_ERR(phy)) {
0219         dev_err(dev, "Failed to create the SS phy\n");
0220         return PTR_ERR(phy);
0221     }
0222
0223     phy_set_drvdata(phy, priv);
0224
0225     provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0226
0227     return PTR_ERR_OR_ZERO(provider);
0228 }
0229
0230 static const struct of_device_id qcom_ssphy_match[] = {
0231     { .compatible = "qcom,usb-ss-28nm-phy", },
0232     { },
0233 };
0234 MODULE_DEVICE_TABLE(of, qcom_ssphy_match);
0235
0236 static struct platform_driver qcom_ssphy_driver = {
0237     .probe      = qcom_ssphy_probe,
0238     .driver = {
0239         .name   = "qcom-usb-ssphy",
0240         .of_match_table = qcom_ssphy_match,
0241     },
0242 };
0243 module_platform_driver(qcom_ssphy_driver);
0244
0245 MODULE_DESCRIPTION("Qualcomm SuperSpeed USB PHY driver");
0246 MODULE_LICENSE("GPL v2");