phy/qualcomm/phy-qcom-snps-femto-v2.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/err.h>
0009 #include <linux/io.h>
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_device.h>
0014 #include <linux/phy/phy.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regmap.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <linux/reset.h>
0019 #include <linux/slab.h>
0020
0021 #define USB2_PHY_USB_PHY_UTMI_CTRL0     (0x3c)
0022 #define SLEEPM                  BIT(0)
0023 #define OPMODE_MASK             GENMASK(4, 3)
0024 #define OPMODE_NORMAL               (0x00)
0025 #define OPMODE_NONDRIVING           BIT(3)
0026 #define TERMSEL                 BIT(5)
0027
0028 #define USB2_PHY_USB_PHY_UTMI_CTRL1     (0x40)
0029 #define XCVRSEL                 BIT(0)
0030
0031 #define USB2_PHY_USB_PHY_UTMI_CTRL5     (0x50)
0032 #define POR                 BIT(1)
0033
0034 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0    (0x54)
0035 #define SIDDQ                   BIT(2)
0036 #define RETENABLEN              BIT(3)
0037 #define FSEL_MASK               GENMASK(6, 4)
0038 #define FSEL_DEFAULT                (0x3 << 4)
0039
0040 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1    (0x58)
0041 #define VBUSVLDEXTSEL0              BIT(4)
0042 #define PLLBTUNE                BIT(5)
0043
0044 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2    (0x5c)
0045 #define VREGBYPASS              BIT(0)
0046
0047 #define USB2_PHY_USB_PHY_HS_PHY_CTRL1       (0x60)
0048 #define VBUSVLDEXT0             BIT(0)
0049
0050 #define USB2_PHY_USB_PHY_HS_PHY_CTRL2       (0x64)
0051 #define USB2_AUTO_RESUME            BIT(0)
0052 #define USB2_SUSPEND_N              BIT(2)
0053 #define USB2_SUSPEND_N_SEL          BIT(3)
0054
0055 #define USB2_PHY_USB_PHY_CFG0           (0x94)
0056 #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN  BIT(0)
0057 #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN       BIT(1)
0058
0059 #define USB2_PHY_USB_PHY_REFCLK_CTRL        (0xa0)
0060 #define REFCLK_SEL_MASK             GENMASK(1, 0)
0061 #define REFCLK_SEL_DEFAULT          (0x2 << 0)
0062
0063 static const char * const qcom_snps_hsphy_vreg_names[] = {
0064     "vdda-pll", "vdda33", "vdda18",
0065 };
0066
0067 #define SNPS_HS_NUM_VREGS       ARRAY_SIZE(qcom_snps_hsphy_vreg_names)
0068
0069 /**
0070  * struct qcom_snps_hsphy - snps hs phy attributes
0071  *
0072  * @phy: generic phy
0073  * @base: iomapped memory space for snps hs phy
0074  *
0075  * @cfg_ahb_clk: AHB2PHY interface clock
0076  * @ref_clk: phy reference clock
0077  * @iface_clk: phy interface clock
0078  * @phy_reset: phy reset control
0079  * @vregs: regulator supplies bulk data
0080  * @phy_initialized: if PHY has been initialized correctly
0081  * @mode: contains the current mode the PHY is in
0082  */
0083 struct qcom_snps_hsphy {
0084     struct phy *phy;
0085     void __iomem *base;
0086
0087     struct clk *cfg_ahb_clk;
0088     struct clk *ref_clk;
0089     struct reset_control *phy_reset;
0090     struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
0091
0092     bool phy_initialized;
0093     enum phy_mode mode;
0094 };
0095
0096 static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
0097                         u32 mask, u32 val)
0098 {
0099     u32 reg;
0100
0101     reg = readl_relaxed(base + offset);
0102     reg &= ~mask;
0103     reg |= val & mask;
0104     writel_relaxed(reg, base + offset);
0105
0106     /* Ensure above write is completed */
0107     readl_relaxed(base + offset);
0108 }
0109
0110 static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy)
0111 {
0112     dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");
0113
0114     if (hsphy->mode == PHY_MODE_USB_HOST) {
0115         /* Enable auto-resume to meet remote wakeup timing */
0116         qcom_snps_hsphy_write_mask(hsphy->base,
0117                        USB2_PHY_USB_PHY_HS_PHY_CTRL2,
0118                        USB2_AUTO_RESUME,
0119                        USB2_AUTO_RESUME);
0120         usleep_range(500, 1000);
0121         qcom_snps_hsphy_write_mask(hsphy->base,
0122                        USB2_PHY_USB_PHY_HS_PHY_CTRL2,
0123                        0, USB2_AUTO_RESUME);
0124     }
0125
0126     clk_disable_unprepare(hsphy->cfg_ahb_clk);
0127     return 0;
0128 }
0129
0130 static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy)
0131 {
0132     int ret;
0133
0134     dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");
0135
0136     ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
0137     if (ret) {
0138         dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n");
0139         return ret;
0140     }
0141
0142     return 0;
0143 }
0144
0145 static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *dev)
0146 {
0147     struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
0148
0149     if (!hsphy->phy_initialized)
0150         return 0;
0151
0152     qcom_snps_hsphy_suspend(hsphy);
0153     return 0;
0154 }
0155
0156 static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev)
0157 {
0158     struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
0159
0160     if (!hsphy->phy_initialized)
0161         return 0;
0162
0163     qcom_snps_hsphy_resume(hsphy);
0164     return 0;
0165 }
0166
0167 static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
0168                     int submode)
0169 {
0170     struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
0171
0172     hsphy->mode = mode;
0173     return 0;
0174 }
0175
0176 static int qcom_snps_hsphy_init(struct phy *phy)
0177 {
0178     struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
0179     int ret;
0180
0181     dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);
0182
0183     ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
0184     if (ret)
0185         return ret;
0186
0187     ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
0188     if (ret) {
0189         dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
0190         goto poweroff_phy;
0191     }
0192
0193     ret = reset_control_assert(hsphy->phy_reset);
0194     if (ret) {
0195         dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
0196         goto disable_ahb_clk;
0197     }
0198
0199     usleep_range(100, 150);
0200
0201     ret = reset_control_deassert(hsphy->phy_reset);
0202     if (ret) {
0203         dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
0204         goto disable_ahb_clk;
0205     }
0206
0207     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
0208                     UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
0209                     UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
0210     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
0211                             POR, POR);
0212     qcom_snps_hsphy_write_mask(hsphy->base,
0213                     USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
0214                     FSEL_MASK, 0);
0215     qcom_snps_hsphy_write_mask(hsphy->base,
0216                     USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
0217                     PLLBTUNE, PLLBTUNE);
0218     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
0219                     REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK);
0220     qcom_snps_hsphy_write_mask(hsphy->base,
0221                     USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
0222                     VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
0223     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
0224                     VBUSVLDEXT0, VBUSVLDEXT0);
0225
0226     qcom_snps_hsphy_write_mask(hsphy->base,
0227                     USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
0228                     VREGBYPASS, VREGBYPASS);
0229
0230     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
0231                     USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
0232                     USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
0233
0234     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
0235                     SLEEPM, SLEEPM);
0236
0237     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
0238                    SIDDQ, 0);
0239
0240     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
0241                     POR, 0);
0242
0243     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
0244                     USB2_SUSPEND_N_SEL, 0);
0245
0246     qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
0247                     UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
0248
0249     hsphy->phy_initialized = true;
0250
0251     return 0;
0252
0253 disable_ahb_clk:
0254     clk_disable_unprepare(hsphy->cfg_ahb_clk);
0255 poweroff_phy:
0256     regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
0257
0258     return ret;
0259 }
0260
0261 static int qcom_snps_hsphy_exit(struct phy *phy)
0262 {
0263     struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
0264
0265     reset_control_assert(hsphy->phy_reset);
0266     clk_disable_unprepare(hsphy->cfg_ahb_clk);
0267     regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
0268     hsphy->phy_initialized = false;
0269
0270     return 0;
0271 }
0272
0273 static const struct phy_ops qcom_snps_hsphy_gen_ops = {
0274     .init       = qcom_snps_hsphy_init,
0275     .exit       = qcom_snps_hsphy_exit,
0276     .set_mode   = qcom_snps_hsphy_set_mode,
0277     .owner      = THIS_MODULE,
0278 };
0279
0280 static const struct of_device_id qcom_snps_hsphy_of_match_table[] = {
0281     { .compatible   = "qcom,sm8150-usb-hs-phy", },
0282     { .compatible   = "qcom,usb-snps-hs-5nm-phy", },
0283     { .compatible   = "qcom,usb-snps-hs-7nm-phy", },
0284     { .compatible   = "qcom,usb-snps-femto-v2-phy", },
0285     { }
0286 };
0287 MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table);
0288
0289 static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = {
0290     SET_RUNTIME_PM_OPS(qcom_snps_hsphy_runtime_suspend,
0291                qcom_snps_hsphy_runtime_resume, NULL)
0292 };
0293
0294 static int qcom_snps_hsphy_probe(struct platform_device *pdev)
0295 {
0296     struct device *dev = &pdev->dev;
0297     struct qcom_snps_hsphy *hsphy;
0298     struct phy_provider *phy_provider;
0299     struct phy *generic_phy;
0300     int ret, i;
0301     int num;
0302
0303     hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL);
0304     if (!hsphy)
0305         return -ENOMEM;
0306
0307     hsphy->base = devm_platform_ioremap_resource(pdev, 0);
0308     if (IS_ERR(hsphy->base))
0309         return PTR_ERR(hsphy->base);
0310
0311     hsphy->ref_clk = devm_clk_get(dev, "ref");
0312     if (IS_ERR(hsphy->ref_clk)) {
0313         ret = PTR_ERR(hsphy->ref_clk);
0314         if (ret != -EPROBE_DEFER)
0315             dev_err(dev, "failed to get ref clk, %d\n", ret);
0316         return ret;
0317     }
0318
0319     hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0320     if (IS_ERR(hsphy->phy_reset)) {
0321         dev_err(dev, "failed to get phy core reset\n");
0322         return PTR_ERR(hsphy->phy_reset);
0323     }
0324
0325     num = ARRAY_SIZE(hsphy->vregs);
0326     for (i = 0; i < num; i++)
0327         hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];
0328
0329     ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);
0330     if (ret) {
0331         if (ret != -EPROBE_DEFER)
0332             dev_err(dev, "failed to get regulator supplies: %d\n",
0333                 ret);
0334         return ret;
0335     }
0336
0337     pm_runtime_set_active(dev);
0338     pm_runtime_enable(dev);
0339     /*
0340      * Prevent runtime pm from being ON by default. Users can enable
0341      * it using power/control in sysfs.
0342      */
0343     pm_runtime_forbid(dev);
0344
0345     generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops);
0346     if (IS_ERR(generic_phy)) {
0347         ret = PTR_ERR(generic_phy);
0348         dev_err(dev, "failed to create phy, %d\n", ret);
0349         return ret;
0350     }
0351     hsphy->phy = generic_phy;
0352
0353     dev_set_drvdata(dev, hsphy);
0354     phy_set_drvdata(generic_phy, hsphy);
0355
0356     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0357     if (!IS_ERR(phy_provider))
0358         dev_dbg(dev, "Registered Qcom-SNPS HS phy\n");
0359     else
0360         pm_runtime_disable(dev);
0361
0362     return PTR_ERR_OR_ZERO(phy_provider);
0363 }
0364
0365 static struct platform_driver qcom_snps_hsphy_driver = {
0366     .probe      = qcom_snps_hsphy_probe,
0367     .driver = {
0368         .name   = "qcom-snps-hs-femto-v2-phy",
0369         .pm = &qcom_snps_hsphy_pm_ops,
0370         .of_match_table = qcom_snps_hsphy_of_match_table,
0371     },
0372 };
0373
0374 module_platform_driver(qcom_snps_hsphy_driver);
0375
0376 MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver");
0377 MODULE_LICENSE("GPL v2");