Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/err.h>
0009 #include <linux/io.h>
0010 #include <linux/kernel.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/module.h>
0013 #include <linux/nvmem-consumer.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/phy/phy.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/regmap.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <linux/reset.h>
0021 #include <linux/slab.h>
0022 
0023 #include <dt-bindings/phy/phy-qcom-qusb2.h>
0024 
0025 #define QUSB2PHY_PLL            0x0
0026 #define QUSB2PHY_PLL_TEST       0x04
0027 #define CLK_REF_SEL         BIT(7)
0028 
0029 #define QUSB2PHY_PLL_TUNE       0x08
0030 #define QUSB2PHY_PLL_USER_CTL1      0x0c
0031 #define QUSB2PHY_PLL_USER_CTL2      0x10
0032 #define QUSB2PHY_PLL_AUTOPGM_CTL1   0x1c
0033 #define QUSB2PHY_PLL_PWR_CTRL       0x18
0034 
0035 /* QUSB2PHY_PLL_STATUS register bits */
0036 #define PLL_LOCKED          BIT(5)
0037 
0038 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
0039 #define CORE_READY_STATUS       BIT(0)
0040 
0041 /* QUSB2PHY_PORT_POWERDOWN register bits */
0042 #define CLAMP_N_EN          BIT(5)
0043 #define FREEZIO_N           BIT(1)
0044 #define POWER_DOWN          BIT(0)
0045 
0046 /* QUSB2PHY_PWR_CTRL1 register bits */
0047 #define PWR_CTRL1_VREF_SUPPLY_TRIM  BIT(5)
0048 #define PWR_CTRL1_CLAMP_N_EN        BIT(1)
0049 
0050 #define QUSB2PHY_REFCLK_ENABLE      BIT(0)
0051 
0052 #define PHY_CLK_SCHEME_SEL      BIT(0)
0053 
0054 /* QUSB2PHY_INTR_CTRL register bits */
0055 #define DMSE_INTR_HIGH_SEL          BIT(4)
0056 #define DPSE_INTR_HIGH_SEL          BIT(3)
0057 #define CHG_DET_INTR_EN             BIT(2)
0058 #define DMSE_INTR_EN                BIT(1)
0059 #define DPSE_INTR_EN                BIT(0)
0060 
0061 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
0062 #define CORE_PLL_EN_FROM_RESET          BIT(4)
0063 #define CORE_RESET              BIT(5)
0064 #define CORE_RESET_MUX              BIT(6)
0065 
0066 /* QUSB2PHY_IMP_CTRL1 register bits */
0067 #define IMP_RES_OFFSET_MASK         GENMASK(5, 0)
0068 #define IMP_RES_OFFSET_SHIFT            0x0
0069 
0070 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
0071 #define BIAS_CTRL2_RES_OFFSET_MASK      GENMASK(5, 0)
0072 #define BIAS_CTRL2_RES_OFFSET_SHIFT     0x0
0073 
0074 /* QUSB2PHY_CHG_CONTROL_2 register bits */
0075 #define CHG_CTRL2_OFFSET_MASK           GENMASK(5, 4)
0076 #define CHG_CTRL2_OFFSET_SHIFT          0x4
0077 
0078 /* QUSB2PHY_PORT_TUNE1 register bits */
0079 #define HSTX_TRIM_MASK              GENMASK(7, 4)
0080 #define HSTX_TRIM_SHIFT             0x4
0081 #define PREEMPH_WIDTH_HALF_BIT          BIT(2)
0082 #define PREEMPHASIS_EN_MASK         GENMASK(1, 0)
0083 #define PREEMPHASIS_EN_SHIFT            0x0
0084 
0085 /* QUSB2PHY_PORT_TUNE2 register bits */
0086 #define HSDISC_TRIM_MASK            GENMASK(1, 0)
0087 #define HSDISC_TRIM_SHIFT           0x0
0088 
0089 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO    0x04
0090 #define QUSB2PHY_PLL_CLOCK_INVERTERS        0x18c
0091 #define QUSB2PHY_PLL_CMODE          0x2c
0092 #define QUSB2PHY_PLL_LOCK_DELAY         0x184
0093 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO     0xb4
0094 #define QUSB2PHY_PLL_BIAS_CONTROL_1     0x194
0095 #define QUSB2PHY_PLL_BIAS_CONTROL_2     0x198
0096 #define QUSB2PHY_PWR_CTRL2          0x214
0097 #define QUSB2PHY_IMP_CTRL1          0x220
0098 #define QUSB2PHY_IMP_CTRL2          0x224
0099 #define QUSB2PHY_CHG_CTRL2          0x23c
0100 
0101 struct qusb2_phy_init_tbl {
0102     unsigned int offset;
0103     unsigned int val;
0104     /*
0105      * register part of layout ?
0106      * if yes, then offset gives index in the reg-layout
0107      */
0108     int in_layout;
0109 };
0110 
0111 #define QUSB2_PHY_INIT_CFG(o, v) \
0112     {           \
0113         .offset = o,    \
0114         .val = v,   \
0115     }
0116 
0117 #define QUSB2_PHY_INIT_CFG_L(o, v) \
0118     {           \
0119         .offset = o,    \
0120         .val = v,   \
0121         .in_layout = 1, \
0122     }
0123 
0124 /* set of registers with offsets different per-PHY */
0125 enum qusb2phy_reg_layout {
0126     QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
0127     QUSB2PHY_PLL_STATUS,
0128     QUSB2PHY_PORT_TUNE1,
0129     QUSB2PHY_PORT_TUNE2,
0130     QUSB2PHY_PORT_TUNE3,
0131     QUSB2PHY_PORT_TUNE4,
0132     QUSB2PHY_PORT_TUNE5,
0133     QUSB2PHY_PORT_TEST1,
0134     QUSB2PHY_PORT_TEST2,
0135     QUSB2PHY_PORT_POWERDOWN,
0136     QUSB2PHY_INTR_CTRL,
0137 };
0138 
0139 static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
0140     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
0141     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8),
0142     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3),
0143     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
0144     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0),
0145     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
0146     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
0147     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
0148     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
0149     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
0150     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
0151     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
0152     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
0153 };
0154 
0155 static const unsigned int ipq6018_regs_layout[] = {
0156     [QUSB2PHY_PLL_STATUS]              = 0x38,
0157     [QUSB2PHY_PORT_TUNE1]              = 0x80,
0158     [QUSB2PHY_PORT_TUNE2]              = 0x84,
0159     [QUSB2PHY_PORT_TUNE3]              = 0x88,
0160     [QUSB2PHY_PORT_TUNE4]              = 0x8C,
0161     [QUSB2PHY_PORT_TUNE5]              = 0x90,
0162     [QUSB2PHY_PORT_TEST1]              = 0x98,
0163     [QUSB2PHY_PORT_TEST2]              = 0x9C,
0164     [QUSB2PHY_PORT_POWERDOWN]          = 0xB4,
0165     [QUSB2PHY_INTR_CTRL]               = 0xBC,
0166 };
0167 
0168 static const unsigned int msm8996_regs_layout[] = {
0169     [QUSB2PHY_PLL_STATUS]       = 0x38,
0170     [QUSB2PHY_PORT_TUNE1]       = 0x80,
0171     [QUSB2PHY_PORT_TUNE2]       = 0x84,
0172     [QUSB2PHY_PORT_TUNE3]       = 0x88,
0173     [QUSB2PHY_PORT_TUNE4]       = 0x8c,
0174     [QUSB2PHY_PORT_TUNE5]       = 0x90,
0175     [QUSB2PHY_PORT_TEST1]       = 0xb8,
0176     [QUSB2PHY_PORT_TEST2]       = 0x9c,
0177     [QUSB2PHY_PORT_POWERDOWN]   = 0xb4,
0178     [QUSB2PHY_INTR_CTRL]        = 0xbc,
0179 };
0180 
0181 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
0182     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
0183     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
0184     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
0185     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
0186 
0187     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
0188     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
0189     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
0190 
0191     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
0192 
0193     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
0194     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
0195 };
0196 
0197 static const unsigned int msm8998_regs_layout[] = {
0198     [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
0199     [QUSB2PHY_PLL_STATUS]              = 0x1a0,
0200     [QUSB2PHY_PORT_TUNE1]              = 0x23c,
0201     [QUSB2PHY_PORT_TUNE2]              = 0x240,
0202     [QUSB2PHY_PORT_TUNE3]              = 0x244,
0203     [QUSB2PHY_PORT_TUNE4]              = 0x248,
0204     [QUSB2PHY_PORT_TEST1]              = 0x24c,
0205     [QUSB2PHY_PORT_TEST2]              = 0x250,
0206     [QUSB2PHY_PORT_POWERDOWN]          = 0x210,
0207     [QUSB2PHY_INTR_CTRL]               = 0x22c,
0208 };
0209 
0210 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
0211     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13),
0212     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
0213     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
0214     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
0215 
0216     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5),
0217     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09),
0218 
0219     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
0220 };
0221 
0222 static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {
0223     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
0224     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
0225     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81),
0226     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17),
0227 
0228     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
0229     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
0230     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
0231 
0232     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
0233 
0234     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
0235     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
0236 };
0237 
0238 static const unsigned int qusb2_v2_regs_layout[] = {
0239     [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
0240     [QUSB2PHY_PLL_STATUS]       = 0x1a0,
0241     [QUSB2PHY_PORT_TUNE1]       = 0x240,
0242     [QUSB2PHY_PORT_TUNE2]       = 0x244,
0243     [QUSB2PHY_PORT_TUNE3]       = 0x248,
0244     [QUSB2PHY_PORT_TUNE4]       = 0x24c,
0245     [QUSB2PHY_PORT_TUNE5]       = 0x250,
0246     [QUSB2PHY_PORT_TEST1]       = 0x254,
0247     [QUSB2PHY_PORT_TEST2]       = 0x258,
0248     [QUSB2PHY_PORT_POWERDOWN]   = 0x210,
0249     [QUSB2PHY_INTR_CTRL]        = 0x230,
0250 };
0251 
0252 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
0253     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
0254     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
0255     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
0256     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
0257     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
0258     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
0259     QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
0260     QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
0261     QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
0262     QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
0263 
0264     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
0265     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
0266     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
0267     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
0268     QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
0269 
0270     QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
0271 };
0272 
0273 struct qusb2_phy_cfg {
0274     const struct qusb2_phy_init_tbl *tbl;
0275     /* number of entries in the table */
0276     unsigned int tbl_num;
0277     /* offset to PHY_CLK_SCHEME register in TCSR map */
0278     unsigned int clk_scheme_offset;
0279 
0280     /* array of registers with different offsets */
0281     const unsigned int *regs;
0282     unsigned int mask_core_ready;
0283     unsigned int disable_ctrl;
0284     unsigned int autoresume_en;
0285 
0286     /* true if PHY has PLL_TEST register to select clk_scheme */
0287     bool has_pll_test;
0288 
0289     /* true if TUNE1 register must be updated by fused value, else TUNE2 */
0290     bool update_tune1_with_efuse;
0291 
0292     /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
0293     bool has_pll_override;
0294 
0295     /* true if PHY default clk scheme is single-ended */
0296     bool se_clk_scheme_default;
0297 };
0298 
0299 static const struct qusb2_phy_cfg msm8996_phy_cfg = {
0300     .tbl        = msm8996_init_tbl,
0301     .tbl_num    = ARRAY_SIZE(msm8996_init_tbl),
0302     .regs       = msm8996_regs_layout,
0303 
0304     .has_pll_test   = true,
0305     .se_clk_scheme_default = true,
0306     .disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
0307     .mask_core_ready = PLL_LOCKED,
0308     .autoresume_en   = BIT(3),
0309 };
0310 
0311 static const struct qusb2_phy_cfg msm8998_phy_cfg = {
0312     .tbl            = msm8998_init_tbl,
0313     .tbl_num        = ARRAY_SIZE(msm8998_init_tbl),
0314     .regs           = msm8998_regs_layout,
0315 
0316     .disable_ctrl   = POWER_DOWN,
0317     .mask_core_ready = CORE_READY_STATUS,
0318     .has_pll_override = true,
0319     .se_clk_scheme_default = true,
0320     .autoresume_en   = BIT(0),
0321     .update_tune1_with_efuse = true,
0322 };
0323 
0324 static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
0325     .tbl            = ipq6018_init_tbl,
0326     .tbl_num        = ARRAY_SIZE(ipq6018_init_tbl),
0327     .regs           = ipq6018_regs_layout,
0328 
0329     .disable_ctrl   = POWER_DOWN,
0330     .mask_core_ready = PLL_LOCKED,
0331     /* autoresume not used */
0332     .autoresume_en   = BIT(0),
0333 };
0334 
0335 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
0336     .tbl        = qusb2_v2_init_tbl,
0337     .tbl_num    = ARRAY_SIZE(qusb2_v2_init_tbl),
0338     .regs       = qusb2_v2_regs_layout,
0339 
0340     .disable_ctrl   = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
0341                POWER_DOWN),
0342     .mask_core_ready = CORE_READY_STATUS,
0343     .has_pll_override = true,
0344     .se_clk_scheme_default = true,
0345     .autoresume_en    = BIT(0),
0346     .update_tune1_with_efuse = true,
0347 };
0348 
0349 static const struct qusb2_phy_cfg sdm660_phy_cfg = {
0350     .tbl        = msm8996_init_tbl,
0351     .tbl_num    = ARRAY_SIZE(msm8996_init_tbl),
0352     .regs       = msm8996_regs_layout,
0353 
0354     .has_pll_test   = true,
0355     .se_clk_scheme_default = false,
0356     .disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
0357     .mask_core_ready = PLL_LOCKED,
0358     .autoresume_en   = BIT(3),
0359 };
0360 
0361 static const struct qusb2_phy_cfg sm6115_phy_cfg = {
0362     .tbl        = sm6115_init_tbl,
0363     .tbl_num    = ARRAY_SIZE(sm6115_init_tbl),
0364     .regs       = msm8996_regs_layout,
0365 
0366     .has_pll_test   = true,
0367     .se_clk_scheme_default = true,
0368     .disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
0369     .mask_core_ready = PLL_LOCKED,
0370     .autoresume_en   = BIT(3),
0371 };
0372 
0373 static const char * const qusb2_phy_vreg_names[] = {
0374     "vdd", "vdda-pll", "vdda-phy-dpdm",
0375 };
0376 
0377 #define QUSB2_NUM_VREGS     ARRAY_SIZE(qusb2_phy_vreg_names)
0378 
0379 /* struct override_param - structure holding qusb2 v2 phy overriding param
0380  * set override true if the  device tree property exists and read and assign
0381  * to value
0382  */
0383 struct override_param {
0384     bool override;
0385     u8 value;
0386 };
0387 
0388 /*struct override_params - structure holding qusb2 v2 phy overriding params
0389  * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register
0390  * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register
0391  * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
0392  * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
0393  * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register
0394  * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register
0395  * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register
0396  */
0397 struct override_params {
0398     struct override_param imp_res_offset;
0399     struct override_param hstx_trim;
0400     struct override_param preemphasis;
0401     struct override_param preemphasis_width;
0402     struct override_param bias_ctrl;
0403     struct override_param charge_ctrl;
0404     struct override_param hsdisc_trim;
0405 };
0406 
0407 /**
0408  * struct qusb2_phy - structure holding qusb2 phy attributes
0409  *
0410  * @phy: generic phy
0411  * @base: iomapped memory space for qubs2 phy
0412  *
0413  * @cfg_ahb_clk: AHB2PHY interface clock
0414  * @ref_clk: phy reference clock
0415  * @iface_clk: phy interface clock
0416  * @phy_reset: phy reset control
0417  * @vregs: regulator supplies bulk data
0418  *
0419  * @tcsr: TCSR syscon register map
0420  * @cell: nvmem cell containing phy tuning value
0421  *
0422  * @overrides: pointer to structure for all overriding tuning params
0423  *
0424  * @cfg: phy config data
0425  * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
0426  * @phy_initialized: indicate if PHY has been initialized
0427  * @mode: current PHY mode
0428  */
0429 struct qusb2_phy {
0430     struct phy *phy;
0431     void __iomem *base;
0432 
0433     struct clk *cfg_ahb_clk;
0434     struct clk *ref_clk;
0435     struct clk *iface_clk;
0436     struct reset_control *phy_reset;
0437     struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
0438 
0439     struct regmap *tcsr;
0440     struct nvmem_cell *cell;
0441 
0442     struct override_params overrides;
0443 
0444     const struct qusb2_phy_cfg *cfg;
0445     bool has_se_clk_scheme;
0446     bool phy_initialized;
0447     enum phy_mode mode;
0448 };
0449 
0450 static inline void qusb2_write_mask(void __iomem *base, u32 offset,
0451                     u32 val, u32 mask)
0452 {
0453     u32 reg;
0454 
0455     reg = readl(base + offset);
0456     reg &= ~mask;
0457     reg |= val & mask;
0458     writel(reg, base + offset);
0459 
0460     /* Ensure above write is completed */
0461     readl(base + offset);
0462 }
0463 
0464 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
0465 {
0466     u32 reg;
0467 
0468     reg = readl(base + offset);
0469     reg |= val;
0470     writel(reg, base + offset);
0471 
0472     /* Ensure above write is completed */
0473     readl(base + offset);
0474 }
0475 
0476 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
0477 {
0478     u32 reg;
0479 
0480     reg = readl(base + offset);
0481     reg &= ~val;
0482     writel(reg, base + offset);
0483 
0484     /* Ensure above write is completed */
0485     readl(base + offset);
0486 }
0487 
0488 static inline
0489 void qcom_qusb2_phy_configure(void __iomem *base,
0490                   const unsigned int *regs,
0491                   const struct qusb2_phy_init_tbl tbl[], int num)
0492 {
0493     int i;
0494 
0495     for (i = 0; i < num; i++) {
0496         if (tbl[i].in_layout)
0497             writel(tbl[i].val, base + regs[tbl[i].offset]);
0498         else
0499             writel(tbl[i].val, base + tbl[i].offset);
0500     }
0501 }
0502 
0503 /*
0504  * Update board specific PHY tuning override values if specified from
0505  * device tree.
0506  */
0507 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
0508 {
0509     const struct qusb2_phy_cfg *cfg = qphy->cfg;
0510     struct override_params *or = &qphy->overrides;
0511 
0512     if (or->imp_res_offset.override)
0513         qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
0514         or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
0515                  IMP_RES_OFFSET_MASK);
0516 
0517     if (or->bias_ctrl.override)
0518         qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
0519         or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
0520                BIAS_CTRL2_RES_OFFSET_MASK);
0521 
0522     if (or->charge_ctrl.override)
0523         qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
0524         or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
0525                  CHG_CTRL2_OFFSET_MASK);
0526 
0527     if (or->hstx_trim.override)
0528         qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
0529         or->hstx_trim.value << HSTX_TRIM_SHIFT,
0530                  HSTX_TRIM_MASK);
0531 
0532     if (or->preemphasis.override)
0533         qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
0534         or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
0535                 PREEMPHASIS_EN_MASK);
0536 
0537     if (or->preemphasis_width.override) {
0538         if (or->preemphasis_width.value ==
0539             QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
0540             qusb2_setbits(qphy->base,
0541                       cfg->regs[QUSB2PHY_PORT_TUNE1],
0542                       PREEMPH_WIDTH_HALF_BIT);
0543         else
0544             qusb2_clrbits(qphy->base,
0545                       cfg->regs[QUSB2PHY_PORT_TUNE1],
0546                       PREEMPH_WIDTH_HALF_BIT);
0547     }
0548 
0549     if (or->hsdisc_trim.override)
0550         qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
0551         or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
0552                  HSDISC_TRIM_MASK);
0553 }
0554 
0555 /*
0556  * Fetches HS Tx tuning value from nvmem and sets the
0557  * QUSB2PHY_PORT_TUNE1/2 register.
0558  * For error case, skip setting the value and use the default value.
0559  */
0560 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
0561 {
0562     struct device *dev = &qphy->phy->dev;
0563     const struct qusb2_phy_cfg *cfg = qphy->cfg;
0564     u8 *val, hstx_trim;
0565 
0566     /* efuse register is optional */
0567     if (!qphy->cell)
0568         return;
0569 
0570     /*
0571      * Read efuse register having TUNE2/1 parameter's high nibble.
0572      * If efuse register shows value as 0x0 (indicating value is not
0573      * fused), or if we fail to find a valid efuse register setting,
0574      * then use default value for high nibble that we have already
0575      * set while configuring the phy.
0576      */
0577     val = nvmem_cell_read(qphy->cell, NULL);
0578     if (IS_ERR(val)) {
0579         dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
0580         return;
0581     }
0582     hstx_trim = val[0];
0583     kfree(val);
0584     if (!hstx_trim) {
0585         dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
0586         return;
0587     }
0588 
0589     /* Fused TUNE1/2 value is the higher nibble only */
0590     if (cfg->update_tune1_with_efuse)
0591         qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
0592                  hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
0593     else
0594         qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
0595                  hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
0596 }
0597 
0598 static int qusb2_phy_set_mode(struct phy *phy,
0599                   enum phy_mode mode, int submode)
0600 {
0601     struct qusb2_phy *qphy = phy_get_drvdata(phy);
0602 
0603     qphy->mode = mode;
0604 
0605     return 0;
0606 }
0607 
0608 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
0609 {
0610     struct qusb2_phy *qphy = dev_get_drvdata(dev);
0611     const struct qusb2_phy_cfg *cfg = qphy->cfg;
0612     u32 intr_mask;
0613 
0614     dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
0615 
0616     if (!qphy->phy_initialized) {
0617         dev_vdbg(dev, "PHY not initialized, bailing out\n");
0618         return 0;
0619     }
0620 
0621     /*
0622      * Enable DP/DM interrupts to detect line state changes based on current
0623      * speed. In other words, enable the triggers _opposite_ of what the
0624      * current D+/D- levels are e.g. if currently D+ high, D- low
0625      * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
0626      */
0627     intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
0628     switch (qphy->mode) {
0629     case PHY_MODE_USB_HOST_HS:
0630     case PHY_MODE_USB_HOST_FS:
0631     case PHY_MODE_USB_DEVICE_HS:
0632     case PHY_MODE_USB_DEVICE_FS:
0633         intr_mask |= DMSE_INTR_HIGH_SEL;
0634         break;
0635     case PHY_MODE_USB_HOST_LS:
0636     case PHY_MODE_USB_DEVICE_LS:
0637         intr_mask |= DPSE_INTR_HIGH_SEL;
0638         break;
0639     default:
0640         /* No device connected, enable both DP/DM high interrupt */
0641         intr_mask |= DMSE_INTR_HIGH_SEL;
0642         intr_mask |= DPSE_INTR_HIGH_SEL;
0643         break;
0644     }
0645 
0646     writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
0647 
0648     /* hold core PLL into reset */
0649     if (cfg->has_pll_override) {
0650         qusb2_setbits(qphy->base,
0651                   cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
0652                   CORE_PLL_EN_FROM_RESET | CORE_RESET |
0653                   CORE_RESET_MUX);
0654     }
0655 
0656     /* enable phy auto-resume only if device is connected on bus */
0657     if (qphy->mode != PHY_MODE_INVALID) {
0658         qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
0659                   cfg->autoresume_en);
0660         /* Autoresume bit has to be toggled in order to enable it */
0661         qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
0662                   cfg->autoresume_en);
0663     }
0664 
0665     if (!qphy->has_se_clk_scheme)
0666         clk_disable_unprepare(qphy->ref_clk);
0667 
0668     clk_disable_unprepare(qphy->cfg_ahb_clk);
0669     clk_disable_unprepare(qphy->iface_clk);
0670 
0671     return 0;
0672 }
0673 
0674 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
0675 {
0676     struct qusb2_phy *qphy = dev_get_drvdata(dev);
0677     const struct qusb2_phy_cfg *cfg = qphy->cfg;
0678     int ret;
0679 
0680     dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
0681 
0682     if (!qphy->phy_initialized) {
0683         dev_vdbg(dev, "PHY not initialized, bailing out\n");
0684         return 0;
0685     }
0686 
0687     ret = clk_prepare_enable(qphy->iface_clk);
0688     if (ret) {
0689         dev_err(dev, "failed to enable iface_clk, %d\n", ret);
0690         return ret;
0691     }
0692 
0693     ret = clk_prepare_enable(qphy->cfg_ahb_clk);
0694     if (ret) {
0695         dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
0696         goto disable_iface_clk;
0697     }
0698 
0699     if (!qphy->has_se_clk_scheme) {
0700         ret = clk_prepare_enable(qphy->ref_clk);
0701         if (ret) {
0702             dev_err(dev, "failed to enable ref clk, %d\n", ret);
0703             goto disable_ahb_clk;
0704         }
0705     }
0706 
0707     writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
0708 
0709     /* bring core PLL out of reset */
0710     if (cfg->has_pll_override) {
0711         qusb2_clrbits(qphy->base,
0712                   cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
0713                   CORE_RESET | CORE_RESET_MUX);
0714     }
0715 
0716     return 0;
0717 
0718 disable_ahb_clk:
0719     clk_disable_unprepare(qphy->cfg_ahb_clk);
0720 disable_iface_clk:
0721     clk_disable_unprepare(qphy->iface_clk);
0722 
0723     return ret;
0724 }
0725 
0726 static int qusb2_phy_init(struct phy *phy)
0727 {
0728     struct qusb2_phy *qphy = phy_get_drvdata(phy);
0729     const struct qusb2_phy_cfg *cfg = qphy->cfg;
0730     unsigned int val = 0;
0731     unsigned int clk_scheme;
0732     int ret;
0733 
0734     dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
0735 
0736     /* turn on regulator supplies */
0737     ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
0738     if (ret)
0739         return ret;
0740 
0741     ret = clk_prepare_enable(qphy->iface_clk);
0742     if (ret) {
0743         dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
0744         goto poweroff_phy;
0745     }
0746 
0747     /* enable ahb interface clock to program phy */
0748     ret = clk_prepare_enable(qphy->cfg_ahb_clk);
0749     if (ret) {
0750         dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
0751         goto disable_iface_clk;
0752     }
0753 
0754     /* Perform phy reset */
0755     ret = reset_control_assert(qphy->phy_reset);
0756     if (ret) {
0757         dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
0758         goto disable_ahb_clk;
0759     }
0760 
0761     /* 100 us delay to keep PHY in reset mode */
0762     usleep_range(100, 150);
0763 
0764     ret = reset_control_deassert(qphy->phy_reset);
0765     if (ret) {
0766         dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
0767         goto disable_ahb_clk;
0768     }
0769 
0770     /* Disable the PHY */
0771     qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
0772               qphy->cfg->disable_ctrl);
0773 
0774     if (cfg->has_pll_test) {
0775         /* save reset value to override reference clock scheme later */
0776         val = readl(qphy->base + QUSB2PHY_PLL_TEST);
0777     }
0778 
0779     qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
0780                  cfg->tbl_num);
0781 
0782     /* Override board specific PHY tuning values */
0783     qusb2_phy_override_phy_params(qphy);
0784 
0785     /* Set efuse value for tuning the PHY */
0786     qusb2_phy_set_tune2_param(qphy);
0787 
0788     /* Enable the PHY */
0789     qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
0790               POWER_DOWN);
0791 
0792     /* Required to get phy pll lock successfully */
0793     usleep_range(150, 160);
0794 
0795     /*
0796      * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
0797      * register in the TCSR so, if there's none, use the default
0798      * value hardcoded in the configuration.
0799      */
0800     qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
0801 
0802     /*
0803      * read TCSR_PHY_CLK_SCHEME register to check if single-ended
0804      * clock scheme is selected. If yes, then disable differential
0805      * ref_clk and use single-ended clock, otherwise use differential
0806      * ref_clk only.
0807      */
0808     if (qphy->tcsr) {
0809         ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
0810                   &clk_scheme);
0811         if (ret) {
0812             dev_err(&phy->dev, "failed to read clk scheme reg\n");
0813             goto assert_phy_reset;
0814         }
0815 
0816         /* is it a differential clock scheme ? */
0817         if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
0818             dev_vdbg(&phy->dev, "%s(): select differential clk\n",
0819                  __func__);
0820             qphy->has_se_clk_scheme = false;
0821         } else {
0822             dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
0823                  __func__);
0824         }
0825     }
0826 
0827     if (!qphy->has_se_clk_scheme) {
0828         ret = clk_prepare_enable(qphy->ref_clk);
0829         if (ret) {
0830             dev_err(&phy->dev, "failed to enable ref clk, %d\n",
0831                 ret);
0832             goto assert_phy_reset;
0833         }
0834     }
0835 
0836     if (cfg->has_pll_test) {
0837         if (!qphy->has_se_clk_scheme)
0838             val &= ~CLK_REF_SEL;
0839         else
0840             val |= CLK_REF_SEL;
0841 
0842         writel(val, qphy->base + QUSB2PHY_PLL_TEST);
0843 
0844         /* ensure above write is through */
0845         readl(qphy->base + QUSB2PHY_PLL_TEST);
0846     }
0847 
0848     /* Required to get phy pll lock successfully */
0849     usleep_range(100, 110);
0850 
0851     val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
0852     if (!(val & cfg->mask_core_ready)) {
0853         dev_err(&phy->dev,
0854             "QUSB2PHY pll lock failed: status reg = %x\n", val);
0855         ret = -EBUSY;
0856         goto disable_ref_clk;
0857     }
0858     qphy->phy_initialized = true;
0859 
0860     return 0;
0861 
0862 disable_ref_clk:
0863     if (!qphy->has_se_clk_scheme)
0864         clk_disable_unprepare(qphy->ref_clk);
0865 assert_phy_reset:
0866     reset_control_assert(qphy->phy_reset);
0867 disable_ahb_clk:
0868     clk_disable_unprepare(qphy->cfg_ahb_clk);
0869 disable_iface_clk:
0870     clk_disable_unprepare(qphy->iface_clk);
0871 poweroff_phy:
0872     regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
0873 
0874     return ret;
0875 }
0876 
0877 static int qusb2_phy_exit(struct phy *phy)
0878 {
0879     struct qusb2_phy *qphy = phy_get_drvdata(phy);
0880 
0881     /* Disable the PHY */
0882     qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
0883               qphy->cfg->disable_ctrl);
0884 
0885     if (!qphy->has_se_clk_scheme)
0886         clk_disable_unprepare(qphy->ref_clk);
0887 
0888     reset_control_assert(qphy->phy_reset);
0889 
0890     clk_disable_unprepare(qphy->cfg_ahb_clk);
0891     clk_disable_unprepare(qphy->iface_clk);
0892 
0893     regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
0894 
0895     qphy->phy_initialized = false;
0896 
0897     return 0;
0898 }
0899 
0900 static const struct phy_ops qusb2_phy_gen_ops = {
0901     .init       = qusb2_phy_init,
0902     .exit       = qusb2_phy_exit,
0903     .set_mode   = qusb2_phy_set_mode,
0904     .owner      = THIS_MODULE,
0905 };
0906 
0907 static const struct of_device_id qusb2_phy_of_match_table[] = {
0908     {
0909         .compatible = "qcom,ipq6018-qusb2-phy",
0910         .data       = &ipq6018_phy_cfg,
0911     }, {
0912         .compatible = "qcom,ipq8074-qusb2-phy",
0913         .data       = &msm8996_phy_cfg,
0914     }, {
0915         .compatible = "qcom,msm8953-qusb2-phy",
0916         .data       = &msm8996_phy_cfg,
0917     }, {
0918         .compatible = "qcom,msm8996-qusb2-phy",
0919         .data       = &msm8996_phy_cfg,
0920     }, {
0921         .compatible = "qcom,msm8998-qusb2-phy",
0922         .data       = &msm8998_phy_cfg,
0923     }, {
0924         .compatible = "qcom,qcm2290-qusb2-phy",
0925         .data       = &sm6115_phy_cfg,
0926     }, {
0927         .compatible = "qcom,sdm660-qusb2-phy",
0928         .data       = &sdm660_phy_cfg,
0929     }, {
0930         .compatible = "qcom,sm4250-qusb2-phy",
0931         .data       = &sm6115_phy_cfg,
0932     }, {
0933         .compatible = "qcom,sm6115-qusb2-phy",
0934         .data       = &sm6115_phy_cfg,
0935     }, {
0936         /*
0937          * Deprecated. Only here to support legacy device
0938          * trees that didn't include "qcom,qusb2-v2-phy"
0939          */
0940         .compatible = "qcom,sdm845-qusb2-phy",
0941         .data       = &qusb2_v2_phy_cfg,
0942     }, {
0943         .compatible = "qcom,qusb2-v2-phy",
0944         .data       = &qusb2_v2_phy_cfg,
0945     },
0946     { },
0947 };
0948 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
0949 
0950 static const struct dev_pm_ops qusb2_phy_pm_ops = {
0951     SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
0952                qusb2_phy_runtime_resume, NULL)
0953 };
0954 
0955 static int qusb2_phy_probe(struct platform_device *pdev)
0956 {
0957     struct device *dev = &pdev->dev;
0958     struct qusb2_phy *qphy;
0959     struct phy_provider *phy_provider;
0960     struct phy *generic_phy;
0961     int ret, i;
0962     int num;
0963     u32 value;
0964     struct override_params *or;
0965 
0966     qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
0967     if (!qphy)
0968         return -ENOMEM;
0969     or = &qphy->overrides;
0970 
0971     qphy->base = devm_platform_ioremap_resource(pdev, 0);
0972     if (IS_ERR(qphy->base))
0973         return PTR_ERR(qphy->base);
0974 
0975     qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
0976     if (IS_ERR(qphy->cfg_ahb_clk)) {
0977         ret = PTR_ERR(qphy->cfg_ahb_clk);
0978         if (ret != -EPROBE_DEFER)
0979             dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
0980         return ret;
0981     }
0982 
0983     qphy->ref_clk = devm_clk_get(dev, "ref");
0984     if (IS_ERR(qphy->ref_clk)) {
0985         ret = PTR_ERR(qphy->ref_clk);
0986         if (ret != -EPROBE_DEFER)
0987             dev_err(dev, "failed to get ref clk, %d\n", ret);
0988         return ret;
0989     }
0990 
0991     qphy->iface_clk = devm_clk_get_optional(dev, "iface");
0992     if (IS_ERR(qphy->iface_clk))
0993         return PTR_ERR(qphy->iface_clk);
0994 
0995     qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
0996     if (IS_ERR(qphy->phy_reset)) {
0997         dev_err(dev, "failed to get phy core reset\n");
0998         return PTR_ERR(qphy->phy_reset);
0999     }
1000 
1001     num = ARRAY_SIZE(qphy->vregs);
1002     for (i = 0; i < num; i++)
1003         qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
1004 
1005     ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
1006     if (ret) {
1007         if (ret != -EPROBE_DEFER)
1008             dev_err(dev, "failed to get regulator supplies: %d\n",
1009                 ret);
1010         return ret;
1011     }
1012 
1013     /* Get the specific init parameters of QMP phy */
1014     qphy->cfg = of_device_get_match_data(dev);
1015 
1016     qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
1017                             "qcom,tcsr-syscon");
1018     if (IS_ERR(qphy->tcsr)) {
1019         dev_dbg(dev, "failed to lookup TCSR regmap\n");
1020         qphy->tcsr = NULL;
1021     }
1022 
1023     qphy->cell = devm_nvmem_cell_get(dev, NULL);
1024     if (IS_ERR(qphy->cell)) {
1025         if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
1026             return -EPROBE_DEFER;
1027         qphy->cell = NULL;
1028         dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
1029     }
1030 
1031     if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
1032                   &value)) {
1033         or->imp_res_offset.value = (u8)value;
1034         or->imp_res_offset.override = true;
1035     }
1036 
1037     if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
1038                   &value)) {
1039         or->bias_ctrl.value = (u8)value;
1040         or->bias_ctrl.override = true;
1041     }
1042 
1043     if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
1044                   &value)) {
1045         or->charge_ctrl.value = (u8)value;
1046         or->charge_ctrl.override = true;
1047     }
1048 
1049     if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
1050                   &value)) {
1051         or->hstx_trim.value = (u8)value;
1052         or->hstx_trim.override = true;
1053     }
1054 
1055     if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
1056                      &value)) {
1057         or->preemphasis.value = (u8)value;
1058         or->preemphasis.override = true;
1059     }
1060 
1061     if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
1062                      &value)) {
1063         or->preemphasis_width.value = (u8)value;
1064         or->preemphasis_width.override = true;
1065     }
1066 
1067     if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
1068                   &value)) {
1069         or->hsdisc_trim.value = (u8)value;
1070         or->hsdisc_trim.override = true;
1071     }
1072 
1073     pm_runtime_set_active(dev);
1074     pm_runtime_enable(dev);
1075     /*
1076      * Prevent runtime pm from being ON by default. Users can enable
1077      * it using power/control in sysfs.
1078      */
1079     pm_runtime_forbid(dev);
1080 
1081     generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
1082     if (IS_ERR(generic_phy)) {
1083         ret = PTR_ERR(generic_phy);
1084         dev_err(dev, "failed to create phy, %d\n", ret);
1085         pm_runtime_disable(dev);
1086         return ret;
1087     }
1088     qphy->phy = generic_phy;
1089 
1090     dev_set_drvdata(dev, qphy);
1091     phy_set_drvdata(generic_phy, qphy);
1092 
1093     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1094     if (!IS_ERR(phy_provider))
1095         dev_info(dev, "Registered Qcom-QUSB2 phy\n");
1096     else
1097         pm_runtime_disable(dev);
1098 
1099     return PTR_ERR_OR_ZERO(phy_provider);
1100 }
1101 
1102 static struct platform_driver qusb2_phy_driver = {
1103     .probe      = qusb2_phy_probe,
1104     .driver = {
1105         .name   = "qcom-qusb2-phy",
1106         .pm = &qusb2_phy_pm_ops,
1107         .of_match_table = qusb2_phy_of_match_table,
1108     },
1109 };
1110 
1111 module_platform_driver(qusb2_phy_driver);
1112 
1113 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1114 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
1115 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!