phy/qualcomm/phy-qcom-qmp.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef QCOM_PHY_QMP_H_
0007 #define QCOM_PHY_QMP_H_
0008
0009 #include "phy-qcom-qmp-qserdes-com.h"
0010 #include "phy-qcom-qmp-qserdes-txrx.h"
0011
0012 #include "phy-qcom-qmp-qserdes-com-v3.h"
0013 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
0014
0015 #include "phy-qcom-qmp-qserdes-com-v4.h"
0016 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
0017 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
0018
0019 #include "phy-qcom-qmp-qserdes-com-v5.h"
0020 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
0021 #include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
0022
0023 #include "phy-qcom-qmp-qserdes-pll.h"
0024
0025 #include "phy-qcom-qmp-pcs-v2.h"
0026
0027 #include "phy-qcom-qmp-pcs-v3.h"
0028 #include "phy-qcom-qmp-pcs-misc-v3.h"
0029 #include "phy-qcom-qmp-pcs-ufs-v3.h"
0030
0031 #include "phy-qcom-qmp-pcs-v4.h"
0032 #include "phy-qcom-qmp-pcs-pcie-v4.h"
0033 #include "phy-qcom-qmp-pcs-usb-v4.h"
0034 #include "phy-qcom-qmp-pcs-ufs-v4.h"
0035
0036 #include "phy-qcom-qmp-pcs-v4_20.h"
0037 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
0038
0039 #include "phy-qcom-qmp-pcs-v5.h"
0040 #include "phy-qcom-qmp-pcs-pcie-v5.h"
0041 #include "phy-qcom-qmp-pcs-usb-v5.h"
0042 #include "phy-qcom-qmp-pcs-ufs-v5.h"
0043
0044 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
0045
0046 #include "phy-qcom-qmp-pcie-qhp.h"
0047
0048 /* Only for QMP V3 & V4 PHY - DP COM registers */
0049 #define QPHY_V3_DP_COM_PHY_MODE_CTRL            0x00
0050 #define QPHY_V3_DP_COM_SW_RESET             0x04
0051 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL          0x08
0052 #define QPHY_V3_DP_COM_SWI_CTRL             0x0c
0053 #define QPHY_V3_DP_COM_TYPEC_CTRL           0x10
0054 #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL         0x14
0055 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL          0x1c
0056
0057 /* QSERDES V3 COM bits */
0058 # define QSERDES_V3_COM_BIAS_EN             0x0001
0059 # define QSERDES_V3_COM_BIAS_EN_MUX         0x0002
0060 # define QSERDES_V3_COM_CLKBUF_R_EN         0x0004
0061 # define QSERDES_V3_COM_CLKBUF_L_EN         0x0008
0062 # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL        0x0010
0063 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L       0x0020
0064 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R       0x0040
0065
0066 /* QSERDES V3 TX bits */
0067 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK       0x001f
0068 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN     0x0020
0069 # define DP_PHY_TXn_TX_DRV_LVL_MASK         0x001f
0070 # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN           0x0020
0071
0072 /* QMP PHY - DP PHY registers */
0073 #define QSERDES_DP_PHY_REVISION_ID0         0x000
0074 #define QSERDES_DP_PHY_REVISION_ID1         0x004
0075 #define QSERDES_DP_PHY_REVISION_ID2         0x008
0076 #define QSERDES_DP_PHY_REVISION_ID3         0x00c
0077 #define QSERDES_DP_PHY_CFG              0x010
0078 #define QSERDES_DP_PHY_PD_CTL               0x018
0079 # define DP_PHY_PD_CTL_PWRDN                0x001
0080 # define DP_PHY_PD_CTL_PSR_PWRDN            0x002
0081 # define DP_PHY_PD_CTL_AUX_PWRDN            0x004
0082 # define DP_PHY_PD_CTL_LANE_0_1_PWRDN           0x008
0083 # define DP_PHY_PD_CTL_LANE_2_3_PWRDN           0x010
0084 # define DP_PHY_PD_CTL_PLL_PWRDN            0x020
0085 # define DP_PHY_PD_CTL_DP_CLAMP_EN          0x040
0086 #define QSERDES_DP_PHY_MODE             0x01c
0087 #define QSERDES_DP_PHY_AUX_CFG0             0x020
0088 #define QSERDES_DP_PHY_AUX_CFG1             0x024
0089 #define QSERDES_DP_PHY_AUX_CFG2             0x028
0090 #define QSERDES_DP_PHY_AUX_CFG3             0x02c
0091 #define QSERDES_DP_PHY_AUX_CFG4             0x030
0092 #define QSERDES_DP_PHY_AUX_CFG5             0x034
0093 #define QSERDES_DP_PHY_AUX_CFG6             0x038
0094 #define QSERDES_DP_PHY_AUX_CFG7             0x03c
0095 #define QSERDES_DP_PHY_AUX_CFG8             0x040
0096 #define QSERDES_DP_PHY_AUX_CFG9             0x044
0097
0098 /* Only for QMP V3 PHY - DP PHY registers */
0099 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK        0x048
0100 # define PHY_AUX_STOP_ERR_MASK              0x01
0101 # define PHY_AUX_DEC_ERR_MASK               0x02
0102 # define PHY_AUX_SYNC_ERR_MASK              0x04
0103 # define PHY_AUX_ALIGN_ERR_MASK             0x08
0104 # define PHY_AUX_REQ_ERR_MASK               0x10
0105
0106 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR       0x04c
0107 #define QSERDES_V3_DP_PHY_AUX_BIST_CFG          0x050
0108
0109 #define QSERDES_V3_DP_PHY_VCO_DIV           0x064
0110 #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL      0x06c
0111 #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL      0x088
0112
0113 #define QSERDES_V3_DP_PHY_SPARE0            0x0ac
0114 #define DP_PHY_SPARE0_MASK              0x0f
0115 #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT        0x04(0x0004)
0116
0117 #define QSERDES_V3_DP_PHY_STATUS            0x0c0
0118
0119 /* Only for QMP V4 PHY - DP PHY registers */
0120 #define QSERDES_V4_DP_PHY_CFG_1             0x014
0121 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK        0x054
0122 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR       0x058
0123 #define QSERDES_V4_DP_PHY_VCO_DIV           0x070
0124 #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL      0x078
0125 #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL      0x09c
0126 #define QSERDES_V4_DP_PHY_SPARE0            0x0c8
0127 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS      0x0d8
0128 #define QSERDES_V4_DP_PHY_STATUS            0x0dc
0129
0130 /* Only for QMP V4 PHY - PCS_MISC registers */
0131 #define QPHY_V4_PCS_MISC_TYPEC_CTRL         0x00
0132 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL       0x04
0133 #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1       0x08
0134 #define QPHY_V4_PCS_MISC_CLAMP_ENABLE           0x0c
0135 #define QPHY_V4_PCS_MISC_TYPEC_STATUS           0x10
0136 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS     0x14
0137
0138 #endif