phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
0007 #define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
0008
0009 /* Only for QMP V5_20 PHY - TX registers */
0010 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX    0x30
0011 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX    0x34
0012 #define QSERDES_V5_20_TX_LANE_MODE_1            0x78
0013 #define QSERDES_V5_20_TX_LANE_MODE_2            0x7c
0014
0015 /* Only for QMP V5_20 PHY - RX registers */
0016 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2     0x008
0017 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3     0x00c
0018 #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS       0x020
0019 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1   0x02c
0020 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3   0x030
0021 #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET       0x07c
0022 #define QSERDES_V5_20_RX_DFE_3              0x090
0023 #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1        0x0b4
0024 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1      0x0c4
0025 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2      0x0c8
0026 #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL        0x0dc
0027 #define QSERDES_V5_20_RX_GM_CAL             0x0ec
0028 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4      0x108
0029 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1        0x164
0030 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2        0x168
0031 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3        0x16c
0032 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5        0x174
0033 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6        0x178
0034 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0       0x17c
0035 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1       0x180
0036 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2       0x184
0037 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3       0x188
0038 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4       0x18c
0039 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5       0x190
0040 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6       0x194
0041 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0       0x198
0042 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1       0x19c
0043 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2       0x1a0
0044 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3       0x1a4
0045 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4       0x1a8
0046 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5       0x1ac
0047 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6       0x1b0
0048 #define QSERDES_V5_20_RX_PHPRE_CTRL         0x1b4
0049 #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET   0x1c0
0050 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
0051 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3   0x1f8
0052 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
0053 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3   0x200
0054 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
0055 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3   0x208
0056 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3   0x210
0057 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3   0x218
0058 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3   0x220
0059
0060 #endif