phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_
0007 #define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_
0008
0009 /* Only for QMP V3 PHY - TX registers */
0010 #define QSERDES_V3_TX_BIST_MODE_LANENO          0x000
0011 #define QSERDES_V3_TX_CLKBUF_ENABLE         0x008
0012 #define QSERDES_V3_TX_TX_EMP_POST1_LVL          0x00c
0013 #define QSERDES_V3_TX_TX_DRV_LVL            0x01c
0014 #define QSERDES_V3_TX_RESET_TSYNC_EN            0x024
0015 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN        0x028
0016 #define QSERDES_V3_TX_TX_BAND               0x02c
0017 #define QSERDES_V3_TX_SLEW_CNTL             0x030
0018 #define QSERDES_V3_TX_INTERFACE_SELECT          0x034
0019 #define QSERDES_V3_TX_RES_CODE_LANE_TX          0x03c
0020 #define QSERDES_V3_TX_RES_CODE_LANE_RX          0x040
0021 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX       0x044
0022 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX       0x048
0023 #define QSERDES_V3_TX_DEBUG_BUS_SEL         0x058
0024 #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN       0x05c
0025 #define QSERDES_V3_TX_HIGHZ_DRVR_EN         0x060
0026 #define QSERDES_V3_TX_TX_POL_INV            0x064
0027 #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN    0x068
0028 #define QSERDES_V3_TX_LANE_MODE_1           0x08c
0029 #define QSERDES_V3_TX_LANE_MODE_2           0x090
0030 #define QSERDES_V3_TX_LANE_MODE_3           0x094
0031 #define QSERDES_V3_TX_RCV_DETECT_LVL_2          0x0a4
0032 #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN          0x0c0
0033 #define QSERDES_V3_TX_TX_INTERFACE_MODE         0x0c4
0034 #define QSERDES_V3_TX_VMODE_CTRL1           0x0f0
0035
0036 /* Only for QMP V3 PHY - RX registers */
0037 #define QSERDES_V3_RX_UCDR_FO_GAIN          0x008
0038 #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF         0x00c
0039 #define QSERDES_V3_RX_UCDR_SO_GAIN          0x014
0040 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF     0x024
0041 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER      0x028
0042 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN          0x02c
0043 #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN     0x030
0044 #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
0045 #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW       0x03c
0046 #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH      0x040
0047 #define QSERDES_V3_RX_UCDR_PI_CONTROLS          0x044
0048 #define QSERDES_V3_RX_RX_TERM_BW            0x07c
0049 #define QSERDES_V3_RX_VGA_CAL_CNTRL1            0x0bc
0050 #define QSERDES_V3_RX_VGA_CAL_CNTRL2            0x0c0
0051 #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB           0x0c8
0052 #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB           0x0cc
0053 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1     0x0d0
0054 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2     0x0d4
0055 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3     0x0d8
0056 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4     0x0dc
0057 #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1   0x0f8
0058 #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2      0x0fc
0059 #define QSERDES_V3_RX_SIGDET_ENABLES            0x100
0060 #define QSERDES_V3_RX_SIGDET_CNTRL          0x104
0061 #define QSERDES_V3_RX_SIGDET_LVL            0x108
0062 #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL     0x10c
0063 #define QSERDES_V3_RX_RX_BAND               0x110
0064 #define QSERDES_V3_RX_RX_INTERFACE_MODE         0x11c
0065 #define QSERDES_V3_RX_RX_MODE_00            0x164
0066 #define QSERDES_V3_RX_RX_MODE_01            0x168
0067
0068 #endif