phy/qualcomm/phy-qcom-qmp-qserdes-pll.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef QCOM_PHY_QMP_QSERDES_PLL_H_
0007 #define QCOM_PHY_QMP_QSERDES_PLL_H_
0008
0009 /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
0010 #define QSERDES_PLL_BG_TIMER                0x00c
0011 #define QSERDES_PLL_SSC_PER1                0x01c
0012 #define QSERDES_PLL_SSC_PER2                0x020
0013 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0        0x024
0014 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0        0x028
0015 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1        0x02c
0016 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1        0x030
0017 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN         0x03c
0018 #define QSERDES_PLL_CLK_ENABLE1             0x040
0019 #define QSERDES_PLL_SYS_CLK_CTRL            0x044
0020 #define QSERDES_PLL_SYSCLK_BUF_ENABLE           0x048
0021 #define QSERDES_PLL_PLL_IVCO                0x050
0022 #define QSERDES_PLL_LOCK_CMP1_MODE0         0x054
0023 #define QSERDES_PLL_LOCK_CMP2_MODE0         0x058
0024 #define QSERDES_PLL_LOCK_CMP1_MODE1         0x060
0025 #define QSERDES_PLL_LOCK_CMP2_MODE1         0x064
0026 #define QSERDES_PLL_BG_TRIM             0x074
0027 #define QSERDES_PLL_CLK_EP_DIV_MODE0            0x078
0028 #define QSERDES_PLL_CLK_EP_DIV_MODE1            0x07c
0029 #define QSERDES_PLL_CP_CTRL_MODE0           0x080
0030 #define QSERDES_PLL_CP_CTRL_MODE1           0x084
0031 #define QSERDES_PLL_PLL_RCTRL_MODE0         0x088
0032 #define QSERDES_PLL_PLL_RCTRL_MODE1         0x08c
0033 #define QSERDES_PLL_PLL_CCTRL_MODE0         0x090
0034 #define QSERDES_PLL_PLL_CCTRL_MODE1         0x094
0035 #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM         0x0a4
0036 #define QSERDES_PLL_SYSCLK_EN_SEL           0x0a8
0037 #define QSERDES_PLL_RESETSM_CNTRL           0x0b0
0038 #define QSERDES_PLL_LOCK_CMP_EN             0x0c4
0039 #define QSERDES_PLL_DEC_START_MODE0         0x0cc
0040 #define QSERDES_PLL_DEC_START_MODE1         0x0d0
0041 #define QSERDES_PLL_DIV_FRAC_START1_MODE0       0x0d8
0042 #define QSERDES_PLL_DIV_FRAC_START2_MODE0       0x0dc
0043 #define QSERDES_PLL_DIV_FRAC_START3_MODE0       0x0e0
0044 #define QSERDES_PLL_DIV_FRAC_START1_MODE1       0x0e4
0045 #define QSERDES_PLL_DIV_FRAC_START2_MODE1       0x0e8
0046 #define QSERDES_PLL_DIV_FRAC_START3_MODE1       0x0ec
0047 #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0       0x100
0048 #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0       0x104
0049 #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1       0x108
0050 #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1       0x10c
0051 #define QSERDES_PLL_VCO_TUNE_MAP            0x120
0052 #define QSERDES_PLL_VCO_TUNE1_MODE0         0x124
0053 #define QSERDES_PLL_VCO_TUNE2_MODE0         0x128
0054 #define QSERDES_PLL_VCO_TUNE1_MODE1         0x12c
0055 #define QSERDES_PLL_VCO_TUNE2_MODE1         0x130
0056 #define QSERDES_PLL_VCO_TUNE_TIMER1         0x13c
0057 #define QSERDES_PLL_VCO_TUNE_TIMER2         0x140
0058 #define QSERDES_PLL_CLK_SELECT              0x16c
0059 #define QSERDES_PLL_HSCLK_SEL               0x170
0060 #define QSERDES_PLL_CORECLK_DIV             0x17c
0061 #define QSERDES_PLL_CORE_CLK_EN             0x184
0062 #define QSERDES_PLL_CMN_CONFIG              0x18c
0063 #define QSERDES_PLL_SVS_MODE_CLK_SEL            0x194
0064 #define QSERDES_PLL_CORECLK_DIV_MODE1           0x1b4
0065
0066 #endif