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0006 #ifndef QCOM_PHY_QMP_PCS_V4_H_
0007 #define QCOM_PHY_QMP_PCS_V4_H_
0008
0009
0010 #define QPHY_V4_PCS_SW_RESET 0x000
0011 #define QPHY_V4_PCS_REVISION_ID0 0x004
0012 #define QPHY_V4_PCS_REVISION_ID1 0x008
0013 #define QPHY_V4_PCS_REVISION_ID2 0x00c
0014 #define QPHY_V4_PCS_REVISION_ID3 0x010
0015 #define QPHY_V4_PCS_PCS_STATUS1 0x014
0016 #define QPHY_V4_PCS_PCS_STATUS2 0x018
0017 #define QPHY_V4_PCS_PCS_STATUS3 0x01c
0018 #define QPHY_V4_PCS_PCS_STATUS4 0x020
0019 #define QPHY_V4_PCS_PCS_STATUS5 0x024
0020 #define QPHY_V4_PCS_PCS_STATUS6 0x028
0021 #define QPHY_V4_PCS_PCS_STATUS7 0x02c
0022 #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030
0023 #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034
0024 #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038
0025 #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c
0026 #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040
0027 #define QPHY_V4_PCS_START_CONTROL 0x044
0028 #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048
0029 #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c
0030 #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050
0031 #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054
0032 #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058
0033 #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c
0034 #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060
0035 #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064
0036 #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068
0037 #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c
0038 #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070
0039 #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074
0040 #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078
0041 #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c
0042 #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080
0043 #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084
0044 #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088
0045 #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c
0046 #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090
0047 #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094
0048 #define QPHY_V4_PCS_FLL_CNTRL1 0x098
0049 #define QPHY_V4_PCS_FLL_CNTRL2 0x09c
0050 #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0
0051 #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4
0052 #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8
0053 #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac
0054 #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0
0055 #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4
0056 #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8
0057 #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc
0058 #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0
0059 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4
0060 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8
0061 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc
0062 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0
0063 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4
0064 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8
0065 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc
0066 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0
0067 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4
0068 #define QPHY_V4_PCS_BIST_CTRL 0x0e8
0069 #define QPHY_V4_PCS_PRBS_POLY0 0x0ec
0070 #define QPHY_V4_PCS_PRBS_POLY1 0x0f0
0071 #define QPHY_V4_PCS_FIXED_PAT0 0x0f4
0072 #define QPHY_V4_PCS_FIXED_PAT1 0x0f8
0073 #define QPHY_V4_PCS_FIXED_PAT2 0x0fc
0074 #define QPHY_V4_PCS_FIXED_PAT3 0x100
0075 #define QPHY_V4_PCS_FIXED_PAT4 0x104
0076 #define QPHY_V4_PCS_FIXED_PAT5 0x108
0077 #define QPHY_V4_PCS_FIXED_PAT6 0x10c
0078 #define QPHY_V4_PCS_FIXED_PAT7 0x110
0079 #define QPHY_V4_PCS_FIXED_PAT8 0x114
0080 #define QPHY_V4_PCS_FIXED_PAT9 0x118
0081 #define QPHY_V4_PCS_FIXED_PAT10 0x11c
0082 #define QPHY_V4_PCS_FIXED_PAT11 0x120
0083 #define QPHY_V4_PCS_FIXED_PAT12 0x124
0084 #define QPHY_V4_PCS_FIXED_PAT13 0x128
0085 #define QPHY_V4_PCS_FIXED_PAT14 0x12c
0086 #define QPHY_V4_PCS_FIXED_PAT15 0x130
0087 #define QPHY_V4_PCS_TXMGN_CONFIG 0x134
0088 #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138
0089 #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c
0090 #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140
0091 #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144
0092 #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148
0093 #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c
0094 #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150
0095 #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154
0096 #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158
0097 #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c
0098 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160
0099 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164
0100 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168
0101 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
0102 #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170
0103 #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174
0104 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178
0105 #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c
0106 #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180
0107 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
0108 #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188
0109 #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
0110 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
0111 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
0112 #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198
0113 #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c
0114 #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
0115 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
0116 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
0117 #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac
0118 #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0
0119 #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4
0120 #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8
0121 #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc
0122 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
0123 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
0124 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8
0125 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc
0126 #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0
0127 #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
0128 #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8
0129 #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc
0130 #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0
0131 #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
0132 #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
0133 #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
0134
0135 #endif
