phy/qualcomm/phy-qcom-qmp-pcs-v2.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef QCOM_PHY_QMP_PCS_V2_H_
0007 #define QCOM_PHY_QMP_PCS_V2_H_
0008
0009 /* Only for QMP V2 PHY - PCS registers */
0010 #define QPHY_V2_PCS_POWER_DOWN_CONTROL          0x004
0011 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0            0x024
0012 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0          0x028
0013 #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL        0x034
0014 #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL       0x038
0015 #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL        0x03c
0016 #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL       0x040
0017 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE       0x054
0018 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL          0x058
0019 #define QPHY_V2_PCS_POWER_STATE_CONFIG1         0x060
0020 #define QPHY_V2_PCS_POWER_STATE_CONFIG2         0x064
0021 #define QPHY_V2_PCS_POWER_STATE_CONFIG4         0x06c
0022 #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1         0x080
0023 #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2         0x084
0024 #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3         0x088
0025 #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK     0x0a0
0026 #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK       0x0a4
0027 #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME       0x0a8
0028 #define QPHY_V2_PCS_FLL_CNTRL1              0x0c0
0029 #define QPHY_V2_PCS_FLL_CNTRL2              0x0c4
0030 #define QPHY_V2_PCS_FLL_CNT_VAL_L           0x0c8
0031 #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL           0x0cc
0032 #define QPHY_V2_PCS_FLL_MAN_CODE            0x0d0
0033
0034 /* UFS only ? */
0035 #define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP  0x0cc
0036 #define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL          0x13c
0037 #define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME         0x140
0038 #define QPHY_V2_PCS_RX_SIGDET_CTRL2         0x148
0039 #define QPHY_V2_PCS_RX_PWM_GEAR_BAND            0x154
0040 #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB    0x1a8
0041 #define QPHY_V2_PCS_OSC_DTCT_ACTIONS            0x1ac
0042 #define QPHY_V2_PCS_RX_SIGDET_LVL           0x1d8
0043 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
0044 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
0045
0046 #endif