phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h

0001 /* Only for QMP V5 PHY - UFS PCS registers */
0002 /* SPDX-License-Identifier: GPL-2.0 */
0003 /*
0004  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
0005  */
0006
0007 #ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_
0008 #define QCOM_PHY_QMP_PCS_UFS_V5_H_
0009
0010 /* Only for QMP V5 PHY - UFS PCS registers */
0011 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB    0x00c
0012 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB    0x010
0013 #define QPHY_V5_PCS_UFS_PLL_CNTL            0x02c
0014 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL        0x030
0015 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL        0x038
0016 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY        0x074
0017 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY        0x0b4
0018 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL        0x124
0019 #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME     0x150
0020 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1         0x154
0021 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2         0x158
0022 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND        0x160
0023 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND         0x168
0024 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1       0x1d8
0025 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1        0x1e0
0026
0027 #endif