phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef QCOM_PHY_QMP_PCS_UFS_V4_H_
0007 #define QCOM_PHY_QMP_PCS_UFS_V4_H_
0008
0009 /* Only for QMP V4 PHY - UFS PCS registers */
0010 #define QPHY_V4_PCS_UFS_PHY_START           0x000
0011 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL      0x004
0012 #define QPHY_V4_PCS_UFS_SW_RESET            0x008
0013 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB    0x00c
0014 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB    0x010
0015 #define QPHY_V4_PCS_UFS_PLL_CNTL            0x02c
0016 #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL        0x030
0017 #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL        0x038
0018 #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL     0x060
0019 #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY        0x074
0020 #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY        0x0b4
0021 #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL        0x124
0022 #define QPHY_V4_PCS_UFS_LINECFG_DISABLE         0x148
0023 #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME     0x150
0024 #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2         0x158
0025 #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND        0x160
0026 #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND         0x168
0027 #define QPHY_V4_PCS_UFS_READY_STATUS            0x180
0028 #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1       0x1d8
0029 #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1        0x1e0
0030
0031 #endif