0001
0002
0003
0004
0005
0006 #include <linux/clk.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/delay.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/of_address.h>
0017 #include <linux/phy/phy.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <linux/reset.h>
0021 #include <linux/slab.h>
0022
0023 #include <dt-bindings/phy/phy.h>
0024
0025 #include "phy-qcom-qmp.h"
0026
0027
0028 #define SW_RESET BIT(0)
0029
0030 #define SW_PWRDN BIT(0)
0031 #define REFCLK_DRV_DSBL BIT(1)
0032
0033 #define SERDES_START BIT(0)
0034 #define PCS_START BIT(1)
0035 #define PLL_READY_GATE_EN BIT(3)
0036
0037 #define PHYSTATUS BIT(6)
0038 #define PHYSTATUS_4_20 BIT(7)
0039
0040 #define PCS_READY BIT(0)
0041
0042
0043
0044 #define SW_DPPHY_RESET BIT(0)
0045
0046 #define SW_DPPHY_RESET_MUX BIT(1)
0047
0048 #define SW_USB3PHY_RESET BIT(2)
0049
0050 #define SW_USB3PHY_RESET_MUX BIT(3)
0051
0052
0053 #define USB3_MODE BIT(0)
0054 #define DP_MODE BIT(1)
0055
0056
0057 #define ARCVR_DTCT_EN BIT(0)
0058 #define ALFPS_DTCT_EN BIT(1)
0059 #define ARCVR_DTCT_EVENT_SEL BIT(4)
0060
0061
0062 #define IRQ_CLEAR BIT(0)
0063
0064
0065 #define RCVR_DETECT BIT(0)
0066
0067
0068 #define CLAMP_EN BIT(0)
0069
0070 #define PHY_INIT_COMPLETE_TIMEOUT 10000
0071 #define POWER_DOWN_DELAY_US_MIN 10
0072 #define POWER_DOWN_DELAY_US_MAX 11
0073
0074 #define MAX_PROP_NAME 32
0075
0076
0077 #define QMP_PHY_LEGACY_LANE_STRIDE 0x400
0078
0079 struct qmp_phy_init_tbl {
0080 unsigned int offset;
0081 unsigned int val;
0082
0083
0084
0085
0086 bool in_layout;
0087
0088
0089
0090
0091 u8 lane_mask;
0092 };
0093
0094 #define QMP_PHY_INIT_CFG(o, v) \
0095 { \
0096 .offset = o, \
0097 .val = v, \
0098 .lane_mask = 0xff, \
0099 }
0100
0101 #define QMP_PHY_INIT_CFG_L(o, v) \
0102 { \
0103 .offset = o, \
0104 .val = v, \
0105 .in_layout = true, \
0106 .lane_mask = 0xff, \
0107 }
0108
0109 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \
0110 { \
0111 .offset = o, \
0112 .val = v, \
0113 .lane_mask = l, \
0114 }
0115
0116
0117 enum qphy_reg_layout {
0118
0119 QPHY_COM_SW_RESET,
0120 QPHY_COM_POWER_DOWN_CONTROL,
0121 QPHY_COM_START_CONTROL,
0122 QPHY_COM_PCS_READY_STATUS,
0123
0124 QPHY_SW_RESET,
0125 QPHY_START_CTRL,
0126 QPHY_PCS_READY_STATUS,
0127 QPHY_PCS_STATUS,
0128 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
0129 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
0130 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
0131 QPHY_PCS_POWER_DOWN_CONTROL,
0132
0133 QPHY_PCS_MISC_TYPEC_CTRL,
0134
0135 QPHY_LAYOUT_SIZE
0136 };
0137
0138 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
0139 [QPHY_COM_SW_RESET] = 0x400,
0140 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
0141 [QPHY_COM_START_CONTROL] = 0x408,
0142 [QPHY_COM_PCS_READY_STATUS] = 0x448,
0143 [QPHY_SW_RESET] = 0x00,
0144 [QPHY_START_CTRL] = 0x08,
0145 [QPHY_PCS_STATUS] = 0x174,
0146 };
0147
0148 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
0149 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
0150 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
0151 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
0152 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
0153 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
0154 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
0155 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
0156 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
0157 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
0158 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
0159 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
0160 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
0161 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
0162 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
0163 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
0164 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
0165 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
0166 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
0167 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
0168 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
0169 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
0170 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
0171 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
0172 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
0173 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
0174 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
0175 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
0176 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
0177 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
0178 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
0179 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
0180 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
0181 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
0182 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
0183 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
0184 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
0185 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
0186 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
0187 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
0188 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
0189 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
0190 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
0191 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
0192 };
0193
0194 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
0195 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
0196 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
0197 };
0198
0199 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
0200 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
0201 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
0202 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
0203 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
0204 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
0205 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
0206 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
0207 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
0208 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
0209 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
0210 };
0211
0212 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
0213 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL, 0x4c),
0214 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
0215 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
0216
0217 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05),
0218
0219 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05),
0220 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02),
0221 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG4, 0x00),
0222 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG1, 0xa3),
0223 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
0224 };
0225
0226 struct qmp_phy;
0227
0228
0229 struct qmp_phy_cfg {
0230
0231 unsigned int type;
0232
0233 int nlanes;
0234
0235
0236 const struct qmp_phy_init_tbl *serdes_tbl;
0237 int serdes_tbl_num;
0238 const struct qmp_phy_init_tbl *serdes_tbl_sec;
0239 int serdes_tbl_num_sec;
0240 const struct qmp_phy_init_tbl *tx_tbl;
0241 int tx_tbl_num;
0242 const struct qmp_phy_init_tbl *tx_tbl_sec;
0243 int tx_tbl_num_sec;
0244 const struct qmp_phy_init_tbl *rx_tbl;
0245 int rx_tbl_num;
0246 const struct qmp_phy_init_tbl *rx_tbl_sec;
0247 int rx_tbl_num_sec;
0248 const struct qmp_phy_init_tbl *pcs_tbl;
0249 int pcs_tbl_num;
0250 const struct qmp_phy_init_tbl *pcs_tbl_sec;
0251 int pcs_tbl_num_sec;
0252 const struct qmp_phy_init_tbl *pcs_misc_tbl;
0253 int pcs_misc_tbl_num;
0254 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
0255 int pcs_misc_tbl_num_sec;
0256
0257
0258 const char * const *clk_list;
0259 int num_clks;
0260
0261 const char * const *reset_list;
0262 int num_resets;
0263
0264 const char * const *vreg_list;
0265 int num_vregs;
0266
0267
0268 const unsigned int *regs;
0269
0270 unsigned int start_ctrl;
0271 unsigned int pwrdn_ctrl;
0272 unsigned int mask_com_pcs_ready;
0273
0274 unsigned int phy_status;
0275
0276
0277 bool has_pwrdn_delay;
0278
0279 int pwrdn_delay_min;
0280 int pwrdn_delay_max;
0281 };
0282
0283
0284
0285
0286
0287
0288
0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299 struct qmp_phy {
0300 struct phy *phy;
0301 const struct qmp_phy_cfg *cfg;
0302 void __iomem *serdes;
0303 void __iomem *tx;
0304 void __iomem *rx;
0305 void __iomem *pcs;
0306 void __iomem *pcs_misc;
0307 struct clk *pipe_clk;
0308 unsigned int index;
0309 struct qcom_qmp *qmp;
0310 struct reset_control *lane_rst;
0311 enum phy_mode mode;
0312 };
0313
0314
0315
0316
0317
0318
0319
0320
0321
0322
0323
0324
0325
0326
0327 struct qcom_qmp {
0328 struct device *dev;
0329
0330 struct clk_bulk_data *clks;
0331 struct reset_control_bulk_data *resets;
0332 struct regulator_bulk_data *vregs;
0333
0334 struct qmp_phy **phys;
0335
0336 struct mutex phy_mutex;
0337 int init_count;
0338 };
0339
0340 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
0341 {
0342 u32 reg;
0343
0344 reg = readl(base + offset);
0345 reg |= val;
0346 writel(reg, base + offset);
0347
0348
0349 readl(base + offset);
0350 }
0351
0352 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
0353 {
0354 u32 reg;
0355
0356 reg = readl(base + offset);
0357 reg &= ~val;
0358 writel(reg, base + offset);
0359
0360
0361 readl(base + offset);
0362 }
0363
0364
0365 static const char * const msm8996_phy_clk_l[] = {
0366 "aux", "cfg_ahb", "ref",
0367 };
0368
0369
0370 static const char * const msm8996_pciephy_reset_l[] = {
0371 "phy", "common", "cfg",
0372 };
0373
0374
0375 static const char * const qmp_phy_vreg_l[] = {
0376 "vdda-phy", "vdda-pll",
0377 };
0378
0379 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
0380 .type = PHY_TYPE_PCIE,
0381 .nlanes = 3,
0382
0383 .serdes_tbl = msm8996_pcie_serdes_tbl,
0384 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
0385 .tx_tbl = msm8996_pcie_tx_tbl,
0386 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
0387 .rx_tbl = msm8996_pcie_rx_tbl,
0388 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
0389 .pcs_tbl = msm8996_pcie_pcs_tbl,
0390 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
0391 .clk_list = msm8996_phy_clk_l,
0392 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
0393 .reset_list = msm8996_pciephy_reset_l,
0394 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
0395 .vreg_list = qmp_phy_vreg_l,
0396 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
0397 .regs = pciephy_regs_layout,
0398
0399 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
0400 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
0401 .mask_com_pcs_ready = PCS_READY,
0402 .phy_status = PHYSTATUS,
0403
0404 .has_pwrdn_delay = true,
0405 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
0406 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
0407 };
0408
0409 static void qcom_qmp_phy_pcie_msm8996_configure_lane(void __iomem *base,
0410 const unsigned int *regs,
0411 const struct qmp_phy_init_tbl tbl[],
0412 int num,
0413 u8 lane_mask)
0414 {
0415 int i;
0416 const struct qmp_phy_init_tbl *t = tbl;
0417
0418 if (!t)
0419 return;
0420
0421 for (i = 0; i < num; i++, t++) {
0422 if (!(t->lane_mask & lane_mask))
0423 continue;
0424
0425 if (t->in_layout)
0426 writel(t->val, base + regs[t->offset]);
0427 else
0428 writel(t->val, base + t->offset);
0429 }
0430 }
0431
0432 static void qcom_qmp_phy_pcie_msm8996_configure(void __iomem *base,
0433 const unsigned int *regs,
0434 const struct qmp_phy_init_tbl tbl[],
0435 int num)
0436 {
0437 qcom_qmp_phy_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff);
0438 }
0439
0440 static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
0441 {
0442 struct qcom_qmp *qmp = qphy->qmp;
0443 const struct qmp_phy_cfg *cfg = qphy->cfg;
0444 void __iomem *serdes = qphy->serdes;
0445 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
0446 int serdes_tbl_num = cfg->serdes_tbl_num;
0447 void __iomem *status;
0448 unsigned int mask, val;
0449 int ret;
0450
0451 qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
0452 if (cfg->serdes_tbl_sec)
0453 qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
0454 cfg->serdes_tbl_num_sec);
0455
0456
0457 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
0458 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
0459 SERDES_START | PCS_START);
0460
0461 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
0462 mask = cfg->mask_com_pcs_ready;
0463
0464 ret = readl_poll_timeout(status, val, (val & mask), 10,
0465 PHY_INIT_COMPLETE_TIMEOUT);
0466 if (ret) {
0467 dev_err(qmp->dev,
0468 "phy common block init timed-out\n");
0469 return ret;
0470 }
0471
0472 return 0;
0473 }
0474
0475 static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
0476 {
0477 struct qcom_qmp *qmp = qphy->qmp;
0478 const struct qmp_phy_cfg *cfg = qphy->cfg;
0479 void __iomem *serdes = qphy->serdes;
0480 int ret;
0481
0482 mutex_lock(&qmp->phy_mutex);
0483 if (qmp->init_count++) {
0484 mutex_unlock(&qmp->phy_mutex);
0485 return 0;
0486 }
0487
0488
0489 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
0490 if (ret) {
0491 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
0492 goto err_unlock;
0493 }
0494
0495 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
0496 if (ret) {
0497 dev_err(qmp->dev, "reset assert failed\n");
0498 goto err_disable_regulators;
0499 }
0500
0501 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
0502 if (ret) {
0503 dev_err(qmp->dev, "reset deassert failed\n");
0504 goto err_disable_regulators;
0505 }
0506
0507 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
0508 if (ret)
0509 goto err_assert_reset;
0510
0511 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
0512 SW_PWRDN);
0513
0514 mutex_unlock(&qmp->phy_mutex);
0515
0516 return 0;
0517
0518 err_assert_reset:
0519 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
0520 err_disable_regulators:
0521 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
0522 err_unlock:
0523 mutex_unlock(&qmp->phy_mutex);
0524
0525 return ret;
0526 }
0527
0528 static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy)
0529 {
0530 struct qcom_qmp *qmp = qphy->qmp;
0531 const struct qmp_phy_cfg *cfg = qphy->cfg;
0532 void __iomem *serdes = qphy->serdes;
0533
0534 mutex_lock(&qmp->phy_mutex);
0535 if (--qmp->init_count) {
0536 mutex_unlock(&qmp->phy_mutex);
0537 return 0;
0538 }
0539
0540 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
0541 SERDES_START | PCS_START);
0542 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
0543 SW_RESET);
0544 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
0545 SW_PWRDN);
0546
0547 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
0548
0549 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
0550
0551 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
0552
0553 mutex_unlock(&qmp->phy_mutex);
0554
0555 return 0;
0556 }
0557
0558 static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
0559 {
0560 struct qmp_phy *qphy = phy_get_drvdata(phy);
0561 struct qcom_qmp *qmp = qphy->qmp;
0562 int ret;
0563 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
0564
0565 ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy);
0566 if (ret)
0567 return ret;
0568
0569 return 0;
0570 }
0571
0572 static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
0573 {
0574 struct qmp_phy *qphy = phy_get_drvdata(phy);
0575 struct qcom_qmp *qmp = qphy->qmp;
0576 const struct qmp_phy_cfg *cfg = qphy->cfg;
0577 void __iomem *tx = qphy->tx;
0578 void __iomem *rx = qphy->rx;
0579 void __iomem *pcs = qphy->pcs;
0580 void __iomem *pcs_misc = qphy->pcs_misc;
0581 void __iomem *status;
0582 unsigned int mask, val, ready;
0583 int ret;
0584
0585 qcom_qmp_phy_pcie_msm8996_serdes_init(qphy);
0586
0587 ret = reset_control_deassert(qphy->lane_rst);
0588 if (ret) {
0589 dev_err(qmp->dev, "lane%d reset deassert failed\n",
0590 qphy->index);
0591 return ret;
0592 }
0593
0594 ret = clk_prepare_enable(qphy->pipe_clk);
0595 if (ret) {
0596 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
0597 goto err_reset_lane;
0598 }
0599
0600
0601 qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs,
0602 cfg->tx_tbl, cfg->tx_tbl_num, 1);
0603 if (cfg->tx_tbl_sec)
0604 qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
0605 cfg->tx_tbl_num_sec, 1);
0606
0607 qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
0608 cfg->rx_tbl, cfg->rx_tbl_num, 1);
0609 if (cfg->rx_tbl_sec)
0610 qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
0611 cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
0612
0613 qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
0614 if (cfg->pcs_tbl_sec)
0615 qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
0616 cfg->pcs_tbl_num_sec);
0617
0618 qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
0619 cfg->pcs_misc_tbl_num);
0620 if (cfg->pcs_misc_tbl_sec)
0621 qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
0622 cfg->pcs_misc_tbl_num_sec);
0623
0624
0625
0626
0627
0628 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
0629
0630 if (cfg->has_pwrdn_delay)
0631 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
0632
0633
0634 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
0635
0636
0637 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
0638
0639 status = pcs + cfg->regs[QPHY_PCS_STATUS];
0640 mask = cfg->phy_status;
0641 ready = 0;
0642
0643 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
0644 PHY_INIT_COMPLETE_TIMEOUT);
0645 if (ret) {
0646 dev_err(qmp->dev, "phy initialization timed-out\n");
0647 goto err_disable_pipe_clk;
0648 }
0649
0650 return 0;
0651
0652 err_disable_pipe_clk:
0653 clk_disable_unprepare(qphy->pipe_clk);
0654 err_reset_lane:
0655 reset_control_assert(qphy->lane_rst);
0656
0657 return ret;
0658 }
0659
0660 static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
0661 {
0662 struct qmp_phy *qphy = phy_get_drvdata(phy);
0663 const struct qmp_phy_cfg *cfg = qphy->cfg;
0664
0665 clk_disable_unprepare(qphy->pipe_clk);
0666
0667
0668 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
0669
0670
0671 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
0672
0673
0674 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
0675 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
0676 cfg->pwrdn_ctrl);
0677 } else {
0678 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
0679 cfg->pwrdn_ctrl);
0680 }
0681
0682 return 0;
0683 }
0684
0685 static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy)
0686 {
0687 struct qmp_phy *qphy = phy_get_drvdata(phy);
0688
0689 reset_control_assert(qphy->lane_rst);
0690
0691 qcom_qmp_phy_pcie_msm8996_com_exit(qphy);
0692
0693 return 0;
0694 }
0695
0696 static int qcom_qmp_phy_pcie_msm8996_enable(struct phy *phy)
0697 {
0698 int ret;
0699
0700 ret = qcom_qmp_phy_pcie_msm8996_init(phy);
0701 if (ret)
0702 return ret;
0703
0704 ret = qcom_qmp_phy_pcie_msm8996_power_on(phy);
0705 if (ret)
0706 qcom_qmp_phy_pcie_msm8996_exit(phy);
0707
0708 return ret;
0709 }
0710
0711 static int qcom_qmp_phy_pcie_msm8996_disable(struct phy *phy)
0712 {
0713 int ret;
0714
0715 ret = qcom_qmp_phy_pcie_msm8996_power_off(phy);
0716 if (ret)
0717 return ret;
0718 return qcom_qmp_phy_pcie_msm8996_exit(phy);
0719 }
0720
0721 static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy,
0722 enum phy_mode mode, int submode)
0723 {
0724 struct qmp_phy *qphy = phy_get_drvdata(phy);
0725
0726 qphy->mode = mode;
0727
0728 return 0;
0729 }
0730
0731 static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
0732 {
0733 struct qcom_qmp *qmp = dev_get_drvdata(dev);
0734 int num = cfg->num_vregs;
0735 int i;
0736
0737 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
0738 if (!qmp->vregs)
0739 return -ENOMEM;
0740
0741 for (i = 0; i < num; i++)
0742 qmp->vregs[i].supply = cfg->vreg_list[i];
0743
0744 return devm_regulator_bulk_get(dev, num, qmp->vregs);
0745 }
0746
0747 static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
0748 {
0749 struct qcom_qmp *qmp = dev_get_drvdata(dev);
0750 int i;
0751 int ret;
0752
0753 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
0754 sizeof(*qmp->resets), GFP_KERNEL);
0755 if (!qmp->resets)
0756 return -ENOMEM;
0757
0758 for (i = 0; i < cfg->num_resets; i++)
0759 qmp->resets[i].id = cfg->reset_list[i];
0760
0761 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
0762 if (ret)
0763 return dev_err_probe(dev, ret, "failed to get resets\n");
0764
0765 return 0;
0766 }
0767
0768 static int qcom_qmp_phy_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
0769 {
0770 struct qcom_qmp *qmp = dev_get_drvdata(dev);
0771 int num = cfg->num_clks;
0772 int i;
0773
0774 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
0775 if (!qmp->clks)
0776 return -ENOMEM;
0777
0778 for (i = 0; i < num; i++)
0779 qmp->clks[i].id = cfg->clk_list[i];
0780
0781 return devm_clk_bulk_get(dev, num, qmp->clks);
0782 }
0783
0784 static void phy_clk_release_provider(void *res)
0785 {
0786 of_clk_del_provider(res);
0787 }
0788
0789
0790
0791
0792
0793
0794
0795
0796
0797
0798
0799
0800
0801
0802
0803
0804
0805
0806
0807 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
0808 {
0809 struct clk_fixed_rate *fixed;
0810 struct clk_init_data init = { };
0811 int ret;
0812
0813 ret = of_property_read_string(np, "clock-output-names", &init.name);
0814 if (ret) {
0815 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
0816 return ret;
0817 }
0818
0819 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
0820 if (!fixed)
0821 return -ENOMEM;
0822
0823 init.ops = &clk_fixed_rate_ops;
0824
0825
0826 fixed->fixed_rate = 125000000;
0827 fixed->hw.init = &init;
0828
0829 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
0830 if (ret)
0831 return ret;
0832
0833 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
0834 if (ret)
0835 return ret;
0836
0837
0838
0839
0840
0841 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
0842 }
0843
0844 static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = {
0845 .power_on = qcom_qmp_phy_pcie_msm8996_enable,
0846 .power_off = qcom_qmp_phy_pcie_msm8996_disable,
0847 .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
0848 .owner = THIS_MODULE,
0849 };
0850
0851 static void qcom_qmp_reset_control_put(void *data)
0852 {
0853 reset_control_put(data);
0854 }
0855
0856 static
0857 int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, int id,
0858 void __iomem *serdes, const struct qmp_phy_cfg *cfg)
0859 {
0860 struct qcom_qmp *qmp = dev_get_drvdata(dev);
0861 struct phy *generic_phy;
0862 struct qmp_phy *qphy;
0863 char prop_name[MAX_PROP_NAME];
0864 int ret;
0865
0866 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
0867 if (!qphy)
0868 return -ENOMEM;
0869
0870 qphy->cfg = cfg;
0871 qphy->serdes = serdes;
0872
0873
0874
0875
0876
0877
0878 qphy->tx = of_iomap(np, 0);
0879 if (!qphy->tx)
0880 return -ENOMEM;
0881
0882 qphy->rx = of_iomap(np, 1);
0883 if (!qphy->rx)
0884 return -ENOMEM;
0885
0886 qphy->pcs = of_iomap(np, 2);
0887 if (!qphy->pcs)
0888 return -ENOMEM;
0889
0890 qphy->pcs_misc = of_iomap(np, 3);
0891
0892 if (!qphy->pcs_misc)
0893 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
0894
0895 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
0896 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
0897 if (IS_ERR(qphy->pipe_clk)) {
0898 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
0899 "failed to get lane%d pipe clock\n", id);
0900 }
0901
0902
0903 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
0904 qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
0905 if (IS_ERR(qphy->lane_rst)) {
0906 dev_err(dev, "failed to get lane%d reset\n", id);
0907 return PTR_ERR(qphy->lane_rst);
0908 }
0909 ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
0910 qphy->lane_rst);
0911 if (ret)
0912 return ret;
0913
0914 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops);
0915 if (IS_ERR(generic_phy)) {
0916 ret = PTR_ERR(generic_phy);
0917 dev_err(dev, "failed to create qphy %d\n", ret);
0918 return ret;
0919 }
0920
0921 qphy->phy = generic_phy;
0922 qphy->index = id;
0923 qphy->qmp = qmp;
0924 qmp->phys[id] = qphy;
0925 phy_set_drvdata(generic_phy, qphy);
0926
0927 return 0;
0928 }
0929
0930 static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = {
0931 {
0932 .compatible = "qcom,msm8996-qmp-pcie-phy",
0933 .data = &msm8996_pciephy_cfg,
0934 },
0935 { },
0936 };
0937 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table);
0938
0939 static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
0940 {
0941 struct qcom_qmp *qmp;
0942 struct device *dev = &pdev->dev;
0943 struct device_node *child;
0944 struct phy_provider *phy_provider;
0945 void __iomem *serdes;
0946 const struct qmp_phy_cfg *cfg = NULL;
0947 int num, id, expected_phys;
0948 int ret;
0949
0950 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
0951 if (!qmp)
0952 return -ENOMEM;
0953
0954 qmp->dev = dev;
0955 dev_set_drvdata(dev, qmp);
0956
0957
0958 cfg = of_device_get_match_data(dev);
0959 if (!cfg)
0960 return -EINVAL;
0961
0962
0963 serdes = devm_platform_ioremap_resource(pdev, 0);
0964 if (IS_ERR(serdes))
0965 return PTR_ERR(serdes);
0966
0967 expected_phys = cfg->nlanes;
0968
0969 mutex_init(&qmp->phy_mutex);
0970
0971 ret = qcom_qmp_phy_pcie_msm8996_clk_init(dev, cfg);
0972 if (ret)
0973 return ret;
0974
0975 ret = qcom_qmp_phy_pcie_msm8996_reset_init(dev, cfg);
0976 if (ret)
0977 return ret;
0978
0979 ret = qcom_qmp_phy_pcie_msm8996_vreg_init(dev, cfg);
0980 if (ret) {
0981 if (ret != -EPROBE_DEFER)
0982 dev_err(dev, "failed to get regulator supplies: %d\n",
0983 ret);
0984 return ret;
0985 }
0986
0987 num = of_get_available_child_count(dev->of_node);
0988
0989 if (num > expected_phys)
0990 return -EINVAL;
0991
0992 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
0993 if (!qmp->phys)
0994 return -ENOMEM;
0995
0996 pm_runtime_set_active(dev);
0997 pm_runtime_enable(dev);
0998
0999
1000
1001
1002 pm_runtime_forbid(dev);
1003
1004 id = 0;
1005 for_each_available_child_of_node(dev->of_node, child) {
1006
1007 ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg);
1008 if (ret) {
1009 dev_err(dev, "failed to create lane%d phy, %d\n",
1010 id, ret);
1011 goto err_node_put;
1012 }
1013
1014
1015
1016
1017
1018 ret = phy_pipe_clk_register(qmp, child);
1019 if (ret) {
1020 dev_err(qmp->dev,
1021 "failed to register pipe clock source\n");
1022 goto err_node_put;
1023 }
1024
1025 id++;
1026 }
1027
1028 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1029 if (!IS_ERR(phy_provider))
1030 dev_info(dev, "Registered Qcom-QMP phy\n");
1031 else
1032 pm_runtime_disable(dev);
1033
1034 return PTR_ERR_OR_ZERO(phy_provider);
1035
1036 err_node_put:
1037 pm_runtime_disable(dev);
1038 of_node_put(child);
1039 return ret;
1040 }
1041
1042 static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = {
1043 .probe = qcom_qmp_phy_pcie_msm8996_probe,
1044 .driver = {
1045 .name = "qcom-qmp-msm8996-pcie-phy",
1046 .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table,
1047 },
1048 };
1049
1050 module_platform_driver(qcom_qmp_phy_pcie_msm8996_driver);
1051
1052 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1053 MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver");
1054 MODULE_LICENSE("GPL v2");