phy/qualcomm/phy-qcom-pcie2.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
0004  * Copyright (c) 2019, Linaro Ltd.
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/clk.h>
0009 #include <linux/iopoll.h>
0010 #include <linux/module.h>
0011 #include <linux/phy/phy.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/reset.h>
0014 #include <linux/slab.h>
0015
0016 #include <dt-bindings/phy/phy.h>
0017
0018 #define PCIE20_PARF_PHY_STTS         0x3c
0019 #define PCIE2_PHY_RESET_CTRL         0x44
0020 #define PCIE20_PARF_PHY_REFCLK_CTRL2 0xa0
0021 #define PCIE20_PARF_PHY_REFCLK_CTRL3 0xa4
0022 #define PCIE20_PARF_PCS_SWING_CTRL1  0x88
0023 #define PCIE20_PARF_PCS_SWING_CTRL2  0x8c
0024 #define PCIE20_PARF_PCS_DEEMPH1      0x74
0025 #define PCIE20_PARF_PCS_DEEMPH2      0x78
0026 #define PCIE20_PARF_PCS_DEEMPH3      0x7c
0027 #define PCIE20_PARF_CONFIGBITS       0x84
0028 #define PCIE20_PARF_PHY_CTRL3        0x94
0029 #define PCIE20_PARF_PCS_CTRL         0x80
0030
0031 #define TX_AMP_VAL                   120
0032 #define PHY_RX0_EQ_GEN1_VAL          0
0033 #define PHY_RX0_EQ_GEN2_VAL          4
0034 #define TX_DEEMPH_GEN1_VAL           24
0035 #define TX_DEEMPH_GEN2_3_5DB_VAL     26
0036 #define TX_DEEMPH_GEN2_6DB_VAL       36
0037 #define PHY_TX0_TERM_OFFST_VAL       0
0038
0039 struct qcom_phy {
0040     struct device *dev;
0041     void __iomem *base;
0042
0043     struct regulator_bulk_data vregs[2];
0044
0045     struct reset_control *phy_reset;
0046     struct reset_control *pipe_reset;
0047     struct clk *pipe_clk;
0048 };
0049
0050 static int qcom_pcie2_phy_init(struct phy *phy)
0051 {
0052     struct qcom_phy *qphy = phy_get_drvdata(phy);
0053     int ret;
0054
0055     ret = reset_control_deassert(qphy->phy_reset);
0056     if (ret) {
0057         dev_err(qphy->dev, "cannot deassert pipe reset\n");
0058         return ret;
0059     }
0060
0061     ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
0062     if (ret)
0063         reset_control_assert(qphy->phy_reset);
0064
0065     return ret;
0066 }
0067
0068 static int qcom_pcie2_phy_power_on(struct phy *phy)
0069 {
0070     struct qcom_phy *qphy = phy_get_drvdata(phy);
0071     int ret;
0072     u32 val;
0073
0074     /* Program REF_CLK source */
0075     val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
0076     val &= ~BIT(1);
0077     writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
0078
0079     usleep_range(1000, 2000);
0080
0081     /* Don't use PAD for refclock */
0082     val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
0083     val &= ~BIT(0);
0084     writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
0085
0086     /* Program SSP ENABLE */
0087     val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
0088     val |= BIT(0);
0089     writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
0090
0091     usleep_range(1000, 2000);
0092
0093     /* Assert Phy SW Reset */
0094     val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
0095     val |= BIT(0);
0096     writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
0097
0098     /* Program Tx Amplitude */
0099     val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
0100     val &= ~0x7f;
0101     val |= TX_AMP_VAL;
0102     writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
0103
0104     val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
0105     val &= ~0x7f;
0106     val |= TX_AMP_VAL;
0107     writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
0108
0109     /* Program De-Emphasis */
0110     val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1);
0111     val &= ~0x3f;
0112     val |= TX_DEEMPH_GEN2_6DB_VAL;
0113     writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1);
0114
0115     val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2);
0116     val &= ~0x3f;
0117     val |= TX_DEEMPH_GEN2_3_5DB_VAL;
0118     writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2);
0119
0120     val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3);
0121     val &= ~0x3f;
0122     val |= TX_DEEMPH_GEN1_VAL;
0123     writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3);
0124
0125     /* Program Rx_Eq */
0126     val = readl(qphy->base + PCIE20_PARF_CONFIGBITS);
0127     val &= ~0x7;
0128     val |= PHY_RX0_EQ_GEN2_VAL;
0129     writel(val, qphy->base + PCIE20_PARF_CONFIGBITS);
0130
0131     /* Program Tx0_term_offset */
0132     val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3);
0133     val &= ~0x1f;
0134     val |= PHY_TX0_TERM_OFFST_VAL;
0135     writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3);
0136
0137     /* disable Tx2Rx Loopback */
0138     val = readl(qphy->base + PCIE20_PARF_PCS_CTRL);
0139     val &= ~BIT(1);
0140     writel(val, qphy->base + PCIE20_PARF_PCS_CTRL);
0141
0142     /* De-assert Phy SW Reset */
0143     val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
0144     val &= ~BIT(0);
0145     writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
0146
0147     usleep_range(1000, 2000);
0148
0149     ret = reset_control_deassert(qphy->pipe_reset);
0150     if (ret) {
0151         dev_err(qphy->dev, "cannot deassert pipe reset\n");
0152         goto out;
0153     }
0154
0155     clk_set_rate(qphy->pipe_clk, 250000000);
0156
0157     ret = clk_prepare_enable(qphy->pipe_clk);
0158     if (ret) {
0159         dev_err(qphy->dev, "failed to enable pipe clock\n");
0160         goto out;
0161     }
0162
0163     ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val,
0164                  !(val & BIT(0)), 1000, 10);
0165     if (ret)
0166         dev_err(qphy->dev, "phy initialization failed\n");
0167
0168 out:
0169     return ret;
0170 }
0171
0172 static int qcom_pcie2_phy_power_off(struct phy *phy)
0173 {
0174     struct qcom_phy *qphy = phy_get_drvdata(phy);
0175     u32 val;
0176
0177     val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
0178     val |= BIT(0);
0179     writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
0180
0181     clk_disable_unprepare(qphy->pipe_clk);
0182     reset_control_assert(qphy->pipe_reset);
0183
0184     return 0;
0185 }
0186
0187 static int qcom_pcie2_phy_exit(struct phy *phy)
0188 {
0189     struct qcom_phy *qphy = phy_get_drvdata(phy);
0190
0191     regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
0192     reset_control_assert(qphy->phy_reset);
0193
0194     return 0;
0195 }
0196
0197 static const struct phy_ops qcom_pcie2_ops = {
0198     .init = qcom_pcie2_phy_init,
0199     .power_on = qcom_pcie2_phy_power_on,
0200     .power_off = qcom_pcie2_phy_power_off,
0201     .exit = qcom_pcie2_phy_exit,
0202     .owner = THIS_MODULE,
0203 };
0204
0205 /*
0206  * Register a fixed rate pipe clock.
0207  *
0208  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
0209  * controls it. The <s>_pipe_clk coming out of the GCC is requested
0210  * by the PHY driver for its operations.
0211  * We register the <s>_pipe_clksrc here. The gcc driver takes care
0212  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
0213  * Below picture shows this relationship.
0214  *
0215  *         +---------------+
0216  *         |   PHY block   |<<---------------------------------------+
0217  *         |               |                                         |
0218  *         |   +-------+   |                   +-----+               |
0219  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
0220  *    clk  |   +-------+   |                   +-----+
0221  *         +---------------+
0222  */
0223 static int phy_pipe_clksrc_register(struct qcom_phy *qphy)
0224 {
0225     struct device_node *np = qphy->dev->of_node;
0226     struct clk_fixed_rate *fixed;
0227     struct clk_init_data init = { };
0228     int ret;
0229
0230     ret = of_property_read_string(np, "clock-output-names", &init.name);
0231     if (ret) {
0232         dev_err(qphy->dev, "%s: No clock-output-names\n", np->name);
0233         return ret;
0234     }
0235
0236     fixed = devm_kzalloc(qphy->dev, sizeof(*fixed), GFP_KERNEL);
0237     if (!fixed)
0238         return -ENOMEM;
0239
0240     init.ops = &clk_fixed_rate_ops;
0241
0242     /* controllers using QMP phys use 250MHz pipe clock interface */
0243     fixed->fixed_rate = 250000000;
0244     fixed->hw.init = &init;
0245
0246     return devm_clk_hw_register(qphy->dev, &fixed->hw);
0247 }
0248
0249 static int qcom_pcie2_phy_probe(struct platform_device *pdev)
0250 {
0251     struct phy_provider *phy_provider;
0252     struct qcom_phy *qphy;
0253     struct device *dev = &pdev->dev;
0254     struct phy *phy;
0255     int ret;
0256
0257     qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
0258     if (!qphy)
0259         return -ENOMEM;
0260
0261     qphy->dev = dev;
0262     qphy->base = devm_platform_ioremap_resource(pdev, 0);
0263     if (IS_ERR(qphy->base))
0264         return PTR_ERR(qphy->base);
0265
0266     ret = phy_pipe_clksrc_register(qphy);
0267     if (ret) {
0268         dev_err(dev, "failed to register pipe_clk\n");
0269         return ret;
0270     }
0271
0272     qphy->vregs[0].supply = "vdda-vp";
0273     qphy->vregs[1].supply = "vdda-vph";
0274     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(qphy->vregs), qphy->vregs);
0275     if (ret < 0)
0276         return ret;
0277
0278     qphy->pipe_clk = devm_clk_get(dev, NULL);
0279     if (IS_ERR(qphy->pipe_clk)) {
0280         dev_err(dev, "failed to acquire pipe clock\n");
0281         return PTR_ERR(qphy->pipe_clk);
0282     }
0283
0284     qphy->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
0285     if (IS_ERR(qphy->phy_reset)) {
0286         dev_err(dev, "failed to acquire phy reset\n");
0287         return PTR_ERR(qphy->phy_reset);
0288     }
0289
0290     qphy->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
0291     if (IS_ERR(qphy->pipe_reset)) {
0292         dev_err(dev, "failed to acquire pipe reset\n");
0293         return PTR_ERR(qphy->pipe_reset);
0294     }
0295
0296     phy = devm_phy_create(dev, dev->of_node, &qcom_pcie2_ops);
0297     if (IS_ERR(phy)) {
0298         dev_err(dev, "failed to create phy\n");
0299         return PTR_ERR(phy);
0300     }
0301
0302     phy_set_drvdata(phy, qphy);
0303
0304     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0305     if (IS_ERR(phy_provider))
0306         dev_err(dev, "failed to register phy provider\n");
0307
0308     return PTR_ERR_OR_ZERO(phy_provider);
0309 }
0310
0311 static const struct of_device_id qcom_pcie2_phy_match_table[] = {
0312     { .compatible = "qcom,pcie2-phy" },
0313     {}
0314 };
0315 MODULE_DEVICE_TABLE(of, qcom_pcie2_phy_match_table);
0316
0317 static struct platform_driver qcom_pcie2_phy_driver = {
0318     .probe = qcom_pcie2_phy_probe,
0319     .driver = {
0320         .name = "phy-qcom-pcie2",
0321         .of_match_table = qcom_pcie2_phy_match_table,
0322     },
0323 };
0324
0325 module_platform_driver(qcom_pcie2_phy_driver);
0326
0327 MODULE_DESCRIPTION("Qualcomm PCIe PHY driver");
0328 MODULE_LICENSE("GPL v2");