Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003  * SerDes PHY driver for Microsemi Ocelot
0004  *
0005  * Copyright (c) 2018 Microsemi
0006  *
0007  */
0008 
0009 #include <linux/err.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/phy.h>
0015 #include <linux/phy/phy.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/regmap.h>
0018 #include <soc/mscc/ocelot_hsio.h>
0019 #include <dt-bindings/phy/phy-ocelot-serdes.h>
0020 
0021 struct serdes_ctrl {
0022     struct regmap       *regs;
0023     struct device       *dev;
0024     struct phy      *phys[SERDES_MAX];
0025 };
0026 
0027 struct serdes_macro {
0028     u8          idx;
0029     /* Not used when in QSGMII or PCIe mode */
0030     int         port;
0031     struct serdes_ctrl  *ctrl;
0032 };
0033 
0034 #define MCB_S6G_CFG_TIMEOUT     50
0035 
0036 static int __serdes_write_mcb_s6g(struct regmap *regmap, u8 macro, u32 op)
0037 {
0038     unsigned int regval = 0;
0039 
0040     regmap_write(regmap, HSIO_MCB_S6G_ADDR_CFG, op |
0041              HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(BIT(macro)));
0042 
0043     return regmap_read_poll_timeout(regmap, HSIO_MCB_S6G_ADDR_CFG, regval,
0044                     (regval & op) != op, 100,
0045                     MCB_S6G_CFG_TIMEOUT * 1000);
0046 }
0047 
0048 static int serdes_commit_mcb_s6g(struct regmap *regmap, u8 macro)
0049 {
0050     return __serdes_write_mcb_s6g(regmap, macro,
0051         HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT);
0052 }
0053 
0054 static int serdes_update_mcb_s6g(struct regmap *regmap, u8 macro)
0055 {
0056     return __serdes_write_mcb_s6g(regmap, macro,
0057         HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT);
0058 }
0059 
0060 static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode)
0061 {
0062     u32 pll_fsm_ctrl_data;
0063     u32 ob_ena1v_mode;
0064     u32 des_bw_ana;
0065     u32 ob_ena_cas;
0066     u32 if_mode;
0067     u32 ob_lev;
0068     u32 qrate;
0069     int ret;
0070 
0071     if (mode == PHY_INTERFACE_MODE_QSGMII) {
0072         pll_fsm_ctrl_data = 120;
0073         ob_ena1v_mode = 0;
0074         ob_ena_cas = 0;
0075         des_bw_ana = 5;
0076         ob_lev = 24;
0077         if_mode = 3;
0078         qrate = 0;
0079     } else {
0080         pll_fsm_ctrl_data = 60;
0081         ob_ena1v_mode = 1;
0082         ob_ena_cas = 2;
0083         des_bw_ana = 3;
0084         ob_lev = 48;
0085         if_mode = 1;
0086         qrate = 1;
0087     }
0088 
0089     ret = serdes_update_mcb_s6g(regmap, serdes);
0090     if (ret)
0091         return ret;
0092 
0093     /* Test pattern */
0094 
0095     regmap_update_bits(regmap, HSIO_S6G_COMMON_CFG,
0096                HSIO_S6G_COMMON_CFG_SYS_RST, 0);
0097 
0098     regmap_update_bits(regmap, HSIO_S6G_PLL_CFG,
0099                HSIO_S6G_PLL_CFG_PLL_FSM_ENA, 0);
0100 
0101     regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
0102                HSIO_S6G_IB_CFG_IB_SIG_DET_ENA |
0103                HSIO_S6G_IB_CFG_IB_REG_ENA |
0104                HSIO_S6G_IB_CFG_IB_SAM_ENA |
0105                HSIO_S6G_IB_CFG_IB_EQZ_ENA |
0106                HSIO_S6G_IB_CFG_IB_CONCUR |
0107                HSIO_S6G_IB_CFG_IB_CAL_ENA,
0108                HSIO_S6G_IB_CFG_IB_SIG_DET_ENA |
0109                HSIO_S6G_IB_CFG_IB_REG_ENA |
0110                HSIO_S6G_IB_CFG_IB_SAM_ENA |
0111                HSIO_S6G_IB_CFG_IB_EQZ_ENA |
0112                HSIO_S6G_IB_CFG_IB_CONCUR);
0113 
0114     regmap_update_bits(regmap, HSIO_S6G_IB_CFG1,
0115                HSIO_S6G_IB_CFG1_IB_FRC_OFFSET |
0116                HSIO_S6G_IB_CFG1_IB_FRC_LP |
0117                HSIO_S6G_IB_CFG1_IB_FRC_MID |
0118                HSIO_S6G_IB_CFG1_IB_FRC_HP |
0119                HSIO_S6G_IB_CFG1_IB_FILT_OFFSET |
0120                HSIO_S6G_IB_CFG1_IB_FILT_LP |
0121                HSIO_S6G_IB_CFG1_IB_FILT_MID |
0122                HSIO_S6G_IB_CFG1_IB_FILT_HP,
0123                HSIO_S6G_IB_CFG1_IB_FILT_OFFSET |
0124                HSIO_S6G_IB_CFG1_IB_FILT_HP |
0125                HSIO_S6G_IB_CFG1_IB_FILT_LP |
0126                HSIO_S6G_IB_CFG1_IB_FILT_MID);
0127 
0128     regmap_update_bits(regmap, HSIO_S6G_IB_CFG2,
0129                HSIO_S6G_IB_CFG2_IB_UREG_M,
0130                HSIO_S6G_IB_CFG2_IB_UREG(4));
0131 
0132     regmap_update_bits(regmap, HSIO_S6G_IB_CFG3,
0133                HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M |
0134                HSIO_S6G_IB_CFG3_IB_INI_LP_M |
0135                HSIO_S6G_IB_CFG3_IB_INI_MID_M |
0136                HSIO_S6G_IB_CFG3_IB_INI_HP_M,
0137                HSIO_S6G_IB_CFG3_IB_INI_OFFSET(31) |
0138                HSIO_S6G_IB_CFG3_IB_INI_LP(1) |
0139                HSIO_S6G_IB_CFG3_IB_INI_MID(31) |
0140                HSIO_S6G_IB_CFG3_IB_INI_HP(0));
0141 
0142     regmap_update_bits(regmap, HSIO_S6G_MISC_CFG,
0143                HSIO_S6G_MISC_CFG_LANE_RST,
0144                HSIO_S6G_MISC_CFG_LANE_RST);
0145 
0146     ret = serdes_commit_mcb_s6g(regmap, serdes);
0147     if (ret)
0148         return ret;
0149 
0150     /* OB + DES + IB + SER CFG */
0151     regmap_update_bits(regmap, HSIO_S6G_OB_CFG,
0152                HSIO_S6G_OB_CFG_OB_IDLE |
0153                HSIO_S6G_OB_CFG_OB_ENA1V_MODE |
0154                HSIO_S6G_OB_CFG_OB_POST0_M |
0155                HSIO_S6G_OB_CFG_OB_PREC_M,
0156                (ob_ena1v_mode ? HSIO_S6G_OB_CFG_OB_ENA1V_MODE : 0) |
0157                HSIO_S6G_OB_CFG_OB_POST0(0) |
0158                HSIO_S6G_OB_CFG_OB_PREC(0));
0159 
0160     regmap_update_bits(regmap, HSIO_S6G_OB_CFG1,
0161                HSIO_S6G_OB_CFG1_OB_ENA_CAS_M |
0162                HSIO_S6G_OB_CFG1_OB_LEV_M,
0163                HSIO_S6G_OB_CFG1_OB_LEV(ob_lev) |
0164                HSIO_S6G_OB_CFG1_OB_ENA_CAS(ob_ena_cas));
0165 
0166     regmap_update_bits(regmap, HSIO_S6G_DES_CFG,
0167                HSIO_S6G_DES_CFG_DES_PHS_CTRL_M |
0168                HSIO_S6G_DES_CFG_DES_CPMD_SEL_M |
0169                HSIO_S6G_DES_CFG_DES_BW_ANA_M,
0170                HSIO_S6G_DES_CFG_DES_PHS_CTRL(2) |
0171                HSIO_S6G_DES_CFG_DES_CPMD_SEL(0) |
0172                HSIO_S6G_DES_CFG_DES_BW_ANA(des_bw_ana));
0173 
0174     regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
0175                HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M |
0176                HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M,
0177                HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(0) |
0178                HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(0));
0179 
0180     regmap_update_bits(regmap, HSIO_S6G_IB_CFG1,
0181                HSIO_S6G_IB_CFG1_IB_TSDET_M,
0182                HSIO_S6G_IB_CFG1_IB_TSDET(16));
0183 
0184     regmap_update_bits(regmap, HSIO_S6G_SER_CFG,
0185                HSIO_S6G_SER_CFG_SER_ALISEL_M |
0186                HSIO_S6G_SER_CFG_SER_ENALI,
0187                HSIO_S6G_SER_CFG_SER_ALISEL(0));
0188 
0189     regmap_update_bits(regmap, HSIO_S6G_PLL_CFG,
0190                HSIO_S6G_PLL_CFG_PLL_DIV4 |
0191                HSIO_S6G_PLL_CFG_PLL_ENA_ROT |
0192                HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M |
0193                HSIO_S6G_PLL_CFG_PLL_ROT_DIR |
0194                HSIO_S6G_PLL_CFG_PLL_ROT_FRQ,
0195                HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA
0196                (pll_fsm_ctrl_data));
0197 
0198     regmap_update_bits(regmap, HSIO_S6G_COMMON_CFG,
0199                HSIO_S6G_COMMON_CFG_SYS_RST |
0200                HSIO_S6G_COMMON_CFG_ENA_LANE |
0201                HSIO_S6G_COMMON_CFG_PWD_RX |
0202                HSIO_S6G_COMMON_CFG_PWD_TX |
0203                HSIO_S6G_COMMON_CFG_HRATE |
0204                HSIO_S6G_COMMON_CFG_QRATE |
0205                HSIO_S6G_COMMON_CFG_ENA_ELOOP |
0206                HSIO_S6G_COMMON_CFG_ENA_FLOOP |
0207                HSIO_S6G_COMMON_CFG_IF_MODE_M,
0208                HSIO_S6G_COMMON_CFG_SYS_RST |
0209                HSIO_S6G_COMMON_CFG_ENA_LANE |
0210                (qrate ? HSIO_S6G_COMMON_CFG_QRATE : 0) |
0211                HSIO_S6G_COMMON_CFG_IF_MODE(if_mode));
0212 
0213     regmap_update_bits(regmap, HSIO_S6G_MISC_CFG,
0214                HSIO_S6G_MISC_CFG_LANE_RST |
0215                HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA |
0216                HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA |
0217                HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA,
0218                HSIO_S6G_MISC_CFG_LANE_RST |
0219                HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA);
0220 
0221 
0222     ret = serdes_commit_mcb_s6g(regmap, serdes);
0223     if (ret)
0224         return ret;
0225 
0226     regmap_update_bits(regmap, HSIO_S6G_PLL_CFG,
0227                HSIO_S6G_PLL_CFG_PLL_FSM_ENA,
0228                HSIO_S6G_PLL_CFG_PLL_FSM_ENA);
0229 
0230     ret = serdes_commit_mcb_s6g(regmap, serdes);
0231     if (ret)
0232         return ret;
0233 
0234     /* Wait for PLL bringup */
0235     msleep(20);
0236 
0237     regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
0238                HSIO_S6G_IB_CFG_IB_CAL_ENA,
0239                HSIO_S6G_IB_CFG_IB_CAL_ENA);
0240 
0241     regmap_update_bits(regmap, HSIO_S6G_MISC_CFG,
0242                HSIO_S6G_MISC_CFG_LANE_RST, 0);
0243 
0244     ret = serdes_commit_mcb_s6g(regmap, serdes);
0245     if (ret)
0246         return ret;
0247 
0248     /* Wait for calibration */
0249     msleep(60);
0250 
0251     regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
0252                HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M |
0253                HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M,
0254                HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(0) |
0255                HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(7));
0256 
0257     regmap_update_bits(regmap, HSIO_S6G_IB_CFG1,
0258                HSIO_S6G_IB_CFG1_IB_TSDET_M,
0259                HSIO_S6G_IB_CFG1_IB_TSDET(3));
0260 
0261     /* IB CFG */
0262 
0263     return 0;
0264 }
0265 
0266 #define MCB_S1G_CFG_TIMEOUT     50
0267 
0268 static int __serdes_write_mcb_s1g(struct regmap *regmap, u8 macro, u32 op)
0269 {
0270     unsigned int regval;
0271 
0272     regmap_write(regmap, HSIO_MCB_S1G_ADDR_CFG, op |
0273              HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(BIT(macro)));
0274 
0275     return regmap_read_poll_timeout(regmap, HSIO_MCB_S1G_ADDR_CFG, regval,
0276                     (regval & op) != op, 100,
0277                     MCB_S1G_CFG_TIMEOUT * 1000);
0278 }
0279 
0280 static int serdes_commit_mcb_s1g(struct regmap *regmap, u8 macro)
0281 {
0282     return __serdes_write_mcb_s1g(regmap, macro,
0283         HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT);
0284 }
0285 
0286 static int serdes_update_mcb_s1g(struct regmap *regmap, u8 macro)
0287 {
0288     return __serdes_write_mcb_s1g(regmap, macro,
0289         HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT);
0290 }
0291 
0292 static int serdes_init_s1g(struct regmap *regmap, u8 serdes)
0293 {
0294     int ret;
0295 
0296     ret = serdes_update_mcb_s1g(regmap, serdes);
0297     if (ret)
0298         return ret;
0299 
0300     regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG,
0301                HSIO_S1G_COMMON_CFG_SYS_RST |
0302                HSIO_S1G_COMMON_CFG_ENA_LANE |
0303                HSIO_S1G_COMMON_CFG_ENA_ELOOP |
0304                HSIO_S1G_COMMON_CFG_ENA_FLOOP,
0305                HSIO_S1G_COMMON_CFG_ENA_LANE);
0306 
0307     regmap_update_bits(regmap, HSIO_S1G_PLL_CFG,
0308                HSIO_S1G_PLL_CFG_PLL_FSM_ENA |
0309                HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M,
0310                HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(200) |
0311                HSIO_S1G_PLL_CFG_PLL_FSM_ENA);
0312 
0313     regmap_update_bits(regmap, HSIO_S1G_MISC_CFG,
0314                HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA |
0315                HSIO_S1G_MISC_CFG_LANE_RST,
0316                HSIO_S1G_MISC_CFG_LANE_RST);
0317 
0318     ret = serdes_commit_mcb_s1g(regmap, serdes);
0319     if (ret)
0320         return ret;
0321 
0322     regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG,
0323                HSIO_S1G_COMMON_CFG_SYS_RST,
0324                HSIO_S1G_COMMON_CFG_SYS_RST);
0325 
0326     regmap_update_bits(regmap, HSIO_S1G_MISC_CFG,
0327                HSIO_S1G_MISC_CFG_LANE_RST, 0);
0328 
0329     ret = serdes_commit_mcb_s1g(regmap, serdes);
0330     if (ret)
0331         return ret;
0332 
0333     return 0;
0334 }
0335 
0336 struct serdes_mux {
0337     u8          idx;
0338     u8          port;
0339     enum phy_mode       mode;
0340     int         submode;
0341     u32         mask;
0342     u32         mux;
0343 };
0344 
0345 #define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \
0346     .idx = _idx,                        \
0347     .port = _port,                      \
0348     .mode = _mode,                      \
0349     .submode = _submode,                    \
0350     .mask = _mask,                      \
0351     .mux = _mux,                        \
0352 }
0353 
0354 #define SERDES_MUX_SGMII(i, p, m, c) \
0355     SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c)
0356 #define SERDES_MUX_QSGMII(i, p, m, c) \
0357     SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c)
0358 
0359 static const struct serdes_mux ocelot_serdes_muxes[] = {
0360     SERDES_MUX_SGMII(SERDES1G(0), 0, 0, 0),
0361     SERDES_MUX_SGMII(SERDES1G(1), 1, HSIO_HW_CFG_DEV1G_5_MODE, 0),
0362     SERDES_MUX_SGMII(SERDES1G(1), 5, HSIO_HW_CFG_QSGMII_ENA |
0363              HSIO_HW_CFG_DEV1G_5_MODE, HSIO_HW_CFG_DEV1G_5_MODE),
0364     SERDES_MUX_SGMII(SERDES1G(2), 2, HSIO_HW_CFG_DEV1G_4_MODE, 0),
0365     SERDES_MUX_SGMII(SERDES1G(2), 4, HSIO_HW_CFG_QSGMII_ENA |
0366              HSIO_HW_CFG_DEV1G_4_MODE, HSIO_HW_CFG_DEV1G_4_MODE),
0367     SERDES_MUX_SGMII(SERDES1G(3), 3, HSIO_HW_CFG_DEV1G_6_MODE, 0),
0368     SERDES_MUX_SGMII(SERDES1G(3), 6, HSIO_HW_CFG_QSGMII_ENA |
0369              HSIO_HW_CFG_DEV1G_6_MODE, HSIO_HW_CFG_DEV1G_6_MODE),
0370     SERDES_MUX_SGMII(SERDES1G(4), 4, HSIO_HW_CFG_QSGMII_ENA |
0371              HSIO_HW_CFG_DEV1G_4_MODE | HSIO_HW_CFG_DEV1G_9_MODE,
0372              0),
0373     SERDES_MUX_SGMII(SERDES1G(4), 9, HSIO_HW_CFG_DEV1G_4_MODE |
0374              HSIO_HW_CFG_DEV1G_9_MODE, HSIO_HW_CFG_DEV1G_4_MODE |
0375              HSIO_HW_CFG_DEV1G_9_MODE),
0376     SERDES_MUX_SGMII(SERDES1G(5), 5, HSIO_HW_CFG_QSGMII_ENA |
0377              HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE,
0378              0),
0379     SERDES_MUX_SGMII(SERDES1G(5), 10, HSIO_HW_CFG_PCIE_ENA |
0380              HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE,
0381              HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE),
0382     SERDES_MUX_QSGMII(SERDES6G(0), 4, HSIO_HW_CFG_QSGMII_ENA,
0383               HSIO_HW_CFG_QSGMII_ENA),
0384     SERDES_MUX_QSGMII(SERDES6G(0), 5, HSIO_HW_CFG_QSGMII_ENA,
0385               HSIO_HW_CFG_QSGMII_ENA),
0386     SERDES_MUX_QSGMII(SERDES6G(0), 6, HSIO_HW_CFG_QSGMII_ENA,
0387               HSIO_HW_CFG_QSGMII_ENA),
0388     SERDES_MUX_SGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA, 0),
0389     SERDES_MUX_QSGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA,
0390               HSIO_HW_CFG_QSGMII_ENA),
0391     SERDES_MUX_SGMII(SERDES6G(1), 8, 0, 0),
0392     SERDES_MUX_SGMII(SERDES6G(2), 10, HSIO_HW_CFG_PCIE_ENA |
0393              HSIO_HW_CFG_DEV2G5_10_MODE, 0),
0394     SERDES_MUX(SERDES6G(2), 10, PHY_MODE_PCIE, 0, HSIO_HW_CFG_PCIE_ENA,
0395            HSIO_HW_CFG_PCIE_ENA),
0396 };
0397 
0398 static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
0399 {
0400     struct serdes_macro *macro = phy_get_drvdata(phy);
0401     unsigned int i;
0402     int ret;
0403 
0404     /* As of now only PHY_MODE_ETHERNET is supported */
0405     if (mode != PHY_MODE_ETHERNET)
0406         return -EOPNOTSUPP;
0407 
0408     for (i = 0; i < ARRAY_SIZE(ocelot_serdes_muxes); i++) {
0409         if (macro->idx != ocelot_serdes_muxes[i].idx ||
0410             mode != ocelot_serdes_muxes[i].mode ||
0411             submode != ocelot_serdes_muxes[i].submode)
0412             continue;
0413 
0414         if (submode != PHY_INTERFACE_MODE_QSGMII &&
0415             macro->port != ocelot_serdes_muxes[i].port)
0416             continue;
0417 
0418         ret = regmap_update_bits(macro->ctrl->regs, HSIO_HW_CFG,
0419                      ocelot_serdes_muxes[i].mask,
0420                      ocelot_serdes_muxes[i].mux);
0421         if (ret)
0422             return ret;
0423 
0424         if (macro->idx <= SERDES1G_MAX)
0425             return serdes_init_s1g(macro->ctrl->regs, macro->idx);
0426         else if (macro->idx <= SERDES6G_MAX)
0427             return serdes_init_s6g(macro->ctrl->regs,
0428                            macro->idx - (SERDES1G_MAX + 1),
0429                            ocelot_serdes_muxes[i].submode);
0430 
0431         /* PCIe not supported yet */
0432         return -EOPNOTSUPP;
0433     }
0434 
0435     return -EINVAL;
0436 }
0437 
0438 static const struct phy_ops serdes_ops = {
0439     .set_mode   = serdes_set_mode,
0440     .owner      = THIS_MODULE,
0441 };
0442 
0443 static struct phy *serdes_simple_xlate(struct device *dev,
0444                        struct of_phandle_args *args)
0445 {
0446     struct serdes_ctrl *ctrl = dev_get_drvdata(dev);
0447     unsigned int port, idx, i;
0448 
0449     if (args->args_count != 2)
0450         return ERR_PTR(-EINVAL);
0451 
0452     port = args->args[0];
0453     idx = args->args[1];
0454 
0455     for (i = 0; i < SERDES_MAX; i++) {
0456         struct serdes_macro *macro = phy_get_drvdata(ctrl->phys[i]);
0457 
0458         if (idx != macro->idx)
0459             continue;
0460 
0461         /* SERDES6G(0) is the only SerDes capable of QSGMII */
0462         if (idx != SERDES6G(0) && macro->port >= 0)
0463             return ERR_PTR(-EBUSY);
0464 
0465         macro->port = port;
0466         return ctrl->phys[i];
0467     }
0468 
0469     return ERR_PTR(-ENODEV);
0470 }
0471 
0472 static int serdes_phy_create(struct serdes_ctrl *ctrl, u8 idx, struct phy **phy)
0473 {
0474     struct serdes_macro *macro;
0475 
0476     *phy = devm_phy_create(ctrl->dev, NULL, &serdes_ops);
0477     if (IS_ERR(*phy))
0478         return PTR_ERR(*phy);
0479 
0480     macro = devm_kzalloc(ctrl->dev, sizeof(*macro), GFP_KERNEL);
0481     if (!macro)
0482         return -ENOMEM;
0483 
0484     macro->idx = idx;
0485     macro->ctrl = ctrl;
0486     macro->port = -1;
0487 
0488     phy_set_drvdata(*phy, macro);
0489 
0490     return 0;
0491 }
0492 
0493 static int serdes_probe(struct platform_device *pdev)
0494 {
0495     struct phy_provider *provider;
0496     struct serdes_ctrl *ctrl;
0497     unsigned int i;
0498     int ret;
0499 
0500     ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
0501     if (!ctrl)
0502         return -ENOMEM;
0503 
0504     ctrl->dev = &pdev->dev;
0505     ctrl->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
0506     if (IS_ERR(ctrl->regs))
0507         return PTR_ERR(ctrl->regs);
0508 
0509     for (i = 0; i < SERDES_MAX; i++) {
0510         ret = serdes_phy_create(ctrl, i, &ctrl->phys[i]);
0511         if (ret)
0512             return ret;
0513     }
0514 
0515     dev_set_drvdata(&pdev->dev, ctrl);
0516 
0517     provider = devm_of_phy_provider_register(ctrl->dev,
0518                          serdes_simple_xlate);
0519 
0520     return PTR_ERR_OR_ZERO(provider);
0521 }
0522 
0523 static const struct of_device_id serdes_ids[] = {
0524     { .compatible = "mscc,vsc7514-serdes", },
0525     {},
0526 };
0527 MODULE_DEVICE_TABLE(of, serdes_ids);
0528 
0529 static struct platform_driver mscc_ocelot_serdes = {
0530     .probe      = serdes_probe,
0531     .driver     = {
0532         .name   = "mscc,ocelot-serdes",
0533         .of_match_table = of_match_ptr(serdes_ids),
0534     },
0535 };
0536 
0537 module_platform_driver(mscc_ocelot_serdes);
0538 
0539 MODULE_AUTHOR("Quentin Schulz <quentin.schulz@bootlin.com>");
0540 MODULE_DESCRIPTION("SerDes driver for Microsemi Ocelot");
0541 MODULE_LICENSE("Dual MIT/GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!