phy/microchip/sparx5_serdes_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0+
0002  * Microchip Sparx5 SerDes driver
0003  *
0004  * Copyright (c) 2020 Microchip Technology Inc.
0005  */
0006
0007 /* This file is autogenerated by cml-utils 2020-11-16 13:11:27 +0100.
0008  * Commit ID: 13bdf073131d8bf40c54901df6988ae4e9c8f29f
0009  */
0010
0011 #ifndef _SPARX5_SERDES_REGS_H_
0012 #define _SPARX5_SERDES_REGS_H_
0013
0014 #include <linux/bitfield.h>
0015 #include <linux/types.h>
0016 #include <linux/bug.h>
0017
0018 enum sparx5_serdes_target {
0019     TARGET_SD10G_LANE = 200,
0020     TARGET_SD25G_LANE = 212,
0021     TARGET_SD6G_LANE = 233,
0022     TARGET_SD_CMU = 248,
0023     TARGET_SD_CMU_CFG = 262,
0024     TARGET_SD_LANE = 276,
0025     TARGET_SD_LANE_25G = 301,
0026     NUM_TARGETS = 332
0027 };
0028
0029 #define __REG(...)    __VA_ARGS__
0030
0031 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */
0032 #define SD10G_LANE_LANE_01(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4)
0033
0034 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
0035 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
0036     FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
0037 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
0038     FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
0039
0040 #define SD10G_LANE_LANE_01_CFG_RXDET_EN          BIT(4)
0041 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\
0042     FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
0043 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\
0044     FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
0045
0046 #define SD10G_LANE_LANE_01_CFG_RXDET_STR         BIT(5)
0047 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\
0048     FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
0049 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\
0050     FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
0051
0052 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */
0053 #define SD10G_LANE_LANE_02(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4)
0054
0055 #define SD10G_LANE_LANE_02_CFG_EN_ADV            BIT(0)
0056 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\
0057     FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
0058 #define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\
0059     FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
0060
0061 #define SD10G_LANE_LANE_02_CFG_EN_MAIN           BIT(1)
0062 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\
0063     FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
0064 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\
0065     FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
0066
0067 #define SD10G_LANE_LANE_02_CFG_EN_DLY            BIT(2)
0068 #define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\
0069     FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
0070 #define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\
0071     FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
0072
0073 #define SD10G_LANE_LANE_02_CFG_EN_DLY2           BIT(3)
0074 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\
0075     FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
0076 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\
0077     FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
0078
0079 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0       GENMASK(7, 4)
0080 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\
0081     FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
0082 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\
0083     FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
0084
0085 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */
0086 #define SD10G_LANE_LANE_03(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4)
0087
0088 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN          BIT(0)
0089 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\
0090     FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
0091 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\
0092     FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
0093
0094 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */
0095 #define SD10G_LANE_LANE_04(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4)
0096
0097 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0       GENMASK(4, 0)
0098 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\
0099     FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
0100 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\
0101     FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
0102
0103 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */
0104 #define SD10G_LANE_LANE_06(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4)
0105
0106 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER         BIT(0)
0107 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\
0108     FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
0109 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\
0110     FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
0111
0112 #define SD10G_LANE_LANE_06_CFG_PD_CLK            BIT(1)
0113 #define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\
0114     FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
0115 #define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\
0116     FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
0117
0118 #define SD10G_LANE_LANE_06_CFG_PD_CML            BIT(2)
0119 #define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\
0120     FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x)
0121 #define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\
0122     FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x)
0123
0124 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN       BIT(3)
0125 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\
0126     FIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
0127 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\
0128     FIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
0129
0130 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN       BIT(4)
0131 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\
0132     FIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
0133 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\
0134     FIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
0135
0136 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH        BIT(5)
0137 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\
0138     FIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
0139 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\
0140     FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
0141
0142 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */
0143 #define SD10G_LANE_LANE_0B(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 44, 0, 1, 4)
0144
0145 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0        GENMASK(3, 0)
0146 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\
0147     FIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
0148 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\
0149     FIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
0150
0151 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE           BIT(4)
0152 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\
0153     FIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
0154 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\
0155     FIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
0156
0157 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN        BIT(5)
0158 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\
0159     FIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
0160 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\
0161     FIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
0162
0163 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE  BIT(6)
0164 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\
0165     FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
0166 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\
0167     FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
0168
0169 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ   BIT(7)
0170 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\
0171     FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
0172 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\
0173     FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
0174
0175 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */
0176 #define SD10G_LANE_LANE_0C(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 48, 0, 1, 4)
0177
0178 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE         BIT(0)
0179 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\
0180     FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
0181 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\
0182     FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
0183
0184 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ          BIT(1)
0185 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\
0186     FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
0187 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\
0188     FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
0189
0190 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE      BIT(2)
0191 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\
0192     FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
0193 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\
0194     FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
0195
0196 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ       BIT(3)
0197 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\
0198     FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
0199 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\
0200     FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
0201
0202 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE      BIT(4)
0203 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\
0204     FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
0205 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\
0206     FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
0207
0208 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ       BIT(5)
0209 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\
0210     FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
0211 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\
0212     FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
0213
0214 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS          BIT(6)
0215 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\
0216     FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
0217 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\
0218     FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
0219
0220 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12     BIT(7)
0221 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\
0222     FIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
0223 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\
0224     FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
0225
0226 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */
0227 #define SD10G_LANE_LANE_0D(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 52, 0, 1, 4)
0228
0229 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0    GENMASK(1, 0)
0230 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\
0231     FIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
0232 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\
0233     FIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
0234
0235 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP           BIT(4)
0236 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\
0237     FIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
0238 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\
0239     FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
0240
0241 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */
0242 #define SD10G_LANE_LANE_0E(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 56, 0, 1, 4)
0243
0244 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0     GENMASK(3, 0)
0245 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\
0246     FIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
0247 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\
0248     FIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
0249
0250 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN           BIT(4)
0251 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\
0252     FIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
0253 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\
0254     FIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
0255
0256 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN           BIT(5)
0257 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\
0258     FIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
0259 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\
0260     FIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
0261
0262 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN      BIT(6)
0263 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\
0264     FIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
0265 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\
0266     FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
0267
0268 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */
0269 #define SD10G_LANE_LANE_0F(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 60, 0, 1, 4)
0270
0271 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0      GENMASK(7, 0)
0272 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\
0273     FIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
0274 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\
0275     FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
0276
0277 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */
0278 #define SD10G_LANE_LANE_13(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 76, 0, 1, 4)
0279
0280 #define SD10G_LANE_LANE_13_CFG_DCDR_PD           BIT(0)
0281 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\
0282     FIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
0283 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\
0284     FIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
0285
0286 #define SD10G_LANE_LANE_13_CFG_PHID_1T           BIT(1)
0287 #define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\
0288     FIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
0289 #define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\
0290     FIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
0291
0292 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN          BIT(2)
0293 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\
0294     FIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
0295 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\
0296     FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
0297
0298 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */
0299 #define SD10G_LANE_LANE_14(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 80, 0, 1, 4)
0300
0301 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0    GENMASK(7, 0)
0302 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\
0303     FIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
0304 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\
0305     FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
0306
0307 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */
0308 #define SD10G_LANE_LANE_15(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 84, 0, 1, 4)
0309
0310 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8   GENMASK(7, 0)
0311 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\
0312     FIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
0313 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\
0314     FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
0315
0316 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */
0317 #define SD10G_LANE_LANE_16(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 88, 0, 1, 4)
0318
0319 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16  GENMASK(7, 0)
0320 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\
0321     FIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
0322 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\
0323     FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
0324
0325 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */
0326 #define SD10G_LANE_LANE_1A(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 104, 0, 1, 4)
0327
0328 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN      BIT(0)
0329 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\
0330     FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
0331 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\
0332     FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
0333
0334 #define SD10G_LANE_LANE_1A_CFG_PI_EN             BIT(1)
0335 #define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\
0336     FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
0337 #define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\
0338     FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
0339
0340 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN         BIT(2)
0341 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\
0342     FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
0343 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\
0344     FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
0345
0346 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS          BIT(3)
0347 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\
0348     FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
0349 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\
0350     FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
0351
0352 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)
0353 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\
0354     FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
0355 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\
0356     FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
0357
0358 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */
0359 #define SD10G_LANE_LANE_22(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 136, 0, 1, 4)
0360
0361 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1     GENMASK(4, 0)
0362 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\
0363     FIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
0364 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\
0365     FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
0366
0367 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */
0368 #define SD10G_LANE_LANE_23(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 140, 0, 1, 4)
0369
0370 #define SD10G_LANE_LANE_23_CFG_DFE_PD            BIT(0)
0371 #define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\
0372     FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
0373 #define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\
0374     FIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
0375
0376 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG         BIT(1)
0377 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\
0378     FIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
0379 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\
0380     FIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
0381
0382 #define SD10G_LANE_LANE_23_CFG_DFECK_EN          BIT(2)
0383 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\
0384     FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
0385 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\
0386     FIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
0387
0388 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD         BIT(3)
0389 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\
0390     FIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
0391 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\
0392     FIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
0393
0394 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0      GENMASK(6, 4)
0395 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\
0396     FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
0397 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\
0398     FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
0399
0400 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */
0401 #define SD10G_LANE_LANE_24(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 144, 0, 1, 4)
0402
0403 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0    GENMASK(3, 0)
0404 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\
0405     FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
0406 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\
0407     FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
0408
0409 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0    GENMASK(7, 4)
0410 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\
0411     FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
0412 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\
0413     FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
0414
0415 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */
0416 #define SD10G_LANE_LANE_26(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 152, 0, 1, 4)
0417
0418 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0)
0419 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\
0420     FIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
0421 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\
0422     FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
0423
0424 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */
0425 #define SD10G_LANE_LANE_2F(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 188, 0, 1, 4)
0426
0427 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0        GENMASK(2, 0)
0428 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\
0429     FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
0430 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\
0431     FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
0432
0433 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0      GENMASK(7, 4)
0434 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\
0435     FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
0436 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\
0437     FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
0438
0439 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */
0440 #define SD10G_LANE_LANE_30(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 192, 0, 1, 4)
0441
0442 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN         BIT(0)
0443 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\
0444     FIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
0445 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\
0446     FIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
0447
0448 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0     GENMASK(6, 4)
0449 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\
0450     FIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
0451 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\
0452     FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
0453
0454 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */
0455 #define SD10G_LANE_LANE_31(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 196, 0, 1, 4)
0456
0457 #define SD10G_LANE_LANE_31_CFG_PI_RSTN           BIT(0)
0458 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\
0459     FIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
0460 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\
0461     FIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
0462
0463 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN          BIT(1)
0464 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\
0465     FIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
0466 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\
0467     FIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
0468
0469 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG       BIT(2)
0470 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\
0471     FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
0472 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\
0473     FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
0474
0475 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN         BIT(3)
0476 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\
0477     FIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
0478 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\
0479     FIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
0480
0481 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8       BIT(4)
0482 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\
0483     FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
0484 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\
0485     FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
0486
0487 #define SD10G_LANE_LANE_31_CFG_R50_EN            BIT(5)
0488 #define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\
0489     FIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x)
0490 #define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\
0491     FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x)
0492
0493 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */
0494 #define SD10G_LANE_LANE_32(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 200, 0, 1, 4)
0495
0496 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)
0497 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\
0498     FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
0499 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\
0500     FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
0501
0502 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
0503 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\
0504     FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
0505 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\
0506     FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
0507
0508 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */
0509 #define SD10G_LANE_LANE_33(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 204, 0, 1, 4)
0510
0511 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)
0512 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
0513     FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
0514 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
0515     FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
0516
0517 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)
0518 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\
0519     FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
0520 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\
0521     FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
0522
0523 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */
0524 #define SD10G_LANE_LANE_35(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 212, 0, 1, 4)
0525
0526 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0        GENMASK(1, 0)
0527 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\
0528     FIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
0529 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\
0530     FIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
0531
0532 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0        GENMASK(5, 4)
0533 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\
0534     FIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
0535 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\
0536     FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
0537
0538 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */
0539 #define SD10G_LANE_LANE_36(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 216, 0, 1, 4)
0540
0541 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)
0542 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\
0543     FIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
0544 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\
0545     FIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
0546
0547 #define SD10G_LANE_LANE_36_CFG_EID_LP            BIT(4)
0548 #define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\
0549     FIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x)
0550 #define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\
0551     FIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x)
0552
0553 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH    BIT(5)
0554 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\
0555     FIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
0556 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\
0557     FIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
0558
0559 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL          BIT(6)
0560 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\
0561     FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
0562 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\
0563     FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
0564
0565 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB         BIT(7)
0566 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\
0567     FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
0568 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\
0569     FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
0570
0571 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */
0572 #define SD10G_LANE_LANE_37(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 220, 0, 1, 4)
0573
0574 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD     BIT(0)
0575 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\
0576     FIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
0577 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\
0578     FIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
0579
0580 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE      BIT(1)
0581 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\
0582     FIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
0583 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\
0584     FIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
0585
0586 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF      BIT(2)
0587 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\
0588     FIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
0589 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\
0590     FIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
0591
0592 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0   GENMASK(5, 4)
0593 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\
0594     FIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
0595 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\
0596     FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
0597
0598 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */
0599 #define SD10G_LANE_LANE_39(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 228, 0, 1, 4)
0600
0601 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0      GENMASK(2, 0)
0602 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\
0603     FIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
0604 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\
0605     FIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
0606
0607 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH         BIT(4)
0608 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\
0609     FIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
0610 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\
0611     FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
0612
0613 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */
0614 #define SD10G_LANE_LANE_3A(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 232, 0, 1, 4)
0615
0616 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0        GENMASK(3, 0)
0617 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\
0618     FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
0619 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\
0620     FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
0621
0622 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0        GENMASK(7, 4)
0623 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\
0624     FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
0625 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\
0626     FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
0627
0628 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */
0629 #define SD10G_LANE_LANE_3C(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 240, 0, 1, 4)
0630
0631 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC           BIT(0)
0632 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\
0633     FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
0634 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\
0635     FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
0636
0637 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER      BIT(1)
0638 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\
0639     FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
0640 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\
0641     FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
0642
0643 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */
0644 #define SD10G_LANE_LANE_40(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 256, 0, 1, 4)
0645
0646 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0  GENMASK(7, 0)
0647 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\
0648     FIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
0649 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\
0650     FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
0651
0652 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */
0653 #define SD10G_LANE_LANE_41(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 260, 0, 1, 4)
0654
0655 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0)
0656 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\
0657     FIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
0658 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\
0659     FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
0660
0661 /*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */
0662 #define SD10G_LANE_LANE_42(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 264, 0, 1, 4)
0663
0664 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0   GENMASK(2, 0)
0665 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\
0666     FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
0667 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\
0668     FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
0669
0670 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0   GENMASK(6, 4)
0671 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\
0672     FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
0673 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\
0674     FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
0675
0676 /*      SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */
0677 #define SD10G_LANE_LANE_48(t)     __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 0, 0, 1, 4)
0678
0679 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0      GENMASK(3, 0)
0680 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\
0681     FIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
0682 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\
0683     FIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
0684
0685 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL      BIT(4)
0686 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\
0687     FIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
0688 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\
0689     FIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
0690
0691 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ           BIT(5)
0692 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\
0693     FIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
0694 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\
0695     FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
0696
0697 /*      SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */
0698 #define SD10G_LANE_LANE_50(t)     __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 32, 0, 1, 4)
0699
0700 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0   GENMASK(1, 0)
0701 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\
0702     FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
0703 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\
0704     FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
0705
0706 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB        BIT(4)
0707 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\
0708     FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
0709 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\
0710     FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
0711
0712 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL   BIT(5)
0713 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\
0714     FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
0715 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\
0716     FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
0717
0718 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL      BIT(6)
0719 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\
0720     FIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
0721 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\
0722     FIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
0723
0724 #define SD10G_LANE_LANE_50_CFG_JT_EN             BIT(7)
0725 #define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\
0726     FIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x)
0727 #define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\
0728     FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x)
0729
0730 /*      SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */
0731 #define SD10G_LANE_LANE_52(t)     __REG(TARGET_SD10G_LANE, t, 12, 328, 0, 1, 24, 0, 0, 1, 4)
0732
0733 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0)
0734 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\
0735     FIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
0736 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\
0737     FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
0738
0739 /*      SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */
0740 #define SD10G_LANE_LANE_83(t)     __REG(TARGET_SD10G_LANE, t, 12, 464, 0, 1, 112, 60, 0, 1, 4)
0741
0742 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE      BIT(0)
0743 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\
0744     FIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
0745 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\
0746     FIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
0747
0748 #define SD10G_LANE_LANE_83_R_TX_POL_INV          BIT(1)
0749 #define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\
0750     FIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
0751 #define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\
0752     FIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
0753
0754 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE      BIT(2)
0755 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\
0756     FIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
0757 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\
0758     FIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
0759
0760 #define SD10G_LANE_LANE_83_R_RX_POL_INV          BIT(3)
0761 #define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\
0762     FIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
0763 #define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\
0764     FIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
0765
0766 #define SD10G_LANE_LANE_83_R_DFE_RSTN            BIT(4)
0767 #define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\
0768     FIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
0769 #define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\
0770     FIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
0771
0772 #define SD10G_LANE_LANE_83_R_CDR_RSTN            BIT(5)
0773 #define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\
0774     FIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
0775 #define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\
0776     FIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
0777
0778 #define SD10G_LANE_LANE_83_R_CTLE_RSTN           BIT(6)
0779 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\
0780     FIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
0781 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\
0782     FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
0783
0784 /*      SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */
0785 #define SD10G_LANE_LANE_93(t)     __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 12, 0, 1, 4)
0786
0787 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN    BIT(0)
0788 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\
0789     FIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
0790 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\
0791     FIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
0792
0793 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1)
0794 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\
0795     FIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
0796 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\
0797     FIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
0798
0799 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE     BIT(2)
0800 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\
0801     FIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
0802 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\
0803     FIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
0804
0805 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL     BIT(3)
0806 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\
0807     FIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
0808 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\
0809     FIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
0810
0811 #define SD10G_LANE_LANE_93_R_REG_MANUAL          BIT(4)
0812 #define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\
0813     FIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
0814 #define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\
0815     FIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
0816
0817 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT   BIT(5)
0818 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\
0819     FIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
0820 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\
0821     FIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
0822
0823 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT    BIT(6)
0824 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\
0825     FIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
0826 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\
0827     FIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
0828
0829 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7)
0830 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\
0831     FIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
0832 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\
0833     FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
0834
0835 /*      SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */
0836 #define SD10G_LANE_LANE_94(t)     __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 16, 0, 1, 4)
0837
0838 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0      GENMASK(2, 0)
0839 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\
0840     FIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
0841 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\
0842     FIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
0843
0844 #define SD10G_LANE_LANE_94_R_ISCAN_REG           BIT(4)
0845 #define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\
0846     FIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
0847 #define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\
0848     FIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
0849
0850 #define SD10G_LANE_LANE_94_R_TXEQ_REG            BIT(5)
0851 #define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\
0852     FIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
0853 #define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\
0854     FIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
0855
0856 #define SD10G_LANE_LANE_94_R_MISC_REG            BIT(6)
0857 #define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\
0858     FIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x)
0859 #define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\
0860     FIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x)
0861
0862 #define SD10G_LANE_LANE_94_R_SWING_REG           BIT(7)
0863 #define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\
0864     FIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x)
0865 #define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\
0866     FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x)
0867
0868 /*      SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */
0869 #define SD10G_LANE_LANE_9E(t)     __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 56, 0, 1, 4)
0870
0871 #define SD10G_LANE_LANE_9E_R_RXEQ_REG            BIT(0)
0872 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\
0873     FIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
0874 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\
0875     FIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
0876
0877 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1)
0878 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\
0879     FIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
0880 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\
0881     FIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
0882
0883 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN    BIT(2)
0884 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\
0885     FIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
0886 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\
0887     FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
0888
0889 /*      SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */
0890 #define SD10G_LANE_LANE_A1(t)     __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 4, 0, 1, 4)
0891
0892 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)
0893 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\
0894     FIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
0895 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\
0896     FIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
0897
0898 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT        BIT(4)
0899 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\
0900     FIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
0901 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\
0902     FIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
0903
0904 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT        BIT(5)
0905 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\
0906     FIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
0907 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\
0908     FIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
0909
0910 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6)
0911 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\
0912     FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
0913 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\
0914     FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
0915
0916 #define SD10G_LANE_LANE_A1_R_PCLK_GATING         BIT(7)
0917 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\
0918     FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
0919 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\
0920     FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
0921
0922 /*      SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */
0923 #define SD10G_LANE_LANE_A2(t)     __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 8, 0, 1, 4)
0924
0925 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)
0926 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\
0927     FIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
0928 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\
0929     FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
0930
0931 /*      SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */
0932 #define SD10G_LANE_LANE_DF(t)     __REG(TARGET_SD10G_LANE, t, 12, 832, 0, 1, 84, 60, 0, 1, 4)
0933
0934 #define SD10G_LANE_LANE_DF_LOL_UDL               BIT(0)
0935 #define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\
0936     FIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x)
0937 #define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\
0938     FIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x)
0939
0940 #define SD10G_LANE_LANE_DF_LOL                   BIT(1)
0941 #define SD10G_LANE_LANE_DF_LOL_SET(x)\
0942     FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)
0943 #define SD10G_LANE_LANE_DF_LOL_GET(x)\
0944     FIELD_GET(SD10G_LANE_LANE_DF_LOL, x)
0945
0946 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)
0947 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
0948     FIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
0949 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
0950     FIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
0951
0952 #define SD10G_LANE_LANE_DF_SQUELCH               BIT(3)
0953 #define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\
0954     FIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x)
0955 #define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\
0956     FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x)
0957
0958 /*      SD25G_TARGET:CMU_GRP_0:CMU_09 */
0959 #define SD25G_LANE_CMU_09(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)
0960
0961 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN      BIT(0)
0962 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\
0963     FIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
0964 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\
0965     FIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
0966
0967 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY           BIT(1)
0968 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\
0969     FIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
0970 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\
0971     FIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
0972
0973 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET        BIT(2)
0974 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\
0975     FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
0976 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\
0977     FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
0978
0979 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD      BIT(3)
0980 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\
0981     FIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
0982 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\
0983     FIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
0984
0985 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0     GENMASK(5, 4)
0986 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\
0987     FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
0988 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\
0989     FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
0990
0991 /*      SD25G_TARGET:CMU_GRP_0:CMU_0B */
0992 #define SD25G_LANE_CMU_0B(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)
0993
0994 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT      BIT(0)
0995 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\
0996     FIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
0997 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\
0998     FIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
0999
1000 #define SD25G_LANE_CMU_0B_CFG_DISLOL             BIT(1)
1001 #define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\
1002     FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
1003 #define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\
1004     FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
1005
1006 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN BIT(2)
1007 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\
1008     FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
1009 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\
1010     FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
1011
1012 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN     BIT(3)
1013 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\
1014     FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
1015 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\
1016     FIELD_GET(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
1017
1018 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD          BIT(4)
1019 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\
1020     FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
1021 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\
1022     FIELD_GET(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
1023
1024 #define SD25G_LANE_CMU_0B_CFG_DISLOS             BIT(5)
1025 #define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\
1026     FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
1027 #define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\
1028     FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
1029
1030 #define SD25G_LANE_CMU_0B_CFG_DCLOL              BIT(6)
1031 #define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\
1032     FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
1033 #define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\
1034     FIELD_GET(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
1035
1036 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN    BIT(7)
1037 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\
1038     FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
1039 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\
1040     FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
1041
1042 /*      SD25G_TARGET:CMU_GRP_0:CMU_0C */
1043 #define SD25G_LANE_CMU_0C(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4)
1044
1045 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET        BIT(0)
1046 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\
1047     FIELD_PREP(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
1048 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\
1049     FIELD_GET(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
1050
1051 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN        BIT(1)
1052 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\
1053     FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
1054 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\
1055     FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
1056
1057 #define SD25G_LANE_CMU_0C_CFG_VCO_PD             BIT(2)
1058 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\
1059     FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
1060 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\
1061     FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
1062
1063 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP        BIT(3)
1064 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\
1065     FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
1066 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\
1067     FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
1068
1069 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0   GENMASK(5, 4)
1070 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\
1071     FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
1072 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\
1073     FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
1074
1075 /*      SD25G_TARGET:CMU_GRP_0:CMU_0D */
1076 #define SD25G_LANE_CMU_0D(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4)
1077
1078 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD         BIT(0)
1079 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\
1080     FIELD_PREP(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
1081 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\
1082     FIELD_GET(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
1083
1084 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN        BIT(1)
1085 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\
1086     FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
1087 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\
1088     FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
1089
1090 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP        BIT(2)
1091 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\
1092     FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
1093 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\
1094     FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
1095
1096 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP        BIT(3)
1097 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\
1098     FIELD_PREP(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
1099 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\
1100     FIELD_GET(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
1101
1102 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0     GENMASK(5, 4)
1103 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\
1104     FIELD_PREP(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
1105 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\
1106     FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
1107
1108 /*      SD25G_TARGET:CMU_GRP_0:CMU_0E */
1109 #define SD25G_LANE_CMU_0E(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4)
1110
1111 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0        GENMASK(3, 0)
1112 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\
1113     FIELD_PREP(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
1114 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\
1115     FIELD_GET(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
1116
1117 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD   BIT(4)
1118 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\
1119     FIELD_PREP(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
1120 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\
1121     FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
1122
1123 /*      SD25G_TARGET:CMU_GRP_0:CMU_13 */
1124 #define SD25G_LANE_CMU_13(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4)
1125
1126 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0    GENMASK(3, 0)
1127 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\
1128     FIELD_PREP(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
1129 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\
1130     FIELD_GET(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
1131
1132 #define SD25G_LANE_CMU_13_CFG_JT_EN              BIT(4)
1133 #define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\
1134     FIELD_PREP(SD25G_LANE_CMU_13_CFG_JT_EN, x)
1135 #define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\
1136     FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x)
1137
1138 /*      SD25G_TARGET:CMU_GRP_0:CMU_18 */
1139 #define SD25G_LANE_CMU_18(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4)
1140
1141 #define SD25G_LANE_CMU_18_R_PLL_RSTN             BIT(0)
1142 #define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\
1143     FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
1144 #define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\
1145     FIELD_GET(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
1146
1147 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET          BIT(1)
1148 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\
1149     FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
1150 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\
1151     FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
1152
1153 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET          BIT(2)
1154 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\
1155     FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
1156 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\
1157     FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
1158
1159 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0       GENMASK(5, 4)
1160 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\
1161     FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
1162 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\
1163     FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
1164
1165 /*      SD25G_TARGET:CMU_GRP_0:CMU_19 */
1166 #define SD25G_LANE_CMU_19(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4)
1167
1168 #define SD25G_LANE_CMU_19_R_CK_RESETB            BIT(0)
1169 #define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\
1170     FIELD_PREP(SD25G_LANE_CMU_19_R_CK_RESETB, x)
1171 #define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\
1172     FIELD_GET(SD25G_LANE_CMU_19_R_CK_RESETB, x)
1173
1174 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN          BIT(1)
1175 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\
1176     FIELD_PREP(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
1177 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\
1178     FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
1179
1180 /*      SD25G_TARGET:CMU_GRP_0:CMU_1A */
1181 #define SD25G_LANE_CMU_1A(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4)
1182
1183 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0       GENMASK(2, 0)
1184 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\
1185     FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
1186 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\
1187     FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
1188
1189 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT  BIT(4)
1190 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\
1191     FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
1192 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\
1193     FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
1194
1195 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE       BIT(5)
1196 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\
1197     FIELD_PREP(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
1198 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\
1199     FIELD_GET(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
1200
1201 #define SD25G_LANE_CMU_1A_R_REG_MANUAL           BIT(6)
1202 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\
1203     FIELD_PREP(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
1204 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\
1205     FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
1206
1207 /*      SD25G_TARGET:CMU_GRP_1:CMU_2A */
1208 #define SD25G_LANE_CMU_2A(t)      __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4)
1209
1210 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0          GENMASK(1, 0)
1211 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\
1212     FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
1213 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\
1214     FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
1215
1216 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE        BIT(4)
1217 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\
1218     FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
1219 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\
1220     FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
1221
1222 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS       BIT(5)
1223 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\
1224     FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
1225 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\
1226     FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
1227
1228 /*      SD25G_TARGET:CMU_GRP_1:CMU_30 */
1229 #define SD25G_LANE_CMU_30(t)      __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4)
1230
1231 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0)
1232 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\
1233     FIELD_PREP(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
1234 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\
1235     FIELD_GET(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
1236
1237 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4)
1238 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\
1239     FIELD_PREP(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
1240 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\
1241     FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
1242
1243 /*      SD25G_TARGET:CMU_GRP_1:CMU_31 */
1244 #define SD25G_LANE_CMU_31(t)      __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4)
1245
1246 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0)
1247 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\
1248     FIELD_PREP(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
1249 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\
1250     FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
1251
1252 /*      SD25G_TARGET:CMU_GRP_2:CMU_40 */
1253 #define SD25G_LANE_CMU_40(t)      __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4)
1254
1255 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL     BIT(0)
1256 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\
1257     FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
1258 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\
1259     FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
1260
1261 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD      BIT(1)
1262 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\
1263     FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
1264 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\
1265     FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
1266
1267 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK          BIT(2)
1268 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\
1269     FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
1270 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\
1271     FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
1272
1273 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN        BIT(3)
1274 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\
1275     FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
1276 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\
1277     FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
1278
1279 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN    BIT(4)
1280 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\
1281     FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
1282 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\
1283     FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
1284
1285 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST       BIT(5)
1286 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\
1287     FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
1288 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\
1289     FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
1290
1291 /*      SD25G_TARGET:CMU_GRP_2:CMU_45 */
1292 #define SD25G_LANE_CMU_45(t)      __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4)
1293
1294 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0  GENMASK(7, 0)
1295 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\
1296     FIELD_PREP(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
1297 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\
1298     FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
1299
1300 /*      SD25G_TARGET:CMU_GRP_2:CMU_46 */
1301 #define SD25G_LANE_CMU_46(t)      __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4)
1302
1303 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0)
1304 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\
1305     FIELD_PREP(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
1306 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\
1307     FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
1308
1309 /*      SD25G_TARGET:CMU_GRP_3:CMU_C0 */
1310 #define SD25G_LANE_CMU_C0(t)      __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4)
1311
1312 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0     GENMASK(3, 0)
1313 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\
1314     FIELD_PREP(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
1315 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\
1316     FIELD_GET(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
1317
1318 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL            BIT(4)
1319 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\
1320     FIELD_PREP(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
1321 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\
1322     FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
1323
1324 /*      SD25G_TARGET:CMU_GRP_4:CMU_FF */
1325 #define SD25G_LANE_CMU_FF(t)      __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4)
1326
1327 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX   GENMASK(7, 0)
1328 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\
1329     FIELD_PREP(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
1330 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\
1331     FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
1332
1333 /*      SD25G_TARGET:LANE_GRP_0:LANE_00 */
1334 #define SD25G_LANE_LANE_00(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4)
1335
1336 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0)
1337 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\
1338     FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
1339 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\
1340     FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
1341
1342 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
1343 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\
1344     FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
1345 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\
1346     FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
1347
1348 /*      SD25G_TARGET:LANE_GRP_0:LANE_01 */
1349 #define SD25G_LANE_LANE_01(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4)
1350
1351 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)
1352 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
1353     FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
1354 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
1355     FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
1356
1357 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0  GENMASK(5, 4)
1358 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\
1359     FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
1360 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\
1361     FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
1362
1363 /*      SD25G_TARGET:LANE_GRP_0:LANE_03 */
1364 #define SD25G_LANE_LANE_03(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4)
1365
1366 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0    GENMASK(4, 0)
1367 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\
1368     FIELD_PREP(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
1369 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\
1370     FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
1371
1372 /*      SD25G_TARGET:LANE_GRP_0:LANE_04 */
1373 #define SD25G_LANE_LANE_04(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4)
1374
1375 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN    BIT(0)
1376 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\
1377     FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
1378 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\
1379     FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
1380
1381 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN    BIT(1)
1382 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\
1383     FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
1384 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\
1385     FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
1386
1387 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML         BIT(2)
1388 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\
1389     FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
1390 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\
1391     FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
1392
1393 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK         BIT(3)
1394 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\
1395     FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
1396 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\
1397     FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
1398
1399 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER      BIT(4)
1400 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\
1401     FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
1402 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\
1403     FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
1404
1405 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN       BIT(5)
1406 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\
1407     FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
1408 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\
1409     FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
1410
1411 /*      SD25G_TARGET:LANE_GRP_0:LANE_05 */
1412 #define SD25G_LANE_LANE_05(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4)
1413
1414 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0   GENMASK(3, 0)
1415 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\
1416     FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
1417 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\
1418     FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
1419
1420 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0         GENMASK(5, 4)
1421 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\
1422     FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
1423 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\
1424     FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
1425
1426 /*      SD25G_TARGET:LANE_GRP_0:LANE_06 */
1427 #define SD25G_LANE_LANE_06(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4)
1428
1429 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN        BIT(0)
1430 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\
1431     FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
1432 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\
1433     FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
1434
1435 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0    GENMASK(7, 4)
1436 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\
1437     FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
1438 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\
1439     FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
1440
1441 /*      SD25G_TARGET:LANE_GRP_0:LANE_07 */
1442 #define SD25G_LANE_LANE_07(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4)
1443
1444 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV         BIT(0)
1445 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\
1446     FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
1447 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\
1448     FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
1449
1450 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2        BIT(1)
1451 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\
1452     FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
1453 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\
1454     FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
1455
1456 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY         BIT(2)
1457 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\
1458     FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
1459 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\
1460     FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
1461
1462 /*      SD25G_TARGET:LANE_GRP_0:LANE_09 */
1463 #define SD25G_LANE_LANE_09(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4)
1464
1465 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0)
1466 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\
1467     FIELD_PREP(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
1468 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\
1469     FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
1470
1471 /*      SD25G_TARGET:LANE_GRP_0:LANE_0A */
1472 #define SD25G_LANE_LANE_0A(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4)
1473
1474 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0)
1475 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\
1476     FIELD_PREP(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
1477 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\
1478     FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
1479
1480 /*      SD25G_TARGET:LANE_GRP_0:LANE_0B */
1481 #define SD25G_LANE_LANE_0B(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4)
1482
1483 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN   BIT(0)
1484 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\
1485     FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
1486 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\
1487     FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
1488
1489 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST      BIT(1)
1490 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\
1491     FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
1492 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\
1493     FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
1494
1495 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0   GENMASK(5, 4)
1496 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\
1497     FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
1498 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\
1499     FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
1500
1501 /*      SD25G_TARGET:LANE_GRP_0:LANE_0C */
1502 #define SD25G_LANE_LANE_0C(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4)
1503
1504 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
1505 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
1506     FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
1507 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
1508     FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
1509
1510 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN       BIT(4)
1511 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\
1512     FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
1513 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\
1514     FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
1515
1516 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD      BIT(5)
1517 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\
1518     FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
1519 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\
1520     FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
1521
1522 /*      SD25G_TARGET:LANE_GRP_0:LANE_0D */
1523 #define SD25G_LANE_LANE_0D(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4)
1524
1525 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0     GENMASK(2, 0)
1526 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\
1527     FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
1528 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\
1529     FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
1530
1531 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8    BIT(4)
1532 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\
1533     FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
1534 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\
1535     FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
1536
1537 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN      BIT(5)
1538 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\
1539     FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
1540 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\
1541     FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
1542
1543 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD        BIT(6)
1544 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\
1545     FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
1546 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\
1547     FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
1548
1549 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN       BIT(7)
1550 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\
1551     FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
1552 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\
1553     FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
1554
1555 /*      SD25G_TARGET:LANE_GRP_0:LANE_0E */
1556 #define SD25G_LANE_LANE_0E(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4)
1557
1558 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN       BIT(0)
1559 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\
1560     FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
1561 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\
1562     FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
1563
1564 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD    BIT(1)
1565 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\
1566     FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
1567 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\
1568     FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
1569
1570 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG      BIT(2)
1571 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\
1572     FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
1573 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\
1574     FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
1575
1576 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0   GENMASK(6, 4)
1577 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\
1578     FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
1579 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\
1580     FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
1581
1582 /*      SD25G_TARGET:LANE_GRP_0:LANE_0F */
1583 #define SD25G_LANE_LANE_0F(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4)
1584
1585 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1  GENMASK(4, 0)
1586 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\
1587     FIELD_PREP(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
1588 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\
1589     FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
1590
1591 /*      SD25G_TARGET:LANE_GRP_0:LANE_18 */
1592 #define SD25G_LANE_LANE_18(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4)
1593
1594 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN       BIT(0)
1595 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\
1596     FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
1597 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\
1598     FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
1599
1600 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT       BIT(1)
1601 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\
1602     FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
1603 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\
1604     FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
1605
1606 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN    BIT(2)
1607 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\
1608     FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
1609 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\
1610     FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
1611
1612 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD      BIT(3)
1613 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\
1614     FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
1615 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\
1616     FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
1617
1618 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0  GENMASK(6, 4)
1619 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\
1620     FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
1621 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\
1622     FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
1623
1624 /*      SD25G_TARGET:LANE_GRP_0:LANE_19 */
1625 #define SD25G_LANE_LANE_19(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4)
1626
1627 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD        BIT(0)
1628 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\
1629     FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
1630 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\
1631     FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
1632
1633 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD        BIT(1)
1634 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\
1635     FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
1636 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\
1637     FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
1638
1639 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL      BIT(2)
1640 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\
1641     FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
1642 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\
1643     FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
1644
1645 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN        BIT(3)
1646 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\
1647     FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
1648 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\
1649     FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
1650
1651 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU      BIT(4)
1652 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\
1653     FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
1654 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\
1655     FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
1656
1657 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP     BIT(5)
1658 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\
1659     FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
1660 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\
1661     FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
1662
1663 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET     BIT(6)
1664 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\
1665     FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
1666 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\
1667     FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
1668
1669 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE        BIT(7)
1670 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\
1671     FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
1672 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\
1673     FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
1674
1675 /*      SD25G_TARGET:LANE_GRP_0:LANE_1A */
1676 #define SD25G_LANE_LANE_1A(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4)
1677
1678 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN     BIT(0)
1679 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\
1680     FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
1681 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\
1682     FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
1683
1684 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0     GENMASK(6, 4)
1685 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\
1686     FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
1687 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\
1688     FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
1689
1690 /*      SD25G_TARGET:LANE_GRP_0:LANE_1B */
1691 #define SD25G_LANE_LANE_1B(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4)
1692
1693 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0      GENMASK(7, 0)
1694 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\
1695     FIELD_PREP(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
1696 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\
1697     FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
1698
1699 /*      SD25G_TARGET:LANE_GRP_0:LANE_1C */
1700 #define SD25G_LANE_LANE_1C(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4)
1701
1702 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN       BIT(0)
1703 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\
1704     FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
1705 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\
1706     FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
1707
1708 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD         BIT(1)
1709 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\
1710     FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
1711 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\
1712     FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
1713
1714 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD      BIT(2)
1715 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\
1716     FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
1717 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\
1718     FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
1719
1720 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0  GENMASK(7, 4)
1721 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\
1722     FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
1723 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\
1724     FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
1725
1726 /*      SD25G_TARGET:LANE_GRP_0:LANE_1D */
1727 #define SD25G_LANE_LANE_1D(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4)
1728
1729 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR  BIT(0)
1730 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\
1731     FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
1732 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\
1733     FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
1734
1735 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD     BIT(1)
1736 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\
1737     FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
1738 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\
1739     FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
1740
1741 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN     BIT(2)
1742 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\
1743     FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
1744 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\
1745     FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
1746
1747 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP   BIT(3)
1748 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\
1749     FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
1750 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\
1751     FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
1752
1753 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T        BIT(4)
1754 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\
1755     FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
1756 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\
1757     FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
1758
1759 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN      BIT(5)
1760 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\
1761     FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
1762 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\
1763     FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
1764
1765 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR     BIT(6)
1766 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\
1767     FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
1768 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\
1769     FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
1770
1771 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD        BIT(7)
1772 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\
1773     FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
1774 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\
1775     FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
1776
1777 /*      SD25G_TARGET:LANE_GRP_0:LANE_1E */
1778 #define SD25G_LANE_LANE_1E(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4)
1779
1780 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0   GENMASK(1, 0)
1781 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\
1782     FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
1783 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\
1784     FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
1785
1786 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN        BIT(4)
1787 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\
1788     FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
1789 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\
1790     FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
1791
1792 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN   BIT(5)
1793 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\
1794     FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
1795 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\
1796     FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
1797
1798 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR   BIT(6)
1799 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\
1800     FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
1801 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\
1802     FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
1803
1804 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD     BIT(7)
1805 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\
1806     FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
1807 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\
1808     FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
1809
1810 /*      SD25G_TARGET:LANE_GRP_0:LANE_21 */
1811 #define SD25G_LANE_LANE_21(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4)
1812
1813 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0)
1814 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\
1815     FIELD_PREP(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
1816 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\
1817     FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
1818
1819 /*      SD25G_TARGET:LANE_GRP_0:LANE_22 */
1820 #define SD25G_LANE_LANE_22(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4)
1821
1822 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0  GENMASK(3, 0)
1823 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\
1824     FIELD_PREP(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
1825 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\
1826     FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
1827
1828 /*      SD25G_TARGET:LANE_GRP_0:LANE_25 */
1829 #define SD25G_LANE_LANE_25(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4)
1830
1831 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0)
1832 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\
1833     FIELD_PREP(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
1834 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\
1835     FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
1836
1837 /*      SD25G_TARGET:LANE_GRP_0:LANE_26 */
1838 #define SD25G_LANE_LANE_26(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4)
1839
1840 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0)
1841 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\
1842     FIELD_PREP(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
1843 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\
1844     FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
1845
1846 /*      SD25G_TARGET:LANE_GRP_0:LANE_28 */
1847 #define SD25G_LANE_LANE_28(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4)
1848
1849 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN  BIT(0)
1850 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\
1851     FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
1852 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\
1853     FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
1854
1855 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH      BIT(1)
1856 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\
1857     FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
1858 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\
1859     FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
1860
1861 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL   BIT(2)
1862 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\
1863     FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
1864 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\
1865     FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
1866
1867 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0 GENMASK(6, 4)
1868 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\
1869     FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
1870 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\
1871     FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
1872
1873 /*      SD25G_TARGET:LANE_GRP_0:LANE_2B */
1874 #define SD25G_LANE_LANE_2B(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4)
1875
1876 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0      GENMASK(3, 0)
1877 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\
1878     FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
1879 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\
1880     FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
1881
1882 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR BIT(4)
1883 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\
1884     FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
1885 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\
1886     FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
1887
1888 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU    BIT(5)
1889 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\
1890     FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
1891 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\
1892     FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
1893
1894 /*      SD25G_TARGET:LANE_GRP_0:LANE_2C */
1895 #define SD25G_LANE_LANE_2C(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4)
1896
1897 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0)
1898 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\
1899     FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
1900 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\
1901     FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
1902
1903 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER   BIT(4)
1904 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\
1905     FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
1906 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\
1907     FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
1908
1909 /*      SD25G_TARGET:LANE_GRP_0:LANE_2D */
1910 #define SD25G_LANE_LANE_2D(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4)
1911
1912 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0   GENMASK(2, 0)
1913 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\
1914     FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
1915 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\
1916     FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
1917
1918 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0 GENMASK(6, 4)
1919 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\
1920     FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
1921 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\
1922     FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
1923
1924 /*      SD25G_TARGET:LANE_GRP_0:LANE_2E */
1925 #define SD25G_LANE_LANE_2E(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4)
1926
1927 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN  BIT(0)
1928 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\
1929     FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
1930 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\
1931     FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
1932
1933 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ         BIT(1)
1934 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\
1935     FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
1936 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\
1937     FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
1938
1939 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ          BIT(2)
1940 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\
1941     FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
1942 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\
1943     FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
1944
1945 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS       BIT(3)
1946 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\
1947     FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
1948 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\
1949     FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
1950
1951 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC     BIT(4)
1952 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\
1953     FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
1954 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\
1955     FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
1956
1957 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG    BIT(5)
1958 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\
1959     FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
1960 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\
1961     FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
1962
1963 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN        BIT(6)
1964 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\
1965     FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
1966 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\
1967     FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
1968
1969 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN      BIT(7)
1970 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\
1971     FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
1972 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\
1973     FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
1974
1975 /*      SD25G_TARGET:LANE_GRP_0:LANE_40 */
1976 #define SD25G_LANE_LANE_40(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4)
1977
1978 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE   BIT(0)
1979 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\
1980     FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
1981 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\
1982     FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
1983
1984 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV       BIT(1)
1985 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\
1986     FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
1987 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\
1988     FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
1989
1990 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE   BIT(2)
1991 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\
1992     FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
1993 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\
1994     FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
1995
1996 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV       BIT(3)
1997 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\
1998     FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
1999 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\
2000     FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
2001
2002 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN         BIT(4)
2003 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\
2004     FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
2005 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\
2006     FIELD_GET(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
2007
2008 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN         BIT(5)
2009 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\
2010     FIELD_PREP(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
2011 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\
2012     FIELD_GET(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
2013
2014 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN        BIT(6)
2015 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\
2016     FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
2017 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\
2018     FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
2019
2020 /*      SD25G_TARGET:LANE_GRP_0:LANE_42 */
2021 #define SD25G_LANE_LANE_42(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4)
2022
2023 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0)
2024 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\
2025     FIELD_PREP(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
2026 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\
2027     FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
2028
2029 /*      SD25G_TARGET:LANE_GRP_0:LANE_43 */
2030 #define SD25G_LANE_LANE_43(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4)
2031
2032 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0)
2033 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\
2034     FIELD_PREP(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
2035 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\
2036     FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
2037
2038 /*      SD25G_TARGET:LANE_GRP_0:LANE_44 */
2039 #define SD25G_LANE_LANE_44(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4)
2040
2041 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0)
2042 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\
2043     FIELD_PREP(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
2044 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\
2045     FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
2046
2047 /*      SD25G_TARGET:LANE_GRP_0:LANE_45 */
2048 #define SD25G_LANE_LANE_45(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4)
2049
2050 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0)
2051 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\
2052     FIELD_PREP(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
2053 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\
2054     FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
2055
2056 /*      SD25G_TARGET:LANE_GRP_1:LANE_DE */
2057 #define SD25G_LANE_LANE_DE(t)     __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4)
2058
2059 #define SD25G_LANE_LANE_DE_LN_LOL_UDL            BIT(0)
2060 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\
2061     FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
2062 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\
2063     FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
2064
2065 #define SD25G_LANE_LANE_DE_LN_LOL                BIT(1)
2066 #define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\
2067     FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL, x)
2068 #define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\
2069     FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL, x)
2070
2071 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED BIT(2)
2072 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\
2073     FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
2074 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\
2075     FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
2076
2077 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI           BIT(3)
2078 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\
2079     FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
2080 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\
2081     FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
2082
2083 /*      SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */
2084 #define SD6G_LANE_LANE_DF(t)      __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4)
2085
2086 #define SD6G_LANE_LANE_DF_LOL_UDL                BIT(0)
2087 #define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\
2088     FIELD_PREP(SD6G_LANE_LANE_DF_LOL_UDL, x)
2089 #define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\
2090     FIELD_GET(SD6G_LANE_LANE_DF_LOL_UDL, x)
2091
2092 #define SD6G_LANE_LANE_DF_LOL                    BIT(1)
2093 #define SD6G_LANE_LANE_DF_LOL_SET(x)\
2094     FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)
2095 #define SD6G_LANE_LANE_DF_LOL_GET(x)\
2096     FIELD_GET(SD6G_LANE_LANE_DF_LOL, x)
2097
2098 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED  BIT(2)
2099 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
2100     FIELD_PREP(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
2101 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
2102     FIELD_GET(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
2103
2104 #define SD6G_LANE_LANE_DF_SQUELCH                BIT(3)
2105 #define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\
2106     FIELD_PREP(SD6G_LANE_LANE_DF_SQUELCH, x)
2107 #define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\
2108     FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x)
2109
2110 /*      SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */
2111 #define SD_CMU_CMU_00(t)          __REG(TARGET_SD_CMU, t, 14, 0, 0, 1, 20, 0, 0, 1, 4)
2112
2113 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE      BIT(0)
2114 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\
2115     FIELD_PREP(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
2116 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\
2117     FIELD_GET(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
2118
2119 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET            BIT(1)
2120 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\
2121     FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
2122 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\
2123     FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
2124
2125 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET            BIT(2)
2126 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\
2127     FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
2128 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\
2129     FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
2130
2131 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0         GENMASK(5, 4)
2132 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\
2133     FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
2134 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\
2135     FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
2136
2137 /*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */
2138 #define SD_CMU_CMU_05(t)          __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 0, 0, 1, 4)
2139
2140 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN          BIT(0)
2141 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\
2142     FIELD_PREP(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
2143 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\
2144     FIELD_GET(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
2145
2146 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0        GENMASK(5, 4)
2147 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\
2148     FIELD_PREP(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
2149 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\
2150     FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
2151
2152 /*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */
2153 #define SD_CMU_CMU_09(t)          __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 16, 0, 1, 4)
2154
2155 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP            BIT(0)
2156 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\
2157     FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
2158 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\
2159     FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
2160
2161 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN            BIT(1)
2162 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\
2163     FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
2164 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\
2165     FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
2166
2167 #define SD_CMU_CMU_09_CFG_SW_8G                  BIT(4)
2168 #define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\
2169     FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)
2170 #define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\
2171     FIELD_GET(SD_CMU_CMU_09_CFG_SW_8G, x)
2172
2173 #define SD_CMU_CMU_09_CFG_SW_10G                 BIT(5)
2174 #define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\
2175     FIELD_PREP(SD_CMU_CMU_09_CFG_SW_10G, x)
2176 #define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\
2177     FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x)
2178
2179 /*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */
2180 #define SD_CMU_CMU_0D(t)          __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 32, 0, 1, 4)
2181
2182 #define SD_CMU_CMU_0D_CFG_PD_DIV64               BIT(0)
2183 #define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\
2184     FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
2185 #define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\
2186     FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
2187
2188 #define SD_CMU_CMU_0D_CFG_PD_DIV66               BIT(1)
2189 #define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\
2190     FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
2191 #define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\
2192     FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
2193
2194 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD           BIT(2)
2195 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\
2196     FIELD_PREP(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
2197 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\
2198     FIELD_GET(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
2199
2200 #define SD_CMU_CMU_0D_CFG_JC_BYP                 BIT(3)
2201 #define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\
2202     FIELD_PREP(SD_CMU_CMU_0D_CFG_JC_BYP, x)
2203 #define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\
2204     FIELD_GET(SD_CMU_CMU_0D_CFG_JC_BYP, x)
2205
2206 #define SD_CMU_CMU_0D_CFG_REFCK_PD               BIT(4)
2207 #define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\
2208     FIELD_PREP(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
2209 #define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\
2210     FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
2211
2212 /*      SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */
2213 #define SD_CMU_CMU_1B(t)          __REG(TARGET_SD_CMU, t, 14, 104, 0, 1, 20, 4, 0, 1, 4)
2214
2215 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0            GENMASK(7, 0)
2216 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\
2217     FIELD_PREP(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
2218 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\
2219     FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
2220
2221 /*      SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */
2222 #define SD_CMU_CMU_1F(t)          __REG(TARGET_SD_CMU, t, 14, 124, 0, 1, 68, 0, 0, 1, 4)
2223
2224 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN             BIT(0)
2225 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\
2226     FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
2227 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\
2228     FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
2229
2230 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN             BIT(1)
2231 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\
2232     FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
2233 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\
2234     FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
2235
2236 #define SD_CMU_CMU_1F_CFG_IC2IP_N                BIT(2)
2237 #define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\
2238     FIELD_PREP(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
2239 #define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\
2240     FIELD_GET(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
2241
2242 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL              BIT(3)
2243 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\
2244     FIELD_PREP(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
2245 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\
2246     FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
2247
2248 /*      SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */
2249 #define SD_CMU_CMU_30(t)          __REG(TARGET_SD_CMU, t, 14, 192, 0, 1, 72, 0, 0, 1, 4)
2250
2251 #define SD_CMU_CMU_30_R_PLL_DLOL_EN              BIT(0)
2252 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\
2253     FIELD_PREP(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
2254 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\
2255     FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
2256
2257 /*      SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */
2258 #define SD_CMU_CMU_44(t)          __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 8, 0, 1, 4)
2259
2260 #define SD_CMU_CMU_44_R_PLL_RSTN                 BIT(0)
2261 #define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\
2262     FIELD_PREP(SD_CMU_CMU_44_R_PLL_RSTN, x)
2263 #define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\
2264     FIELD_GET(SD_CMU_CMU_44_R_PLL_RSTN, x)
2265
2266 #define SD_CMU_CMU_44_R_CK_RESETB                BIT(1)
2267 #define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\
2268     FIELD_PREP(SD_CMU_CMU_44_R_CK_RESETB, x)
2269 #define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\
2270     FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x)
2271
2272 /*      SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */
2273 #define SD_CMU_CMU_45(t)          __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 12, 0, 1, 4)
2274
2275 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL          BIT(0)
2276 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\
2277     FIELD_PREP(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
2278 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\
2279     FIELD_GET(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
2280
2281 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT      BIT(1)
2282 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\
2283     FIELD_PREP(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
2284 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\
2285     FIELD_GET(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
2286
2287 #define SD_CMU_CMU_45_RESERVED                   BIT(2)
2288 #define SD_CMU_CMU_45_RESERVED_SET(x)\
2289     FIELD_PREP(SD_CMU_CMU_45_RESERVED, x)
2290 #define SD_CMU_CMU_45_RESERVED_GET(x)\
2291     FIELD_GET(SD_CMU_CMU_45_RESERVED, x)
2292
2293 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT    BIT(3)
2294 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\
2295     FIELD_PREP(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
2296 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\
2297     FIELD_GET(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
2298
2299 #define SD_CMU_CMU_45_RESERVED_2                 BIT(4)
2300 #define SD_CMU_CMU_45_RESERVED_2_SET(x)\
2301     FIELD_PREP(SD_CMU_CMU_45_RESERVED_2, x)
2302 #define SD_CMU_CMU_45_RESERVED_2_GET(x)\
2303     FIELD_GET(SD_CMU_CMU_45_RESERVED_2, x)
2304
2305 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT     BIT(5)
2306 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\
2307     FIELD_PREP(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
2308 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\
2309     FIELD_GET(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
2310
2311 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT         BIT(6)
2312 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\
2313     FIELD_PREP(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
2314 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\
2315     FIELD_GET(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
2316
2317 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN     BIT(7)
2318 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\
2319     FIELD_PREP(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
2320 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\
2321     FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
2322
2323 /*      SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */
2324 #define SD_CMU_CMU_47(t)          __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 20, 0, 1, 4)
2325
2326 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0      GENMASK(4, 0)
2327 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\
2328     FIELD_PREP(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
2329 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\
2330     FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
2331
2332 /*      SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */
2333 #define SD_CMU_CMU_E0(t)          __REG(TARGET_SD_CMU, t, 14, 896, 0, 1, 8, 0, 0, 1, 4)
2334
2335 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0         GENMASK(3, 0)
2336 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\
2337     FIELD_PREP(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
2338 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\
2339     FIELD_GET(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
2340
2341 #define SD_CMU_CMU_E0_PLL_LOL_UDL                BIT(4)
2342 #define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\
2343     FIELD_PREP(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
2344 #define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\
2345     FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
2346
2347 /*      SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */
2348 #define SD_CMU_CFG_SD_CMU_CFG(t)  __REG(TARGET_SD_CMU_CFG, t, 14, 0, 0, 1, 8, 0, 0, 1, 4)
2349
2350 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST            BIT(0)
2351 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\
2352     FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
2353 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\
2354     FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
2355
2356 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST        BIT(1)
2357 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\
2358     FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
2359 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\
2360     FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
2361
2362 /*      SD_LANE_TARGET:SD_RESET:SD_SER_RST */
2363 #define SD_LANE_SD_SER_RST(t)     __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 0, 0, 1, 4)
2364
2365 #define SD_LANE_SD_SER_RST_SER_RST               BIT(0)
2366 #define SD_LANE_SD_SER_RST_SER_RST_SET(x)\
2367     FIELD_PREP(SD_LANE_SD_SER_RST_SER_RST, x)
2368 #define SD_LANE_SD_SER_RST_SER_RST_GET(x)\
2369     FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x)
2370
2371 /*      SD_LANE_TARGET:SD_RESET:SD_DES_RST */
2372 #define SD_LANE_SD_DES_RST(t)     __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 4, 0, 1, 4)
2373
2374 #define SD_LANE_SD_DES_RST_DES_RST               BIT(0)
2375 #define SD_LANE_SD_DES_RST_DES_RST_SET(x)\
2376     FIELD_PREP(SD_LANE_SD_DES_RST_DES_RST, x)
2377 #define SD_LANE_SD_DES_RST_DES_RST_GET(x)\
2378     FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x)
2379
2380 /*      SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */
2381 #define SD_LANE_SD_LANE_CFG(t)    __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 0, 0, 1, 4)
2382
2383 #define SD_LANE_SD_LANE_CFG_MACRO_RST            BIT(0)
2384 #define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\
2385     FIELD_PREP(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
2386 #define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\
2387     FIELD_GET(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
2388
2389 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST          BIT(1)
2390 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
2391     FIELD_PREP(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
2392 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
2393     FIELD_GET(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
2394
2395 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL           GENMASK(5, 4)
2396 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\
2397     FIELD_PREP(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
2398 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\
2399     FIELD_GET(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
2400
2401 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL           GENMASK(7, 6)
2402 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\
2403     FIELD_PREP(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
2404 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\
2405     FIELD_GET(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
2406
2407 #define SD_LANE_SD_LANE_CFG_LANE_RST             BIT(8)
2408 #define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\
2409     FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RST, x)
2410 #define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\
2411     FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RST, x)
2412
2413 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST          BIT(9)
2414 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\
2415     FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
2416 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\
2417     FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
2418
2419 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST          BIT(10)
2420 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\
2421     FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
2422 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\
2423     FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
2424
2425 /*      SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */
2426 #define SD_LANE_SD_LANE_STAT(t)   __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 4, 0, 1, 4)
2427
2428 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE        BIT(0)
2429 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
2430     FIELD_PREP(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
2431 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
2432     FIELD_GET(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
2433
2434 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE        BIT(1)
2435 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\
2436     FIELD_PREP(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
2437 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\
2438     FIELD_GET(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
2439
2440 #define SD_LANE_SD_LANE_STAT_DBG_OBS             GENMASK(31, 16)
2441 #define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\
2442     FIELD_PREP(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
2443 #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\
2444     FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
2445
2446 /*      SD_LANE_TARGET:CFG_STAT_FX100:MISC */
2447 #define SD_LANE_MISC(t)           __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 0, 0, 1, 4)
2448
2449 #define SD_LANE_MISC_SD_125_RST_DIS              BIT(0)
2450 #define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\
2451     FIELD_PREP(SD_LANE_MISC_SD_125_RST_DIS, x)
2452 #define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\
2453     FIELD_GET(SD_LANE_MISC_SD_125_RST_DIS, x)
2454
2455 #define SD_LANE_MISC_RX_ENA                      BIT(1)
2456 #define SD_LANE_MISC_RX_ENA_SET(x)\
2457     FIELD_PREP(SD_LANE_MISC_RX_ENA, x)
2458 #define SD_LANE_MISC_RX_ENA_GET(x)\
2459     FIELD_GET(SD_LANE_MISC_RX_ENA, x)
2460
2461 #define SD_LANE_MISC_MUX_ENA                     BIT(2)
2462 #define SD_LANE_MISC_MUX_ENA_SET(x)\
2463     FIELD_PREP(SD_LANE_MISC_MUX_ENA, x)
2464 #define SD_LANE_MISC_MUX_ENA_GET(x)\
2465     FIELD_GET(SD_LANE_MISC_MUX_ENA, x)
2466
2467 #define SD_LANE_MISC_CORE_CLK_FREQ               GENMASK(5, 4)
2468 #define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\
2469     FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x)
2470 #define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\
2471     FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x)
2472
2473 /*      SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */
2474 #define SD_LANE_M_STAT_MISC(t)    __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 36, 0, 1, 4)
2475
2476 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0)
2477 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\
2478     FIELD_PREP(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
2479 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\
2480     FIELD_GET(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
2481
2482 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT           GENMASK(31, 24)
2483 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\
2484     FIELD_PREP(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
2485 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\
2486     FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
2487
2488 /*      SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */
2489 #define SD_LANE_25G_SD_SER_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4)
2490
2491 #define SD_LANE_25G_SD_SER_RST_SER_RST           BIT(0)
2492 #define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\
2493     FIELD_PREP(SD_LANE_25G_SD_SER_RST_SER_RST, x)
2494 #define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\
2495     FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x)
2496
2497 /*      SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */
2498 #define SD_LANE_25G_SD_DES_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4)
2499
2500 #define SD_LANE_25G_SD_DES_RST_DES_RST           BIT(0)
2501 #define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\
2502     FIELD_PREP(SD_LANE_25G_SD_DES_RST_DES_RST, x)
2503 #define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\
2504     FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x)
2505
2506 /*      SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */
2507 #define SD_LANE_25G_SD_LANE_CFG(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4)
2508
2509 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST        BIT(0)
2510 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\
2511     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
2512 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\
2513     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
2514
2515 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST      BIT(1)
2516 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
2517     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
2518 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
2519     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
2520
2521 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE BIT(4)
2522 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\
2523     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
2524 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\
2525     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
2526
2527 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE  GENMASK(7, 5)
2528 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\
2529     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
2530 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\
2531     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
2532
2533 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST         BIT(8)
2534 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\
2535     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
2536 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\
2537     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
2538
2539 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV       BIT(9)
2540 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\
2541     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
2542 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\
2543     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
2544
2545 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN      BIT(10)
2546 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\
2547     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
2548 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\
2549     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
2550
2551 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY       BIT(11)
2552 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\
2553     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
2554 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\
2555     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
2556
2557 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV      GENMASK(15, 12)
2558 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\
2559     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
2560 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\
2561     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
2562
2563 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN     BIT(16)
2564 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\
2565     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
2566 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\
2567     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
2568
2569 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY      GENMASK(21, 17)
2570 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\
2571     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
2572 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\
2573     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
2574
2575 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN     BIT(22)
2576 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\
2577     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
2578 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\
2579     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
2580
2581 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN BIT(23)
2582 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\
2583     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
2584 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\
2585     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
2586
2587 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING  BIT(24)
2588 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\
2589     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
2590 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\
2591     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
2592
2593 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI     BIT(25)
2594 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\
2595     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
2596 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\
2597     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
2598
2599 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN GENMASK(28, 26)
2600 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\
2601     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
2602 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\
2603     FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
2604
2605 /*      SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */
2606 #define SD_LANE_25G_SD_LANE_CFG2(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4)
2607
2608 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL  GENMASK(2, 0)
2609 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\
2610     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
2611 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\
2612     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
2613
2614 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL    GENMASK(5, 3)
2615 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\
2616     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
2617 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\
2618     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
2619
2620 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL   GENMASK(8, 6)
2621 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\
2622     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
2623 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\
2624     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
2625
2626 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED GENMASK(10, 9)
2627 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\
2628     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
2629 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\
2630     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
2631
2632 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV   GENMASK(13, 11)
2633 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\
2634     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
2635 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\
2636     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
2637
2638 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV   GENMASK(16, 14)
2639 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\
2640     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
2641 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\
2642     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
2643
2644 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL GENMASK(19, 17)
2645 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\
2646     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
2647 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\
2648     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
2649
2650 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV GENMASK(23, 20)
2651 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\
2652     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
2653 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\
2654     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
2655
2656 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL  GENMASK(25, 24)
2657 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\
2658     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
2659 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\
2660     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
2661
2662 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL      GENMASK(28, 26)
2663 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\
2664     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
2665 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\
2666     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
2667
2668 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL      GENMASK(31, 29)
2669 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\
2670     FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
2671 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\
2672     FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
2673
2674 /*      SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */
2675 #define SD_LANE_25G_SD_LANE_STAT(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4)
2676
2677 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE    BIT(0)
2678 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
2679     FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
2680 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
2681     FIELD_GET(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
2682
2683 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE   BIT(1)
2684 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\
2685     FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
2686 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\
2687     FIELD_GET(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
2688
2689 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS         GENMASK(31, 16)
2690 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\
2691     FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
2692 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\
2693     FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
2694
2695 #endif /* _SPARX5_SERDES_REGS_H_ */