phy/microchip/lan966x_serdes_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002
0003 #ifndef _LAN966X_SERDES_REGS_H_
0004 #define _LAN966X_SERDES_REGS_H_
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/types.h>
0008 #include <linux/bug.h>
0009
0010 enum lan966x_target {
0011     TARGET_HSIO = 32,
0012     NUM_TARGETS = 66
0013 };
0014
0015 #define __REG(...)    __VA_ARGS__
0016
0017 /*      HSIO:SD:SD_CFG */
0018 #define HSIO_SD_CFG(g)            __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 0, 0, 1, 4)
0019
0020 #define HSIO_SD_CFG_PHY_RESET                    BIT(27)
0021 #define HSIO_SD_CFG_PHY_RESET_SET(x)\
0022     FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
0023 #define HSIO_SD_CFG_PHY_RESET_GET(x)\
0024     FIELD_GET(HSIO_SD_CFG_PHY_RESET, x)
0025
0026 #define HSIO_SD_CFG_TX_RESET                     BIT(18)
0027 #define HSIO_SD_CFG_TX_RESET_SET(x)\
0028     FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
0029 #define HSIO_SD_CFG_TX_RESET_GET(x)\
0030     FIELD_GET(HSIO_SD_CFG_TX_RESET, x)
0031
0032 #define HSIO_SD_CFG_TX_RATE                      GENMASK(17, 16)
0033 #define HSIO_SD_CFG_TX_RATE_SET(x)\
0034     FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
0035 #define HSIO_SD_CFG_TX_RATE_GET(x)\
0036     FIELD_GET(HSIO_SD_CFG_TX_RATE, x)
0037
0038 #define HSIO_SD_CFG_TX_INVERT                    BIT(15)
0039 #define HSIO_SD_CFG_TX_INVERT_SET(x)\
0040     FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x)
0041 #define HSIO_SD_CFG_TX_INVERT_GET(x)\
0042     FIELD_GET(HSIO_SD_CFG_TX_INVERT, x)
0043
0044 #define HSIO_SD_CFG_TX_EN                        BIT(14)
0045 #define HSIO_SD_CFG_TX_EN_SET(x)\
0046     FIELD_PREP(HSIO_SD_CFG_TX_EN, x)
0047 #define HSIO_SD_CFG_TX_EN_GET(x)\
0048     FIELD_GET(HSIO_SD_CFG_TX_EN, x)
0049
0050 #define HSIO_SD_CFG_TX_DATA_EN                   BIT(12)
0051 #define HSIO_SD_CFG_TX_DATA_EN_SET(x)\
0052     FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x)
0053 #define HSIO_SD_CFG_TX_DATA_EN_GET(x)\
0054     FIELD_GET(HSIO_SD_CFG_TX_DATA_EN, x)
0055
0056 #define HSIO_SD_CFG_TX_CM_EN                     BIT(11)
0057 #define HSIO_SD_CFG_TX_CM_EN_SET(x)\
0058     FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x)
0059 #define HSIO_SD_CFG_TX_CM_EN_GET(x)\
0060     FIELD_GET(HSIO_SD_CFG_TX_CM_EN, x)
0061
0062 #define HSIO_SD_CFG_LANE_10BIT_SEL               BIT(10)
0063 #define HSIO_SD_CFG_LANE_10BIT_SEL_SET(x)\
0064     FIELD_PREP(HSIO_SD_CFG_LANE_10BIT_SEL, x)
0065 #define HSIO_SD_CFG_LANE_10BIT_SEL_GET(x)\
0066     FIELD_GET(HSIO_SD_CFG_LANE_10BIT_SEL, x)
0067
0068 #define HSIO_SD_CFG_RX_TERM_EN                   BIT(9)
0069 #define HSIO_SD_CFG_RX_TERM_EN_SET(x)\
0070     FIELD_PREP(HSIO_SD_CFG_RX_TERM_EN, x)
0071 #define HSIO_SD_CFG_RX_TERM_EN_GET(x)\
0072     FIELD_GET(HSIO_SD_CFG_RX_TERM_EN, x)
0073
0074 #define HSIO_SD_CFG_RX_RESET                     BIT(8)
0075 #define HSIO_SD_CFG_RX_RESET_SET(x)\
0076     FIELD_PREP(HSIO_SD_CFG_RX_RESET, x)
0077 #define HSIO_SD_CFG_RX_RESET_GET(x)\
0078     FIELD_GET(HSIO_SD_CFG_RX_RESET, x)
0079
0080 #define HSIO_SD_CFG_RX_RATE                      GENMASK(7, 6)
0081 #define HSIO_SD_CFG_RX_RATE_SET(x)\
0082     FIELD_PREP(HSIO_SD_CFG_RX_RATE, x)
0083 #define HSIO_SD_CFG_RX_RATE_GET(x)\
0084     FIELD_GET(HSIO_SD_CFG_RX_RATE, x)
0085
0086 #define HSIO_SD_CFG_RX_PLL_EN                    BIT(5)
0087 #define HSIO_SD_CFG_RX_PLL_EN_SET(x)\
0088     FIELD_PREP(HSIO_SD_CFG_RX_PLL_EN, x)
0089 #define HSIO_SD_CFG_RX_PLL_EN_GET(x)\
0090     FIELD_GET(HSIO_SD_CFG_RX_PLL_EN, x)
0091
0092 #define HSIO_SD_CFG_RX_INVERT                    BIT(3)
0093 #define HSIO_SD_CFG_RX_INVERT_SET(x)\
0094     FIELD_PREP(HSIO_SD_CFG_RX_INVERT, x)
0095 #define HSIO_SD_CFG_RX_INVERT_GET(x)\
0096     FIELD_GET(HSIO_SD_CFG_RX_INVERT, x)
0097
0098 #define HSIO_SD_CFG_RX_DATA_EN                   BIT(2)
0099 #define HSIO_SD_CFG_RX_DATA_EN_SET(x)\
0100     FIELD_PREP(HSIO_SD_CFG_RX_DATA_EN, x)
0101 #define HSIO_SD_CFG_RX_DATA_EN_GET(x)\
0102     FIELD_GET(HSIO_SD_CFG_RX_DATA_EN, x)
0103
0104 #define HSIO_SD_CFG_LANE_LOOPBK_EN               BIT(0)
0105 #define HSIO_SD_CFG_LANE_LOOPBK_EN_SET(x)\
0106     FIELD_PREP(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
0107 #define HSIO_SD_CFG_LANE_LOOPBK_EN_GET(x)\
0108     FIELD_GET(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
0109
0110 /*      HSIO:SD:MPLL_CFG */
0111 #define HSIO_MPLL_CFG(g)          __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 8, 0, 1, 4)
0112
0113 #define HSIO_MPLL_CFG_REF_SSP_EN                 BIT(18)
0114 #define HSIO_MPLL_CFG_REF_SSP_EN_SET(x)\
0115     FIELD_PREP(HSIO_MPLL_CFG_REF_SSP_EN, x)
0116 #define HSIO_MPLL_CFG_REF_SSP_EN_GET(x)\
0117     FIELD_GET(HSIO_MPLL_CFG_REF_SSP_EN, x)
0118
0119 #define HSIO_MPLL_CFG_REF_CLKDIV2                BIT(17)
0120 #define HSIO_MPLL_CFG_REF_CLKDIV2_SET(x)\
0121     FIELD_PREP(HSIO_MPLL_CFG_REF_CLKDIV2, x)
0122 #define HSIO_MPLL_CFG_REF_CLKDIV2_GET(x)\
0123     FIELD_GET(HSIO_MPLL_CFG_REF_CLKDIV2, x)
0124
0125 #define HSIO_MPLL_CFG_MPLL_EN                    BIT(16)
0126 #define HSIO_MPLL_CFG_MPLL_EN_SET(x)\
0127     FIELD_PREP(HSIO_MPLL_CFG_MPLL_EN, x)
0128 #define HSIO_MPLL_CFG_MPLL_EN_GET(x)\
0129     FIELD_GET(HSIO_MPLL_CFG_MPLL_EN, x)
0130
0131 #define HSIO_MPLL_CFG_MPLL_MULTIPLIER            GENMASK(6, 0)
0132 #define HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(x)\
0133     FIELD_PREP(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
0134 #define HSIO_MPLL_CFG_MPLL_MULTIPLIER_GET(x)\
0135     FIELD_GET(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
0136
0137 /*      HSIO:SD:SD_STAT */
0138 #define HSIO_SD_STAT(g)           __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 12, 0, 1, 4)
0139
0140 #define HSIO_SD_STAT_MPLL_STATE                  BIT(6)
0141 #define HSIO_SD_STAT_MPLL_STATE_SET(x)\
0142     FIELD_PREP(HSIO_SD_STAT_MPLL_STATE, x)
0143 #define HSIO_SD_STAT_MPLL_STATE_GET(x)\
0144     FIELD_GET(HSIO_SD_STAT_MPLL_STATE, x)
0145
0146 #define HSIO_SD_STAT_TX_STATE                    BIT(5)
0147 #define HSIO_SD_STAT_TX_STATE_SET(x)\
0148     FIELD_PREP(HSIO_SD_STAT_TX_STATE, x)
0149 #define HSIO_SD_STAT_TX_STATE_GET(x)\
0150     FIELD_GET(HSIO_SD_STAT_TX_STATE, x)
0151
0152 #define HSIO_SD_STAT_TX_CM_STATE                 BIT(2)
0153 #define HSIO_SD_STAT_TX_CM_STATE_SET(x)\
0154     FIELD_PREP(HSIO_SD_STAT_TX_CM_STATE, x)
0155 #define HSIO_SD_STAT_TX_CM_STATE_GET(x)\
0156     FIELD_GET(HSIO_SD_STAT_TX_CM_STATE, x)
0157
0158 #define HSIO_SD_STAT_RX_PLL_STATE                BIT(0)
0159 #define HSIO_SD_STAT_RX_PLL_STATE_SET(x)\
0160     FIELD_PREP(HSIO_SD_STAT_RX_PLL_STATE, x)
0161 #define HSIO_SD_STAT_RX_PLL_STATE_GET(x)\
0162     FIELD_GET(HSIO_SD_STAT_RX_PLL_STATE, x)
0163
0164 /*      HSIO:HW_CFGSTAT:HW_CFG */
0165 #define HSIO_HW_CFG               __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 0, 0, 1, 4)
0166
0167 #define HSIO_HW_CFG_RGMII_1_CFG                  BIT(15)
0168 #define HSIO_HW_CFG_RGMII_1_CFG_SET(x)\
0169     (((x) << 15) & GENMASK(15, 15))
0170 #define HSIO_HW_CFG_RGMII_1_CFG_GET(x)\
0171     FIELD_GET(HSIO_HW_CFG_RGMII_1_CFG, x)
0172
0173 #define HSIO_HW_CFG_RGMII_0_CFG                  BIT(14)
0174 #define HSIO_HW_CFG_RGMII_0_CFG_SET(x)\
0175     (((x) << 14) & GENMASK(14, 14))
0176 #define HSIO_HW_CFG_RGMII_0_CFG_GET(x)\
0177     FIELD_GET(HSIO_HW_CFG_RGMII_0_CFG, x)
0178
0179 #define HSIO_HW_CFG_RGMII_ENA                    GENMASK(13, 12)
0180 #define HSIO_HW_CFG_RGMII_ENA_SET(x)\
0181     (((x) << 12) & GENMASK(13, 12))
0182 #define HSIO_HW_CFG_RGMII_ENA_GET(x)\
0183     FIELD_GET(HSIO_HW_CFG_RGMII_ENA, x)
0184
0185 #define HSIO_HW_CFG_SD6G_0_CFG                   BIT(11)
0186 #define HSIO_HW_CFG_SD6G_0_CFG_SET(x)\
0187     (((x) << 11) & GENMASK(11, 11))
0188 #define HSIO_HW_CFG_SD6G_0_CFG_GET(x)\
0189     FIELD_GET(HSIO_HW_CFG_SD6G_0_CFG, x)
0190
0191 #define HSIO_HW_CFG_SD6G_1_CFG                   BIT(10)
0192 #define HSIO_HW_CFG_SD6G_1_CFG_SET(x)\
0193     (((x) << 10) & GENMASK(10, 10))
0194 #define HSIO_HW_CFG_SD6G_1_CFG_GET(x)\
0195     FIELD_GET(HSIO_HW_CFG_SD6G_1_CFG, x)
0196
0197 #define HSIO_HW_CFG_GMII_ENA                     GENMASK(9, 2)
0198 #define HSIO_HW_CFG_GMII_ENA_SET(x)\
0199     (((x) << 2) & GENMASK(9, 2))
0200 #define HSIO_HW_CFG_GMII_ENA_GET(x)\
0201     FIELD_GET(HSIO_HW_CFG_GMII_ENA, x)
0202
0203 #define HSIO_HW_CFG_QSGMII_ENA                   GENMASK(1, 0)
0204 #define HSIO_HW_CFG_QSGMII_ENA_SET(x)\
0205     ((x) & GENMASK(1, 0))
0206 #define HSIO_HW_CFG_QSGMII_ENA_GET(x)\
0207     FIELD_GET(HSIO_HW_CFG_QSGMII_ENA, x)
0208
0209 #endif /* _LAN966X_HSIO_REGS_H_ */