phy/mediatek/phy-mtk-ufs.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2019 MediaTek Inc.
0004  * Author: Stanley Chu <stanley.chu@mediatek.com>
0005  */
0006
0007 #include <linux/clk.h>
0008 #include <linux/delay.h>
0009 #include <linux/io.h>
0010 #include <linux/module.h>
0011 #include <linux/phy/phy.h>
0012 #include <linux/platform_device.h>
0013
0014 /* mphy register and offsets */
0015 #define MP_GLB_DIG_8C               0x008C
0016 #define FRC_PLL_ISO_EN              BIT(8)
0017 #define PLL_ISO_EN                  BIT(9)
0018 #define FRC_FRC_PWR_ON              BIT(10)
0019 #define PLL_PWR_ON                  BIT(11)
0020
0021 #define MP_LN_DIG_RX_9C             0xA09C
0022 #define FSM_DIFZ_FRC                BIT(18)
0023
0024 #define MP_LN_DIG_RX_AC             0xA0AC
0025 #define FRC_RX_SQ_EN                BIT(0)
0026 #define RX_SQ_EN                    BIT(1)
0027
0028 #define MP_LN_RX_44                 0xB044
0029 #define FRC_CDR_PWR_ON              BIT(17)
0030 #define CDR_PWR_ON                  BIT(18)
0031 #define FRC_CDR_ISO_EN              BIT(19)
0032 #define CDR_ISO_EN                  BIT(20)
0033
0034 #define UFSPHY_CLKS_CNT    2
0035
0036 struct ufs_mtk_phy {
0037     struct device *dev;
0038     void __iomem *mmio;
0039     struct clk_bulk_data clks[UFSPHY_CLKS_CNT];
0040 };
0041
0042 static inline u32 mphy_readl(struct ufs_mtk_phy *phy, u32 reg)
0043 {
0044     return readl(phy->mmio + reg);
0045 }
0046
0047 static inline void mphy_writel(struct ufs_mtk_phy *phy, u32 val, u32 reg)
0048 {
0049     writel(val, phy->mmio + reg);
0050 }
0051
0052 static void mphy_set_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
0053 {
0054     u32 val;
0055
0056     val = mphy_readl(phy, reg);
0057     val |= bit;
0058     mphy_writel(phy, val, reg);
0059 }
0060
0061 static void mphy_clr_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
0062 {
0063     u32 val;
0064
0065     val = mphy_readl(phy, reg);
0066     val &= ~bit;
0067     mphy_writel(phy, val, reg);
0068 }
0069
0070 static struct ufs_mtk_phy *get_ufs_mtk_phy(struct phy *generic_phy)
0071 {
0072     return (struct ufs_mtk_phy *)phy_get_drvdata(generic_phy);
0073 }
0074
0075 static int ufs_mtk_phy_clk_init(struct ufs_mtk_phy *phy)
0076 {
0077     struct device *dev = phy->dev;
0078     struct clk_bulk_data *clks = phy->clks;
0079
0080     clks[0].id = "unipro";
0081     clks[1].id = "mp";
0082     return devm_clk_bulk_get(dev, UFSPHY_CLKS_CNT, clks);
0083 }
0084
0085 static void ufs_mtk_phy_set_active(struct ufs_mtk_phy *phy)
0086 {
0087     /* release DA_MP_PLL_PWR_ON */
0088     mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
0089     mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
0090
0091     /* release DA_MP_PLL_ISO_EN */
0092     mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
0093     mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
0094
0095     /* release DA_MP_CDR_PWR_ON */
0096     mphy_set_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
0097     mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
0098
0099     /* release DA_MP_CDR_ISO_EN */
0100     mphy_clr_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
0101     mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
0102
0103     /* release DA_MP_RX0_SQ_EN */
0104     mphy_set_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
0105     mphy_clr_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
0106
0107     /* delay 1us to wait DIFZ stable */
0108     udelay(1);
0109
0110     /* release DIFZ */
0111     mphy_clr_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
0112 }
0113
0114 static void ufs_mtk_phy_set_deep_hibern(struct ufs_mtk_phy *phy)
0115 {
0116     /* force DIFZ */
0117     mphy_set_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
0118
0119     /* force DA_MP_RX0_SQ_EN */
0120     mphy_set_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
0121     mphy_clr_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
0122
0123     /* force DA_MP_CDR_ISO_EN */
0124     mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
0125     mphy_set_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
0126
0127     /* force DA_MP_CDR_PWR_ON */
0128     mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
0129     mphy_clr_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
0130
0131     /* force DA_MP_PLL_ISO_EN */
0132     mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
0133     mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
0134
0135     /* force DA_MP_PLL_PWR_ON */
0136     mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
0137     mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
0138 }
0139
0140 static int ufs_mtk_phy_power_on(struct phy *generic_phy)
0141 {
0142     struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy);
0143     int ret;
0144
0145     ret = clk_bulk_prepare_enable(UFSPHY_CLKS_CNT, phy->clks);
0146     if (ret)
0147         return ret;
0148
0149     ufs_mtk_phy_set_active(phy);
0150
0151     return 0;
0152 }
0153
0154 static int ufs_mtk_phy_power_off(struct phy *generic_phy)
0155 {
0156     struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy);
0157
0158     ufs_mtk_phy_set_deep_hibern(phy);
0159
0160     clk_bulk_disable_unprepare(UFSPHY_CLKS_CNT, phy->clks);
0161
0162     return 0;
0163 }
0164
0165 static const struct phy_ops ufs_mtk_phy_ops = {
0166     .power_on       = ufs_mtk_phy_power_on,
0167     .power_off      = ufs_mtk_phy_power_off,
0168     .owner          = THIS_MODULE,
0169 };
0170
0171 static int ufs_mtk_phy_probe(struct platform_device *pdev)
0172 {
0173     struct device *dev = &pdev->dev;
0174     struct phy *generic_phy;
0175     struct phy_provider *phy_provider;
0176     struct ufs_mtk_phy *phy;
0177     int ret;
0178
0179     phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
0180     if (!phy)
0181         return -ENOMEM;
0182
0183     phy->mmio = devm_platform_ioremap_resource(pdev, 0);
0184     if (IS_ERR(phy->mmio))
0185         return PTR_ERR(phy->mmio);
0186
0187     phy->dev = dev;
0188
0189     ret = ufs_mtk_phy_clk_init(phy);
0190     if (ret)
0191         return ret;
0192
0193     generic_phy = devm_phy_create(dev, NULL, &ufs_mtk_phy_ops);
0194     if (IS_ERR(generic_phy))
0195         return PTR_ERR(generic_phy);
0196
0197     phy_set_drvdata(generic_phy, phy);
0198
0199     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0200
0201     return PTR_ERR_OR_ZERO(phy_provider);
0202 }
0203
0204 static const struct of_device_id ufs_mtk_phy_of_match[] = {
0205     {.compatible = "mediatek,mt8183-ufsphy"},
0206     {},
0207 };
0208 MODULE_DEVICE_TABLE(of, ufs_mtk_phy_of_match);
0209
0210 static struct platform_driver ufs_mtk_phy_driver = {
0211     .probe = ufs_mtk_phy_probe,
0212     .driver = {
0213         .of_match_table = ufs_mtk_phy_of_match,
0214         .name = "ufs_mtk_phy",
0215     },
0216 };
0217 module_platform_driver(ufs_mtk_phy_driver);
0218
0219 MODULE_DESCRIPTION("Universal Flash Storage (UFS) MediaTek MPHY");
0220 MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
0221 MODULE_LICENSE("GPL v2");