phy/mediatek/phy-mtk-pcie.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2022 MediaTek Inc.
0004  * Author: Jianjun Wang <jianjun.wang@mediatek.com>
0005  */
0006
0007 #include <linux/bitfield.h>
0008 #include <linux/module.h>
0009 #include <linux/nvmem-consumer.h>
0010 #include <linux/of_device.h>
0011 #include <linux/phy/phy.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/slab.h>
0014
0015 #include "phy-mtk-io.h"
0016
0017 #define PEXTP_ANA_GLB_00_REG        0x9000
0018 /* Internal Resistor Selection of TX Bias Current */
0019 #define EFUSE_GLB_INTR_SEL      GENMASK(28, 24)
0020
0021 #define PEXTP_ANA_LN0_TRX_REG       0xa000
0022
0023 #define PEXTP_ANA_TX_REG        0x04
0024 /* TX PMOS impedance selection */
0025 #define EFUSE_LN_TX_PMOS_SEL        GENMASK(5, 2)
0026 /* TX NMOS impedance selection */
0027 #define EFUSE_LN_TX_NMOS_SEL        GENMASK(11, 8)
0028
0029 #define PEXTP_ANA_RX_REG        0x3c
0030 /* RX impedance selection */
0031 #define EFUSE_LN_RX_SEL         GENMASK(3, 0)
0032
0033 #define PEXTP_ANA_LANE_OFFSET       0x100
0034
0035 /**
0036  * struct mtk_pcie_lane_efuse - eFuse data for each lane
0037  * @tx_pmos: TX PMOS impedance selection data
0038  * @tx_nmos: TX NMOS impedance selection data
0039  * @rx_data: RX impedance selection data
0040  * @lane_efuse_supported: software eFuse data is supported for this lane
0041  */
0042 struct mtk_pcie_lane_efuse {
0043     u32 tx_pmos;
0044     u32 tx_nmos;
0045     u32 rx_data;
0046     bool lane_efuse_supported;
0047 };
0048
0049 /**
0050  * struct mtk_pcie_phy_data - phy data for each SoC
0051  * @num_lanes: supported lane numbers
0052  * @sw_efuse_supported: support software to load eFuse data
0053  */
0054 struct mtk_pcie_phy_data {
0055     int num_lanes;
0056     bool sw_efuse_supported;
0057 };
0058
0059 /**
0060  * struct mtk_pcie_phy - PCIe phy driver main structure
0061  * @dev: pointer to device
0062  * @phy: pointer to generic phy
0063  * @sif_base: IO mapped register base address of system interface
0064  * @data: pointer to SoC dependent data
0065  * @sw_efuse_en: software eFuse enable status
0066  * @efuse_glb_intr: internal resistor selection of TX bias current data
0067  * @efuse: pointer to eFuse data for each lane
0068  */
0069 struct mtk_pcie_phy {
0070     struct device *dev;
0071     struct phy *phy;
0072     void __iomem *sif_base;
0073     const struct mtk_pcie_phy_data *data;
0074
0075     bool sw_efuse_en;
0076     u32 efuse_glb_intr;
0077     struct mtk_pcie_lane_efuse *efuse;
0078 };
0079
0080 static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
0081                     unsigned int lane)
0082 {
0083     struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
0084     void __iomem *addr;
0085
0086     if (!data->lane_efuse_supported)
0087         return;
0088
0089     addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
0090            lane * PEXTP_ANA_LANE_OFFSET;
0091
0092     mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL,
0093                 FIELD_PREP(EFUSE_LN_TX_PMOS_SEL, data->tx_pmos));
0094
0095     mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL,
0096                 FIELD_PREP(EFUSE_LN_TX_NMOS_SEL, data->tx_nmos));
0097
0098     mtk_phy_update_bits(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL,
0099                 FIELD_PREP(EFUSE_LN_RX_SEL, data->rx_data));
0100 }
0101
0102 /**
0103  * mtk_pcie_phy_init() - Initialize the phy
0104  * @phy: the phy to be initialized
0105  *
0106  * Initialize the phy by setting the efuse data.
0107  * The hardware settings will be reset during suspend, it should be
0108  * reinitialized when the consumer calls phy_init() again on resume.
0109  */
0110 static int mtk_pcie_phy_init(struct phy *phy)
0111 {
0112     struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
0113     int i;
0114
0115     if (!pcie_phy->sw_efuse_en)
0116         return 0;
0117
0118     /* Set global data */
0119     mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
0120                 EFUSE_GLB_INTR_SEL,
0121                 FIELD_PREP(EFUSE_GLB_INTR_SEL, pcie_phy->efuse_glb_intr));
0122
0123     for (i = 0; i < pcie_phy->data->num_lanes; i++)
0124         mtk_pcie_efuse_set_lane(pcie_phy, i);
0125
0126     return 0;
0127 }
0128
0129 static const struct phy_ops mtk_pcie_phy_ops = {
0130     .init   = mtk_pcie_phy_init,
0131     .owner  = THIS_MODULE,
0132 };
0133
0134 static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
0135                     unsigned int lane)
0136 {
0137     struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
0138     struct device *dev = pcie_phy->dev;
0139     char efuse_id[16];
0140     int ret;
0141
0142     snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
0143     ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
0144     if (ret)
0145         return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
0146
0147     snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
0148     ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
0149     if (ret)
0150         return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
0151
0152     snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
0153     ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
0154     if (ret)
0155         return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
0156
0157     if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
0158         return dev_err_probe(dev, -EINVAL,
0159                      "No eFuse data found for lane%d, but dts enable it\n",
0160                      lane);
0161
0162     efuse->lane_efuse_supported = true;
0163
0164     return 0;
0165 }
0166
0167 static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
0168 {
0169     struct device *dev = pcie_phy->dev;
0170     bool nvmem_enabled;
0171     int ret, i;
0172
0173     /* nvmem data is optional */
0174     nvmem_enabled = device_property_present(dev, "nvmem-cells");
0175     if (!nvmem_enabled)
0176         return 0;
0177
0178     ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
0179                           &pcie_phy->efuse_glb_intr);
0180     if (ret)
0181         return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
0182
0183     pcie_phy->sw_efuse_en = true;
0184
0185     pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
0186                        sizeof(*pcie_phy->efuse), GFP_KERNEL);
0187     if (!pcie_phy->efuse)
0188         return -ENOMEM;
0189
0190     for (i = 0; i < pcie_phy->data->num_lanes; i++) {
0191         ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
0192         if (ret)
0193             return ret;
0194     }
0195
0196     return 0;
0197 }
0198
0199 static int mtk_pcie_phy_probe(struct platform_device *pdev)
0200 {
0201     struct device *dev = &pdev->dev;
0202     struct phy_provider *provider;
0203     struct mtk_pcie_phy *pcie_phy;
0204     int ret;
0205
0206     pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
0207     if (!pcie_phy)
0208         return -ENOMEM;
0209
0210     pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
0211     if (IS_ERR(pcie_phy->sif_base))
0212         return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
0213                      "Failed to map phy-sif base\n");
0214
0215     pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
0216     if (IS_ERR(pcie_phy->phy))
0217         return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
0218                      "Failed to create PCIe phy\n");
0219
0220     pcie_phy->dev = dev;
0221     pcie_phy->data = of_device_get_match_data(dev);
0222     if (!pcie_phy->data)
0223         return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
0224
0225     if (pcie_phy->data->sw_efuse_supported) {
0226         /*
0227          * Failed to read the efuse data is not a fatal problem,
0228          * ignore the failure and keep going.
0229          */
0230         ret = mtk_pcie_read_efuse(pcie_phy);
0231         if (ret == -EPROBE_DEFER || ret == -ENOMEM)
0232             return ret;
0233     }
0234
0235     phy_set_drvdata(pcie_phy->phy, pcie_phy);
0236
0237     provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0238     if (IS_ERR(provider))
0239         return dev_err_probe(dev, PTR_ERR(provider),
0240                      "PCIe phy probe failed\n");
0241
0242     return 0;
0243 }
0244
0245 static const struct mtk_pcie_phy_data mt8195_data = {
0246     .num_lanes = 2,
0247     .sw_efuse_supported = true,
0248 };
0249
0250 static const struct of_device_id mtk_pcie_phy_of_match[] = {
0251     { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
0252     { },
0253 };
0254 MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
0255
0256 static struct platform_driver mtk_pcie_phy_driver = {
0257     .probe  = mtk_pcie_phy_probe,
0258     .driver = {
0259         .name = "mtk-pcie-phy",
0260         .of_match_table = mtk_pcie_phy_of_match,
0261     },
0262 };
0263 module_platform_driver(mtk_pcie_phy_driver);
0264
0265 MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
0266 MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
0267 MODULE_LICENSE("GPL");