phy/mediatek/phy-mtk-mipi-dsi.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2019 MediaTek Inc.
0004  * Author: Jitao Shi <jitao.shi@mediatek.com>
0005  */
0006
0007 #ifndef _MTK_MIPI_TX_H
0008 #define _MTK_MIPI_TX_H
0009
0010 #include <linux/clk.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/delay.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/nvmem-consumer.h>
0016 #include <linux/of_device.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/phy/phy.h>
0019 #include <linux/slab.h>
0020
0021 struct mtk_mipitx_data {
0022     const u32 mppll_preserve;
0023     const struct clk_ops *mipi_tx_clk_ops;
0024     void (*mipi_tx_enable_signal)(struct phy *phy);
0025     void (*mipi_tx_disable_signal)(struct phy *phy);
0026 };
0027
0028 struct mtk_mipi_tx {
0029     struct device *dev;
0030     void __iomem *regs;
0031     u32 data_rate;
0032     u32 mipitx_drive;
0033     u32 rt_code[5];
0034     const struct mtk_mipitx_data *driver_data;
0035     struct clk_hw pll_hw;
0036     struct clk *pll;
0037 };
0038
0039 struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw);
0040 void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
0041 void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
0042 void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 mask,
0043                  u32 data);
0044 int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0045                  unsigned long parent_rate);
0046 unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
0047                       unsigned long parent_rate);
0048
0049 extern const struct mtk_mipitx_data mt2701_mipitx_data;
0050 extern const struct mtk_mipitx_data mt8173_mipitx_data;
0051 extern const struct mtk_mipitx_data mt8183_mipitx_data;
0052
0053 #endif