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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2021 MediaTek Inc.
0004  *
0005  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
0006  */
0007 
0008 #ifndef __PHY_MTK_H__
0009 #define __PHY_MTK_H__
0010 
0011 #include <linux/io.h>
0012 
0013 static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits)
0014 {
0015     u32 tmp = readl(reg);
0016 
0017     tmp &= ~bits;
0018     writel(tmp, reg);
0019 }
0020 
0021 static inline void mtk_phy_set_bits(void __iomem *reg, u32 bits)
0022 {
0023     u32 tmp = readl(reg);
0024 
0025     tmp |= bits;
0026     writel(tmp, reg);
0027 }
0028 
0029 static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val)
0030 {
0031     u32 tmp = readl(reg);
0032 
0033     tmp &= ~mask;
0034     tmp |= val & mask;
0035     writel(tmp, reg);
0036 }
0037 
0038 #endif