phy/mediatek/phy-mtk-hdmi.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2018 MediaTek Inc.
0004  * Author: Chunhui Dai <chunhui.dai@mediatek.com>
0005  */
0006
0007 #ifndef _MTK_HDMI_PHY_H
0008 #define _MTK_HDMI_PHY_H
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/delay.h>
0012 #include <linux/io.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/module.h>
0015 #include <linux/of_device.h>
0016 #include <linux/phy/phy.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/types.h>
0019
0020 struct mtk_hdmi_phy;
0021
0022 struct mtk_hdmi_phy_conf {
0023     unsigned long flags;
0024     bool pll_default_off;
0025     const struct clk_ops *hdmi_phy_clk_ops;
0026     void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
0027     void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
0028 };
0029
0030 struct mtk_hdmi_phy {
0031     void __iomem *regs;
0032     struct device *dev;
0033     struct mtk_hdmi_phy_conf *conf;
0034     struct clk *pll;
0035     struct clk_hw pll_hw;
0036     unsigned long pll_rate;
0037     unsigned char drv_imp_clk;
0038     unsigned char drv_imp_d2;
0039     unsigned char drv_imp_d1;
0040     unsigned char drv_imp_d0;
0041     unsigned int ibias;
0042     unsigned int ibias_up;
0043 };
0044
0045 void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
0046                  u32 bits);
0047 void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
0048                u32 bits);
0049 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
0050                u32 val, u32 mask);
0051 struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
0052
0053 extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
0054 extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
0055
0056 #endif /* _MTK_HDMI_PHY_H */