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0007 #include "phy-mtk-hdmi.h"
0008
0009 static int mtk_hdmi_phy_power_on(struct phy *phy);
0010 static int mtk_hdmi_phy_power_off(struct phy *phy);
0011
0012 static const struct phy_ops mtk_hdmi_phy_dev_ops = {
0013 .power_on = mtk_hdmi_phy_power_on,
0014 .power_off = mtk_hdmi_phy_power_off,
0015 .owner = THIS_MODULE,
0016 };
0017
0018 void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
0019 u32 bits)
0020 {
0021 void __iomem *reg = hdmi_phy->regs + offset;
0022 u32 tmp;
0023
0024 tmp = readl(reg);
0025 tmp &= ~bits;
0026 writel(tmp, reg);
0027 }
0028
0029 void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
0030 u32 bits)
0031 {
0032 void __iomem *reg = hdmi_phy->regs + offset;
0033 u32 tmp;
0034
0035 tmp = readl(reg);
0036 tmp |= bits;
0037 writel(tmp, reg);
0038 }
0039
0040 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
0041 u32 val, u32 mask)
0042 {
0043 void __iomem *reg = hdmi_phy->regs + offset;
0044 u32 tmp;
0045
0046 tmp = readl(reg);
0047 tmp = (tmp & ~mask) | (val & mask);
0048 writel(tmp, reg);
0049 }
0050
0051 inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
0052 {
0053 return container_of(hw, struct mtk_hdmi_phy, pll_hw);
0054 }
0055
0056 static int mtk_hdmi_phy_power_on(struct phy *phy)
0057 {
0058 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
0059 int ret;
0060
0061 ret = clk_prepare_enable(hdmi_phy->pll);
0062 if (ret < 0)
0063 return ret;
0064
0065 hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
0066 return 0;
0067 }
0068
0069 static int mtk_hdmi_phy_power_off(struct phy *phy)
0070 {
0071 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
0072
0073 hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
0074 clk_disable_unprepare(hdmi_phy->pll);
0075
0076 return 0;
0077 }
0078
0079 static const struct phy_ops *
0080 mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
0081 {
0082 if (hdmi_phy && hdmi_phy->conf &&
0083 hdmi_phy->conf->hdmi_phy_enable_tmds &&
0084 hdmi_phy->conf->hdmi_phy_disable_tmds)
0085 return &mtk_hdmi_phy_dev_ops;
0086
0087 if (hdmi_phy)
0088 dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
0089 return NULL;
0090 }
0091
0092 static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy,
0093 struct clk_init_data *clk_init)
0094 {
0095 clk_init->flags = hdmi_phy->conf->flags;
0096 clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
0097 }
0098
0099 static int mtk_hdmi_phy_probe(struct platform_device *pdev)
0100 {
0101 struct device *dev = &pdev->dev;
0102 struct mtk_hdmi_phy *hdmi_phy;
0103 struct clk *ref_clk;
0104 const char *ref_clk_name;
0105 struct clk_init_data clk_init = {
0106 .num_parents = 1,
0107 .parent_names = (const char * const *)&ref_clk_name,
0108 };
0109
0110 struct phy *phy;
0111 struct phy_provider *phy_provider;
0112 int ret;
0113
0114 hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
0115 if (!hdmi_phy)
0116 return -ENOMEM;
0117
0118 hdmi_phy->regs = devm_platform_ioremap_resource(pdev, 0);
0119 if (IS_ERR(hdmi_phy->regs))
0120 return PTR_ERR(hdmi_phy->regs);
0121
0122 ref_clk = devm_clk_get(dev, "pll_ref");
0123 if (IS_ERR(ref_clk))
0124 return dev_err_probe(dev, PTR_ERR(ref_clk),
0125 "Failed to get PLL reference clock\n");
0126
0127 ref_clk_name = __clk_get_name(ref_clk);
0128
0129 ret = of_property_read_string(dev->of_node, "clock-output-names",
0130 &clk_init.name);
0131 if (ret < 0)
0132 return dev_err_probe(dev, ret, "Failed to read clock-output-names\n");
0133
0134 hdmi_phy->dev = dev;
0135 hdmi_phy->conf =
0136 (struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
0137 mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
0138 hdmi_phy->pll_hw.init = &clk_init;
0139 hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
0140 if (IS_ERR(hdmi_phy->pll))
0141 return dev_err_probe(dev, PTR_ERR(hdmi_phy->pll),
0142 "Failed to register PLL\n");
0143
0144 ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
0145 &hdmi_phy->ibias);
0146 if (ret < 0)
0147 return dev_err_probe(dev, ret, "Failed to get ibias\n");
0148
0149 ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
0150 &hdmi_phy->ibias_up);
0151 if (ret < 0)
0152 return dev_err_probe(dev, ret, "Failed to get ibias_up\n");
0153
0154 dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
0155 hdmi_phy->drv_imp_clk = 0x30;
0156 hdmi_phy->drv_imp_d2 = 0x30;
0157 hdmi_phy->drv_imp_d1 = 0x30;
0158 hdmi_phy->drv_imp_d0 = 0x30;
0159
0160 phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
0161 if (IS_ERR(phy))
0162 return dev_err_probe(dev, PTR_ERR(phy), "Cannot create HDMI PHY\n");
0163
0164 phy_set_drvdata(phy, hdmi_phy);
0165
0166 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0167 if (IS_ERR(phy_provider))
0168 return dev_err_probe(dev, PTR_ERR(phy_provider),
0169 "Failed to register HDMI PHY\n");
0170
0171 if (hdmi_phy->conf->pll_default_off)
0172 hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
0173
0174 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
0175 hdmi_phy->pll);
0176 }
0177
0178 static const struct of_device_id mtk_hdmi_phy_match[] = {
0179 { .compatible = "mediatek,mt2701-hdmi-phy",
0180 .data = &mtk_hdmi_phy_2701_conf,
0181 },
0182 { .compatible = "mediatek,mt8173-hdmi-phy",
0183 .data = &mtk_hdmi_phy_8173_conf,
0184 },
0185 {},
0186 };
0187 MODULE_DEVICE_TABLE(of, mtk_hdmi_phy_match);
0188
0189 static struct platform_driver mtk_hdmi_phy_driver = {
0190 .probe = mtk_hdmi_phy_probe,
0191 .driver = {
0192 .name = "mediatek-hdmi-phy",
0193 .of_match_table = mtk_hdmi_phy_match,
0194 },
0195 };
0196 module_platform_driver(mtk_hdmi_phy_driver);
0197
0198 MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
0199 MODULE_LICENSE("GPL v2");
