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0007 #include "phy-mtk-hdmi.h"
0008
0009 #define HDMI_CON0 0x00
0010 #define RG_HDMITX_PLL_EN BIT(31)
0011 #define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
0012 #define PLL_FBKDIV_SHIFT 24
0013 #define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
0014 #define PLL_FBKSEL_SHIFT 22
0015 #define RG_HDMITX_PLL_PREDIV (0x3 << 20)
0016 #define PREDIV_SHIFT 20
0017 #define RG_HDMITX_PLL_POSDIV (0x3 << 18)
0018 #define POSDIV_SHIFT 18
0019 #define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
0020 #define RG_HDMITX_PLL_IR (0xf << 12)
0021 #define PLL_IR_SHIFT 12
0022 #define RG_HDMITX_PLL_IC (0xf << 8)
0023 #define PLL_IC_SHIFT 8
0024 #define RG_HDMITX_PLL_BP (0xf << 4)
0025 #define PLL_BP_SHIFT 4
0026 #define RG_HDMITX_PLL_BR (0x3 << 2)
0027 #define PLL_BR_SHIFT 2
0028 #define RG_HDMITX_PLL_BC (0x3 << 0)
0029 #define PLL_BC_SHIFT 0
0030 #define HDMI_CON1 0x04
0031 #define RG_HDMITX_PLL_DIVEN (0x7 << 29)
0032 #define PLL_DIVEN_SHIFT 29
0033 #define RG_HDMITX_PLL_AUTOK_EN BIT(28)
0034 #define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
0035 #define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
0036 #define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
0037 #define RG_HDMITX_PLL_BAND (0x3f << 16)
0038 #define RG_HDMITX_PLL_REF_SEL BIT(15)
0039 #define RG_HDMITX_PLL_BIAS_EN BIT(14)
0040 #define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
0041 #define RG_HDMITX_PLL_TXDIV_EN BIT(12)
0042 #define RG_HDMITX_PLL_TXDIV (0x3 << 10)
0043 #define PLL_TXDIV_SHIFT 10
0044 #define RG_HDMITX_PLL_LVROD_EN BIT(9)
0045 #define RG_HDMITX_PLL_MONVC_EN BIT(8)
0046 #define RG_HDMITX_PLL_MONCK_EN BIT(7)
0047 #define RG_HDMITX_PLL_MONREF_EN BIT(6)
0048 #define RG_HDMITX_PLL_TST_EN BIT(5)
0049 #define RG_HDMITX_PLL_TST_CK_EN BIT(4)
0050 #define RG_HDMITX_PLL_TST_SEL (0xf << 0)
0051 #define HDMI_CON2 0x08
0052 #define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
0053 #define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
0054 #define RG_HDMITX_EN_TX_CKLDO BIT(0)
0055 #define HDMI_CON3 0x0c
0056 #define RG_HDMITX_SER_EN (0xf << 28)
0057 #define RG_HDMITX_PRD_EN (0xf << 24)
0058 #define RG_HDMITX_PRD_IMP_EN (0xf << 20)
0059 #define RG_HDMITX_DRV_EN (0xf << 16)
0060 #define RG_HDMITX_DRV_IMP_EN (0xf << 12)
0061 #define DRV_IMP_EN_SHIFT 12
0062 #define RG_HDMITX_MHLCK_FORCE BIT(10)
0063 #define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
0064 #define RG_HDMITX_MHLCK_EN BIT(8)
0065 #define RG_HDMITX_SER_DIN_SEL (0xf << 4)
0066 #define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
0067 #define RG_HDMITX_SER_BIST_TOG BIT(2)
0068 #define RG_HDMITX_SER_DIN_TOG BIT(1)
0069 #define RG_HDMITX_SER_CLKDIG_INV BIT(0)
0070 #define HDMI_CON4 0x10
0071 #define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
0072 #define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
0073 #define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
0074 #define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
0075 #define PRD_IBIAS_CLK_SHIFT 24
0076 #define PRD_IBIAS_D2_SHIFT 16
0077 #define PRD_IBIAS_D1_SHIFT 8
0078 #define PRD_IBIAS_D0_SHIFT 0
0079 #define HDMI_CON5 0x14
0080 #define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
0081 #define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
0082 #define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
0083 #define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
0084 #define DRV_IBIAS_CLK_SHIFT 24
0085 #define DRV_IBIAS_D2_SHIFT 16
0086 #define DRV_IBIAS_D1_SHIFT 8
0087 #define DRV_IBIAS_D0_SHIFT 0
0088 #define HDMI_CON6 0x18
0089 #define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
0090 #define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
0091 #define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
0092 #define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
0093 #define DRV_IMP_CLK_SHIFT 24
0094 #define DRV_IMP_D2_SHIFT 16
0095 #define DRV_IMP_D1_SHIFT 8
0096 #define DRV_IMP_D0_SHIFT 0
0097 #define HDMI_CON7 0x1c
0098 #define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
0099 #define RG_HDMITX_SER_DIN (0x3ff << 16)
0100 #define RG_HDMITX_CHLDC_TST (0xf << 12)
0101 #define RG_HDMITX_CHLCK_TST (0xf << 8)
0102 #define RG_HDMITX_RESERVE (0xff << 0)
0103 #define HDMI_CON8 0x20
0104 #define RGS_HDMITX_2T1_LEV (0xf << 16)
0105 #define RGS_HDMITX_2T1_EDG (0xf << 12)
0106 #define RGS_HDMITX_5T1_LEV (0xf << 8)
0107 #define RGS_HDMITX_5T1_EDG (0xf << 4)
0108 #define RGS_HDMITX_PLUG_TST BIT(0)
0109
0110 static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
0111 {
0112 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
0113
0114 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
0115 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
0116 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
0117 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
0118 usleep_range(100, 150);
0119 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
0120 usleep_range(100, 150);
0121 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
0122 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
0123
0124 return 0;
0125 }
0126
0127 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
0128 {
0129 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
0130
0131 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
0132 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
0133 usleep_range(100, 150);
0134 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
0135 usleep_range(100, 150);
0136 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
0137 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
0138 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
0139 usleep_range(100, 150);
0140 }
0141
0142 static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0143 unsigned long *parent_rate)
0144 {
0145 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
0146
0147 hdmi_phy->pll_rate = rate;
0148 if (rate <= 74250000)
0149 *parent_rate = rate;
0150 else
0151 *parent_rate = rate / 2;
0152
0153 return rate;
0154 }
0155
0156 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0157 unsigned long parent_rate)
0158 {
0159 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
0160 unsigned int pre_div;
0161 unsigned int div;
0162 unsigned int pre_ibias;
0163 unsigned int hdmi_ibias;
0164 unsigned int imp_en;
0165
0166 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
0167 rate, parent_rate);
0168
0169 if (rate <= 27000000) {
0170 pre_div = 0;
0171 div = 3;
0172 } else if (rate <= 74250000) {
0173 pre_div = 1;
0174 div = 2;
0175 } else {
0176 pre_div = 1;
0177 div = 1;
0178 }
0179
0180 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
0181 (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
0182 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
0183 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
0184 (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
0185 RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
0186 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
0187 (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
0188 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
0189 (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
0190 RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
0191 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
0192 (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
0193 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
0194 (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
0195 (0x1 << PLL_BR_SHIFT),
0196 RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
0197 RG_HDMITX_PLL_BR);
0198 if (rate < 165000000) {
0199 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
0200 RG_HDMITX_PRD_IMP_EN);
0201 pre_ibias = 0x3;
0202 imp_en = 0x0;
0203 hdmi_ibias = hdmi_phy->ibias;
0204 } else {
0205 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
0206 RG_HDMITX_PRD_IMP_EN);
0207 pre_ibias = 0x6;
0208 imp_en = 0xf;
0209 hdmi_ibias = hdmi_phy->ibias_up;
0210 }
0211 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
0212 (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
0213 (pre_ibias << PRD_IBIAS_D2_SHIFT) |
0214 (pre_ibias << PRD_IBIAS_D1_SHIFT) |
0215 (pre_ibias << PRD_IBIAS_D0_SHIFT),
0216 RG_HDMITX_PRD_IBIAS_CLK |
0217 RG_HDMITX_PRD_IBIAS_D2 |
0218 RG_HDMITX_PRD_IBIAS_D1 |
0219 RG_HDMITX_PRD_IBIAS_D0);
0220 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
0221 (imp_en << DRV_IMP_EN_SHIFT),
0222 RG_HDMITX_DRV_IMP_EN);
0223 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
0224 (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
0225 (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
0226 (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
0227 (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
0228 RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
0229 RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
0230 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
0231 (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
0232 (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
0233 (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
0234 (hdmi_ibias << DRV_IBIAS_D0_SHIFT),
0235 RG_HDMITX_DRV_IBIAS_CLK |
0236 RG_HDMITX_DRV_IBIAS_D2 |
0237 RG_HDMITX_DRV_IBIAS_D1 |
0238 RG_HDMITX_DRV_IBIAS_D0);
0239 return 0;
0240 }
0241
0242 static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
0243 unsigned long parent_rate)
0244 {
0245 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
0246
0247 return hdmi_phy->pll_rate;
0248 }
0249
0250 static const struct clk_ops mtk_hdmi_phy_pll_ops = {
0251 .prepare = mtk_hdmi_pll_prepare,
0252 .unprepare = mtk_hdmi_pll_unprepare,
0253 .set_rate = mtk_hdmi_pll_set_rate,
0254 .round_rate = mtk_hdmi_pll_round_rate,
0255 .recalc_rate = mtk_hdmi_pll_recalc_rate,
0256 };
0257
0258 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
0259 {
0260 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
0261 RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
0262 RG_HDMITX_DRV_EN);
0263 usleep_range(100, 150);
0264 }
0265
0266 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
0267 {
0268 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
0269 RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
0270 RG_HDMITX_SER_EN);
0271 }
0272
0273 struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
0274 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
0275 .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
0276 .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
0277 .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
0278 };
0279
0280 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
0281 MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
0282 MODULE_LICENSE("GPL v2");
