phy/mediatek/phy-mtk-dp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MediaTek DisplayPort PHY driver
0004  *
0005  * Copyright (c) 2022, BayLibre Inc.
0006  * Copyright (c) 2022, MediaTek Inc.
0007  */
0008
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/of.h>
0013 #include <linux/phy/phy.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/regmap.h>
0016
0017 #define PHY_OFFSET          0x1000
0018
0019 #define MTK_DP_PHY_DIG_PLL_CTL_1    (PHY_OFFSET + 0x14)
0020 #define TPLL_SSC_EN         BIT(3)
0021
0022 #define MTK_DP_PHY_DIG_BIT_RATE     (PHY_OFFSET + 0x3C)
0023 #define BIT_RATE_RBR            0
0024 #define BIT_RATE_HBR            1
0025 #define BIT_RATE_HBR2           2
0026 #define BIT_RATE_HBR3           3
0027
0028 #define MTK_DP_PHY_DIG_SW_RST       (PHY_OFFSET + 0x38)
0029 #define DP_GLB_SW_RST_PHYD      BIT(0)
0030
0031 #define MTK_DP_LANE0_DRIVING_PARAM_3        (PHY_OFFSET + 0x138)
0032 #define MTK_DP_LANE1_DRIVING_PARAM_3        (PHY_OFFSET + 0x238)
0033 #define MTK_DP_LANE2_DRIVING_PARAM_3        (PHY_OFFSET + 0x338)
0034 #define MTK_DP_LANE3_DRIVING_PARAM_3        (PHY_OFFSET + 0x438)
0035 #define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT   BIT(4)
0036 #define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT   (BIT(10) | BIT(12))
0037 #define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT   GENMASK(20, 19)
0038 #define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT   GENMASK(29, 29)
0039 #define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
0040                  XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
0041                  XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
0042                  XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
0043
0044 #define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT   GENMASK(4, 3)
0045 #define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT   GENMASK(12, 9)
0046 #define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT   (BIT(18) | BIT(21))
0047 #define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT   GENMASK(29, 29)
0048 #define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
0049                  XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
0050                  XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
0051                  XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
0052
0053 #define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT   (BIT(3) | BIT(5))
0054 #define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT   GENMASK(13, 12)
0055 #define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
0056                  XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
0057
0058 #define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT  0
0059 #define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT  GENMASK(10, 10)
0060 #define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT  GENMASK(19, 19)
0061 #define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT  GENMASK(28, 28)
0062 #define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
0063                  XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
0064                  XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
0065                  XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
0066
0067 #define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT  0
0068 #define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT  GENMASK(10, 9)
0069 #define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT  GENMASK(19, 18)
0070 #define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT  0
0071 #define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
0072                  XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
0073                  XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
0074                  XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
0075
0076 #define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT  GENMASK(3, 3)
0077 #define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT  0
0078 #define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
0079                  XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
0080
0081 struct mtk_dp_phy {
0082     struct regmap *regs;
0083 };
0084
0085 static int mtk_dp_phy_init(struct phy *phy)
0086 {
0087     struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
0088     u32 driving_params[] = {
0089         DRIVING_PARAM_3_DEFAULT,
0090         DRIVING_PARAM_4_DEFAULT,
0091         DRIVING_PARAM_5_DEFAULT,
0092         DRIVING_PARAM_6_DEFAULT,
0093         DRIVING_PARAM_7_DEFAULT,
0094         DRIVING_PARAM_8_DEFAULT
0095     };
0096
0097     regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3,
0098               driving_params, ARRAY_SIZE(driving_params));
0099     regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3,
0100               driving_params, ARRAY_SIZE(driving_params));
0101     regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3,
0102               driving_params, ARRAY_SIZE(driving_params));
0103     regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3,
0104               driving_params, ARRAY_SIZE(driving_params));
0105
0106     return 0;
0107 }
0108
0109 static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
0110 {
0111     struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
0112     u32 val;
0113
0114     if (opts->dp.set_rate) {
0115         switch (opts->dp.link_rate) {
0116         default:
0117             dev_err(&phy->dev,
0118                 "Implementation error, unknown linkrate %x\n",
0119                 opts->dp.link_rate);
0120             return -EINVAL;
0121         case 1620:
0122             val = BIT_RATE_RBR;
0123             break;
0124         case 2700:
0125             val = BIT_RATE_HBR;
0126             break;
0127         case 5400:
0128             val = BIT_RATE_HBR2;
0129             break;
0130         case 8100:
0131             val = BIT_RATE_HBR3;
0132             break;
0133         }
0134         regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val);
0135     }
0136
0137     regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
0138                TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
0139
0140     return 0;
0141 }
0142
0143 static int mtk_dp_phy_reset(struct phy *phy)
0144 {
0145     struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
0146
0147     regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST,
0148                DP_GLB_SW_RST_PHYD, 0);
0149     usleep_range(50, 200);
0150     regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST,
0151                DP_GLB_SW_RST_PHYD, 1);
0152
0153     return 0;
0154 }
0155
0156 static const struct phy_ops mtk_dp_phy_dev_ops = {
0157     .init = mtk_dp_phy_init,
0158     .configure = mtk_dp_phy_configure,
0159     .reset = mtk_dp_phy_reset,
0160     .owner = THIS_MODULE,
0161 };
0162
0163 static int mtk_dp_phy_probe(struct platform_device *pdev)
0164 {
0165     struct device *dev = &pdev->dev;
0166     struct mtk_dp_phy *dp_phy;
0167     struct phy *phy;
0168     struct regmap *regs;
0169
0170     regs = *(struct regmap **)dev->platform_data;
0171     if (!regs)
0172         return dev_err_probe(dev, EINVAL,
0173                      "No data passed, requires struct regmap**\n");
0174
0175     dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL);
0176     if (!dp_phy)
0177         return -ENOMEM;
0178
0179     dp_phy->regs = regs;
0180     phy = devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops);
0181     if (IS_ERR(phy))
0182         return dev_err_probe(dev, PTR_ERR(phy),
0183                      "Failed to create DP PHY\n");
0184
0185     phy_set_drvdata(phy, dp_phy);
0186     if (!dev->of_node)
0187         phy_create_lookup(phy, "dp", dev_name(dev));
0188
0189     return 0;
0190 }
0191
0192 static struct platform_driver mtk_dp_phy_driver = {
0193     .probe = mtk_dp_phy_probe,
0194     .driver = {
0195         .name = "mediatek-dp-phy",
0196     },
0197 };
0198 module_platform_driver(mtk_dp_phy_driver);
0199
0200 MODULE_AUTHOR("Markus Schneider-Pargmann <msp@baylibre.com>");
0201 MODULE_DESCRIPTION("MediaTek DP PHY Driver");
0202 MODULE_LICENSE("GPL");